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Lab Exercise #7: Decoders, Multiplexors, Shifters and Encoders

Revision: October 12, 2002

Overview

This lab introduces several circuits that are frequently used by digital designers: a data selector (also
called a multiplexor or just "mux"); a decoder; an encoder; and a shifter. These circuits are each good
examples of modular or macro circuit components. These components can be used by themselves to
implement certain simple functions, but they are most often used as building blocks in the
implementation of more complex digital circuits. In this lab, these circuits will be implemented
directly, and then used as modules to create more complex circuits.

Background

Multiplexors

A multiplexor (or mux) has two different types of inputs, data inputs and select
inputs, but only one output. A mux functions by connecting one of its input lines to I0
its output – which input is connected to the output is determined by the select I1
inputs. For example, if it is desired that input signal I2 of an 4 input mux be I2 Y
selected (i.e., connected to the output), then the select input lines must be set to I3
“10”. A mux of N inputs, commonly called an “N-to-1” mux, requires log2N select S1
S0
inputs. Common mux sizes are 2:1 (1 select input), 4:1 (2 select inputs), and 8:1 (3
select inputs). The truth table below specifies the behavior of a 4:1 mux. Note the
use of entered variables in the truth table – if entered variables were not used, the
truth table would require 26 or 64 rows. In general, when entered-variable truth Mux circuit
tables are used to define a circuit, “control” inputs are shown as column-heading symbol
variables, and data inputs are used an entered variables.

S1 S0 Y The truth table can easily be modified for muxes that handle different numbers of
0 0 I0 inputs, by adding or removing control input columns. A minimal mux circuit can be
designed by transferring the information in the truth table to a K-map, or by simply
0 1 I1
inspecting the truth table and writing an SOP equation (the reader in encouraged to
1 0 I2
verify that this is a minimal equation):
1 1 I3
Y = S1’.S0’ .I0 + S1’.S0.I1 + S1.S0’ .I2 + S1.S0 .I3
4:1 mux truth An N input mux is a simple SOP circuit constructed from N input AND gates and a
table single output OR gate. The AND gates combines the select inputs with the data
inputs such that only one AND is asserted at any time, and the OR output stage
simply combines the outputs of the AND gates. As an example, to select input I2 in a 4 input mux, the
two select lines are set to S1 = 1 and S0 = 0, and the input AND stage would use a three input AND
gate combining S1, S0, and I2.

Lab #7: Decoders, Multiplexors, Shifters and Encoders © Digilent, Inc. 2002
Decoders, Multiplexors, Shifters and Encoders Page 2 of 8

Problem 1: Compete the 4 input multiplexor circuit schematic in the lab submission form by
sketching the missing wires.

Often, mux circuits will use an enable input in addition to the other inputs. The enable input drives the
output to logic ‘0’ when de-asserted, and allows normal mux operation when asserted.

Problem 2: Complete the truth table and circuit sketch for a 4:1 mux with enable.

Consider the K-map representation of a given logic function, where each K-map cell contains a '0', '1',
or an entered variable expression. Each unique combination of K-map index variables selects a
particular K-map cell (e.g., cell 6 of an 8 cell K-map is selected when A=1, B=1, C=0). Now consider
a mux, where each unique combination of select inputs selects a particular data input to be passed to
the output (e.g., I6 of an 8 input mux can be selected by setting the select inputs to A=1, B=1, C=0). It
follows that if the inputs to a given logic function are connected to the select inputs of a mux, and
those same inputs are used as K-map index variables, then each cell in the K-map corresponds to a
particular mux data input. This suggests a mux can be used to implement a logic function by
“connecting” the K-map cell contents to the data lines of the mux, and connecting the K-map index
variables to the select lines of the mux. Mux data inputs are connected to: '0' (or ground) when the
corresponding K-map cell contains a '0'; '1' (or Vdd) when the corresponding K-map cell contains a
'1'; and if a K-map cell contains an entered variable expression, then a circuit implementing that
expression is connected to the corresponding mux data input. Note that when a mux is used to
implement a logic circuit directly from a truth table or K-map, logic minimization is not performed.
This saves design time, but usually creates a less efficient circuit (a classic tradeoff encountered in all
engineering disciplines). Note also that mux implementations work well for K-maps containing entered
variables.

Problem 3: Complete the sketch in the lab submission form to create a mux-based circuit that can
implement the logic equation shown in the submission form.

Muxes are most often used to transfer data elements from a

I3[7:0]
memory circuit to data processing circuit according to an
I2[7:0]
“address” presented on the select lines (this application of
I1[7:0]
muxes will be presented in later labs that deal with memory I0[7:0]
Y[7:0]
I0(0)
systems). Most data elements are bytes or words consisting of I1(0) Y(0)
8, 16, 32 or more bits, and “bus muxes” must be used in these I2(0)
I3(0)
systems to switch multiple bits simultaneously. A block
diagram and schematic for a bus mux that can select one of S1
four 8-bit data elements is shown below. S0
I0(1)
8 I1(1) Y(1)
I0[7:0] I2(1)
I3(1)
8
I1[7:0] 8
8 Y[7:0]
I2[7:0]
8 I0(7)
I3[7:0] I1(7) Y(7)
I2(7)
I3(7)
S1
S0
Decoders, Multiplexors, Shifters and Encoders Page 3 of 8

A mux can easily be described in behavioral VHDL using a selected signal assignment statement as
shown below. The code example on the left is for a mux that switches logic signals, and the code on
the right is for an 8-bit bus mux. Note the only difference in the code is in the port statement, where the
data elements for the bus mux are declared to be vectors instead of signals. Note also that the
assignment statement in the bus mux example assigns vector quantities just like signals. When you
examine the code examples, particularly the bus mux, look again at the previous figure and consider
the amount of effort required to create a bus mux schematic vs. the bus mux VHDL code.

library IEEE; library IEEE;

use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity mux_cond is entity mux_cond is

port (I0,I1,I2,I3 : in STD_LOGIC; port(I3,I2,I1,I0:in STD_LOGIC_VECTOR(7 downto 0);
S:in STD_LOGIC_VECTOR(1 downto 0); S : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC); Y : out STD_LOGIC_VECTOR(7 downto 0));
end mux_cond; end mux_cond;

architecture arch1 of mux_cond is architecture arch1 of mux_cond is

begin begin
with S select with S select
Y <= I0 when "00", Y <= I0 when "00",
I1 when "01", I1 when "01",
I2 when "10", I2 when "10",
I3 when others; I3 when others;
end arch1; end arch1;

VHDL code for a logic-signal mux VHDL code for a bus mux

Decoders

A decoder is a circuit that receives N inputs and then asserts one of 2N corresponding Y0
output signals based on that input. If the N inputs are taken as an N-bit binary I0 Y1
number, then only the output that corresponds to the input binary number is asserted. I1 Y2
For example, if a binary 5 (or "101") is input to a 3:8 decoder, then only the 5th output I2 Y3
of the decoder will be asserted and all other outputs will be de-asserted. Practical Y4
decoder circuits are usually built as: 2:4 decoders with 2 inputs and 22 (4) outputs; 3:8 Y5
decoders with 3 inputs and 23 (8) outputs; or 4:16 decoders with 4 inputs 24 (16) Y6

outputs. A decoder circuit requires one AND gate to drive each output, and each Y7

AND gate decodes a particular binary number. For example, a 3:8 decoder requires 8
AND gates, with the first AND gate having inputs A’ .B’.C’, the second A’ .B’.C, the 3:8 decoder
symbol
third A’ .B.C’, etc.

Problem 4: Complete the 3:8 decoder schematic on the lab submission form by sketching the
missing wires.

If a decoder larger than 4:16 is needed, it can be built by cascading smaller decoders of the sizes just
mentioned. Only decoders with an enable input can be used to construct larger decoder circuits. As
with the mux, the enable input drives all outputs to “0” when de-asserted, and allows normal decoder
operation when asserted.

Problem 5: Complete the 3:8 decoder with enable schematic on the lab submission form by
sketching the missing wires.
Decoders, Multiplexors, Shifters and Encoders Page 4 of 8

Problem 6: Complete the 4:16 decoder built from 4 2:4 decoders on the lab submission form by
sketching the missing wires.

Consider the function of a decoder and the truth table, K-map, or minterm representation of a given
function. Each row in a truth table, cell in a K-map, or minterm number in an equation represents a
particular combination of inputs. Each output of a decoder is uniquely asserted for a particular
combination of inputs. Thus, if the inputs to a given logic function are connected to the inputs of a
decoder, and those same inputs are used as K-map input logic variables, then a direct one-to-one
mapping is created between the K-map cells and the decoder outputs. It follows that any given function
represented in a truth table or K-map can be directly implemented using a decoder, by simply by
OR'ing the decoder outputs that correspond to a truth table row or K-map cell containing a “1”
(decoder outputs that correspond to K-map cells that contain a zero are simply left unconnected). In
such a circuit, any input combination with a logic '1' in the corresponding truth table row or K-map cell
will drive the output OR gate to a logic '1', and any input combination with a logic '0' in the
corresponding K-map cell will drive the OR gate output to a logic '0'. Note that when a decoder is used
to implement a circuit directly from a truth table or K-map, no logic minimization is performed. Using
a decoder in this fashion saves time, but usually results in a less efficient implementation.

Problem 7: Complete the circuit sketch in the lab submission form to create a decoder-based circuit
that can implement the logic equation shown.

Decoders are most often used to select a particular a memory device to receive a data element
transferred from a “data processing” circuit to a memory circuit to within a digital system (this
application of decoders will be presented in later labs that deal with memory systems).

A decoder can easily be

library IEEE;
described in behavioral VHDL use IEEE.std_logic_1164.all;
using a selected signal
assignment statement as shown entity decoder is
to the right. In the example, port (I: in STD_LOGIC_VECTOR(1 downto 0);
both the inputs and outputs are Y: out STD_LOGIC_VECTOR(3 downto 0));
end decoder;
grouped as busses so that a
selected assignment statement architecture arch1 of decoder is
can be used. In this example, begin
the inputs can be individually with I select
Y <= "0001" when "00",
referred to as I(1) and I(0), and "0010" when "01",
the outputs as Y(0) through "0100" when "10",
Y(3). The code can easily be "1000" when others;
modified to describe decoders end arch1;
of any size.
VHDL code for a 2:4 decoder
Priority Encoders

A priority encoder is, in a sense, the dual (or opposite) of the decoder circuit – it receives N inputs
(where N is typically 4, 8 or 16), and asserts an output binary code of M=log2N bits (so the M-bit
binary code is typically 2, 3, or 4 bits). The M-bit binary code indicates which input was asserted (i.e.,
in a 4:2 binary encoder, binary code 00 would be output if the 0th input line was asserted, binary code
01 would be output of the 1st input line was asserted, etc.). Since more than one input line to the
encoder might be asserted at any given time, the priority encoder asserts an output code corresponding
Decoders, Multiplexors, Shifters and Encoders Page 5 of 8

to the highest numbered input that is asserted (i.e., if both input line 0 and input line 2 were asserted in
a 4:2 encoder, then binary code 10 would be output indicating that input line 2 is the highest line
number – or highest priority input – currently asserted).

At first thought, a four input encoder circuit should require just two outputs. In EIN EOUT
such a circuit, asserting the 3rd input signal would cause a “11” output, asserting I0 Y0
the 2nd input signal would output a “10”, asserting the 1st input signal would I1 Y1
output a “01”, and asserting the 0th input would output “00”. But what if no I2 GS
inputs are asserted? Again, a “00” would be output. To avoid creating an I3
ambiguous “00” output, encoders typically use an “Enable In” (EIN) signal and
an “Enable Output” (EOUT) signal. EIN functions like other enable signals – Priority
when it is de-asserted, all outputs are driven to logic ‘0’, and when it is asserted, Encoder
the encoder outputs can be driven by the inputs. EOUT is asserted only when EIN
is asserted and no input signals are asserted. Thus, EOUT can be used to distinguish between no inputs
asserted and the 0th input asserted.

Larger encoders can be built from smaller encoder modules in much the same way that larger decoders
can be built from smaller decoder modules. An encoder module that can be used as a building block
for larger encoders must have one additional output called group-signal (GS). GS is asserted whenever
EIN is asserted along with any other input signal, and it is used to form the most significant bit of the
encoded output data element.

Problem 8. Complete the truth table for a four-input encoder circuit that includes EIN, EOUT, and GS
signals. When completing the truth table, note that if I3 is a ‘1’, it DOES NOT matter
what I2, I1, or I0 are – the encoded output will be “11” (this information can result in
don’t cares in the truth table, which makes the design much easier). When the truth
table is complete, transfer the information to the K-maps, and use the K-maps to find
minimal SOP equations.

Encoder circuits are typically used in library IEEE;

digital systems when a binary number
that corresponds to a given input must
be generated. For example, individual
“call attendant” signals arising from
passengers seated on an airplane could
be encoded into a seat number. Priority
encoders are also used when certain
input signals must be dealt with in a
special manner. For example, if inputs
from several sources can all arrive
simultaneously, a priority encoder can
indicate which signal should be dealt
with first.
Behavioral VHDL code describing a
4:2 priority encoder is shown on the
right.
use IEEE.STD_LOGIC_1164.ALL;
entity encoder is
Port (ein : in std_logic;
I : in std_logic_vector(3 downto 0);
eout, gs : out std_logic;
Y : out std_logic_vector(1 downto 0));
end encoder;
architecture Behavioral of encoder is
begin
eout <=ein and not I(3) and not I(2) and not
I(1) and not I(0);
gs <= ein and (I(3) or I(2) or I(1) or I(0));
Y(1) <= I(3) or I(2);
Y(0) <= I(3) or I(1);
end Behavioral;
VHDL code for a priority encoder
Decoders, Multiplexors, Shifters and Encoders Page 6 of 8

Shifters

A shifter is a circuit that produces an N-bit output based on an N-bit data input and an M-bit control
input, where the N output bits are place-shifted copies of the input bits, shifted some number of bits to
the left or right as determined by the M inputs. As an example, the function of an 8-bit shifter capable
of shifting one, two, or three bits to the right or left is illustrated below. Note that in this case, the M-
bits are divided into two separate functions: two bits (M1 and M0) to determine how many bit positions
to shift (0, 1, 2,or 3); and one bit (M2) to indicate which direction to shift (left = 1 or right = 0).

M2 M1 M0 I7 I6 I5 I4 I3 I2 I1 I0 M2 M1 M0 I7 I6 I5 I4 I3 I2 I1 I0 M2 M1 M 0 I7 I6 I5 I4 I3 I2 I1 I0

Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y1 Y0 Y 7 Y 6 Y 5 Y4 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y 2 Y 1 Y 0

M2 M1 M0 = 0 0 0 M2 M1 M0 = 0 0 1 M2 M1 M0 = 1 1 0

When bits are shifted left or right, some bits “fall off” one M2 M1 M0 I7 I6 I5 I4 I3 I2 I1 I0
end of the shifter, and are simply discarded. New bits
must then be shifted in from the opposite side. If no FILL I7
input exists, then 0’s are shifted in. Some shifters have a I6
FILL input signal, so that either a ‘1’ or a ‘0’ can be
shifted in depending on the state of the FILL input. Some Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
shifters also offer a ROTATE function where the Rotate Left by 2
“shifted-out” bits are wrapped around to the fill bit as
shown on the right.

The truth table below shows the input/output requirements for a four-bit shifter that can shift or rotate
an input value left or right by one bit. Note that the truth table uses entered variables to compress the
number of rows that would otherwise be required. A minimal circuit can be found from this truth table
using pencil-and-paper methods or a computer-based minimization program.

Shifters are most often found in circuits that work with EN R D Y3 Y2 Y 1 Y0

groups of signals that together represent binary numbers. For
example, a shifter circuit can multiply a number by 2, 4, or 8 0 x x I3 I2 I1 I0
simply by shifting the number right by 1, 2, or 3 bits (and 1 0 0 I2 I1 I0 0
similarly, a shifter can divide a number by 2, 4, or 8 by
shifting the number left by 1, 2, or 3 bits). Shifters are also 1 0 1 0 I3 I2 I1
used in computer applications where individual bits within a
1 1 0 I2 I1 I0 I3
data byte or word must be accessed. These applications are
discussed further in later labs. 1 1 1 I0 I3 I2 I1

A behavioral VHDL design of a simple 8-bit shifter that can Truth table for a 4-bit shifter with shift/rotate
rotate or shift left or right by one bit is shown. A conditional left/right functions
assignment statement is used in this example (it is the only
statement in the architecture body). A conditional assignment statement uses the “when/else”
keywords to distinguish between potential signal assignments. Conditional assignment statements are
Decoders, Multiplexors, Shifters and Encoders Page 7 of 8

useful when more complex

combinational logic circuits must be library IEEE;
use IEEE.std_logic_1164.all;
described. In fact, the conditional
assignment statement shown here and entity my_shift is
the selected assignment statement used port (DIN: in STD_LOGIC_VECTOR (7 downto 0);
earlier are the most useful VHDL R,EN: in STD_LOGIC;
DOUT: out STD_LOGIC_VECTOR (7 downto
statements for describing general 0));
combinational circuits. end my_shift;

Note that the first operation in the architecture my_shift_arch of my_shift is

conditional assignment statement begin
DOUT<= DIN when EN = '0' else
assigns the entire DIN bus to the DIN(6 downto 0)&DIN(7) when (R = '1') else
DOUT bus – this is useful when DIN(6 downto 0)&'0';
working with bussed data elements. In end my_shift_arch;
general, only busses of like sizes
should be assigned to one another. Behavioral VHDL for a simple shifter
Also note the use of the concatenation
operator (&) to create the rotate and 0-fill operations.

Problem 9. Complete the truth table for a 4-bit shifter that has no enable input, no rotate input, two
inputs that dictate whether the input is to be shifted 0, 1, 2, or 3 bits, a direction input,
and a fill input.

Lab Procedure

Problem 10. Multiplexor Circuits

a) On the lab submission form, enter the function F=Σ m(0,2,7,9,10,11,14) + φ(1,12,13) in the third
order K-map using D as an MEV. Loop out minimum cover, and write the equation for F1.
b) Create a circuit macro for a 4:1 mux and for a 2:1 mux using the Xilinx VHDL editor. Add these
macros to a new schematic page, and use them to create an 8:1 mux in the schematic editor.
c) Use the 8:1 mux and whatever additional gates are required to implement the function from part (a).
Verify the circuit’s performance using the Xilinx simulator. If the mux circuit had been built from
gates (rather than VHDL code), what would have been the gate/input tally of this circuit (answer on
submission form)?
d) Print and attach the schematic, VHDL code for the 4:1 mux, and simulation output.

Problem 11. Decoder Circuits

a) Implement a 3:8 decoder with an enable input using the Xilinx schematic capture program.
Simulate the circuit to ensure that it functions correctly, and then create a macro for your decoder.
b) Create a 4:16 decoder from two 3:8 decoder macros, and use it to implement a circuit for the
function F = Σ m( 0, 4, 5, 6, 12, 14 ) + φ( 3, 9 ). Simulate and verify the circuit's performance.
c) Add the required gates to your circuit to create the function G = Σ m( 1, 3, 5, 9, 10, 13 ) + φ( 4 ).
Note that the independent functions F and G are generated from the same decoder at the same time.
Decoders, Multiplexors, Shifters and Encoders Page 8 of 8

d) Combine the F and G function outputs with a 2OR gate, and label the new output H. Then use the
decoder outputs and an AND gate to create the POS function J = Π M( 2, 7, 8, 11, 15 ). (Watch the
assertion levels when implementing the POS circuit!) Simulate the circuit, and compare the H and J
outputs.
e) Print and attach the circuit and simulation output from part d.

Problem 12. Priority Encoder Circuits

a) Open a new schematic page and implement a circuit for a four-input priority encoder. Your circuit
should have an enable input, a group-signal (GS) output, and an enable-out (EO) output. Simulate
the circuit to verify its performance.
b) Create a macro for the encoder, and use that macro and whatever further gates are required to
create an 8-input priority encoder. Simulate the circuit to verify its performance.
c) Print and attach the circuit schematic and simulation output.

Problem 13. Shifter circuits

Use the VHDL tool to implement an 8-bit shifter that can shift or rotate left or right by 0, 1, 2, or 3 bit
positions. Simulate the circuit to verify its performance. Print and attach the VHDL code and simulator
output.

Problem 14. De-multiplexing circuit

A decoder with an enable can also be used as a de-multiplexor. A de-multiplexor can receive the
output signal produced by a multiplexor and select signals used by a multiplexor to recreate the
original input signals to a decoder. The advantage in using a multiplexor/de-multiplexor circuit is that
fewer signal wires can be used to communicate data over a distance; the disadvantage is that only one
data signal at a time can be transmitted. Design a mux/de-mux circuit using the Xilinx schematic
capture tools and the Digilab board that can communicate 8 data signals using only 4 wires. Use three
slide switch inputs to select the data channel, four buttons to form the eight required data channel
inputs, and 8 LEDs to show the output. The eight inputs are formed from the four buttons as follows:
I0 = BTN1; I1 = BTN2; I2 = BTN3; I3 = BTN4; I4 = BTN1 and BTN2; I5 = BTN2 and BTN3; I6 =
BTN3 and BTN4; and I7 = BTN4 and BTN1.

This last problem is presented with less detail than previous problems. You must do a little more
thinking, and a little more design work to arrive at a solution.