BSc Hons.

Electronics &
Telecommunications
Technology
HETT204: APPLICATIONS OF
ELECTRONIC DEVICES & CIRCUITS

Mr. P Dangare
 CE Amplifier Design Procedure
Use KVL to calculate resistor values to give
required IC, gain and base bias conditions
i.e to give appropriate values for VC, VB & VE.
The DC bias point is usually established to
allow for a large variation or swing in Vout.
To provide this large swing in Vout, a bias
network is chosen so that VC = VCC/2
Approximations:
IC = IB:
IE = ( + 1)IB or IC IE for »1
VBE = 0.6 - 0.7 V for Si
VBE = 0.2 – 0.3 V for Ge.
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 Fixed Bias
Applying KVL to input loop:
VCC I B RB VBE

VCC VBE
IB
RB
But I C IB

(VCC VBE )
I CQ
RB

Applying KVL to output loop:

VCC I C RC VCE

VCEQ VCC I CQ RC

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 Emitter Stabilized bias
Applying KVL to input loop:
VCC I B RB VBE I E RE

VCC I B RB (1 ) RE VBE

VCC VBE
IB
RB ( 1) RE
But I C IB
(VCC VBE )
I CQ
RB ( 1) RE

Applying KVL to output loop:

VCC I C RC VCE I E RE
VCEQ VCC I CQ ( RC RE )

RC
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Also AV 4
RE
 Collector Feedback bias
Applying KVL to input loop:
VCC (IC I B ) RC I B RF VBE

VCC I B RB (1 ) RE VBE
VCC VBE
IB
RF ( 1) RC
IC
But I C IB IB

(VCC VBE )
I CQ
RF ( 1) RC

Applying KVL to output loop:

1
VCC (I C I B ) RC VCE IC 1 RC VCE

1
VCEQ VCC I CQ (1 ) RC
VCEQ VCC I CQ RC (since 1)
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 Voltage Divider bias

R1
VBB VCC
R1 R2

R1 R2
RB R1 R2
R1 R2
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 Voltage Divider bias
Applying KVL to output loop:
VCC I C RC VCE I E RE

VCC I C RC RE VCE

VCC VCE RC
I CQ Also AV
RC RE RE

VCEQ VCC I CQ RC RE (since 1)

Applying KVL to input loop:
VBB I B RB VBE I E RE VBB I B RB VBE IB( 1) RE

VBB VBE
IB Also Vb VBE I E RE
RB ( 1) RE

VCC VCC IC
Rules of thumb: VC I R1 10 I B 10
2 R1 R2
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 DC Biasing Circuits
The ac operation of an +V CC
amplifier depends on
the initial dc values of
IB, IC, and VCE.
RC
By varying IB around
RB
an initial dc value, IC
v out
and VCE are made to
vary around their initial
dc values.
DC biasing is a static
v in vce
operation since it deals ib
with setting a fixed
(steady) level of ic
current (through the
device) with a desired
fixed voltage drop
across the device.

8
Purpose of the DC biasing circuit
To turn the device “ON”
To place it in operation in the region
of its characteristic where the device
operates most linearly,
• i.e. to set up the initial dc values of IB,
IC, and VCE

9
For the emitter stabilized & voltage divider bias circuits:
The transistor operates under
certain constraints & must be
biased properly to keep it in its
active region. This involves the
choice of the operating point of the
amplifier w.r.t. its characteristic
curves.
The nominal voltage gain
of this amplifier without the
bypass capacitor is given
by:
Vout RC
Vin RE
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RC + RE determines the ICmax
and the load line for the
operation of the amplifier.
Once the supply voltage is
chosen, ICmax is selected &
that determines the total
value for these two resistors.
After the total resistance is
determined, then it is divided
into RC & RE to achieve the
required voltage gain. It is
also desirable to maintain
good temperature stability.
10
 Voltage-Divider Bias
The voltage – divider +V CC
(or potentiometer) bias
circuit is by far the
most commonly used.
RC
RB1, RB2 voltage- R1
divider to set the value v out
of VB , IB C1
C2

C3 to short circuit v in

ac signals to ground,
while not effect the DC R2

operating (or biasing)

of a circuit RE C3

Bypass Capacitor
(RE stabilizes the ac
signals) 11
 DC Equivalent Circuit
+V CC +V CC

RC IC RC
R1 R1

RL

v in

R2 R2
IE

RE RE

Bias Circuit DC equivalent

circuit 12
 Graphical DC Bias Analysis
+V C C
VCC ICRC VCE IERE 0
for I C IE
1 VCC
IC RC IC VCE
RC RE RC RE
R1 Point - slope form of straight line equation :
y mx c

I C(sat) = V CC /(R C +R E )

R2 DC Load Line
IE
IC
RE (mA)
V CE(off) = V CC

V CE
13
 DC Load Line
• The straight line is known as the DC IC(sat) = VCC/(RC+RE)
load line
• Its significance is that regardless of DC Load Line
the behaviour of the transistor, the IC
collector current IC and the collector- (mA)
VCE(off) = VCC
emitter voltage VCE must always lie
on the load line, VCE
• depends ONLY on the VCC, RC and RE
• i.e. The dc load line is a graph that
represents all the possible
combinations of IC and VCE for a
given amplifier. (For every possible
value of IC, the amplifier will have a
corresponding value of VCE.)
• It must be true at the same time as
the transistor characteristic. Solve
two conditions using simultaneous
equations What is IC(sat) and VCE(off) ?
• graphically Q-point !!
14
 Q-Point (Static Operation Point)
When a transistor does not have an ac input,
it will have specific dc values of IC and VCE.
These values correspond to a specific point on
the dc load line. This point is called the Q-
point.
The letter Q corresponds to the word (Latent)
quiescent, meaning at rest.
A quiescent amplifier is one that has no ac
signal applied and therefore has constant dc
values of IC and VCE.

15
Q-Point (Static Operation Point)
The intersection of the dc
bias value of IB with the
dc load line determines
the Q-point.
It is desirable to have the
Q-point centered on the
load line. Why?
When a circuit is designed
to have a centered Q-
point, the amplifier is said
to be midpoint biased.
Midpoint biasing allows
optimum ac operation of
the amplifier.
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 Transistor Characteristic Curves

Note: The load line gives all the possible combinations of IC and
VCE for a given BJT.
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 Determining the load line

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5/24/2021 19
 Implications of Operating Point

• As a rule of thumb RC 10 RE
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 Indirectly Biased CE amplifier Design

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 DC Biasing + AC signal
When an ac signal is
applied to the base of
the transistor, IC and
VCE will both vary
around their Q-point
values.
When the Q-point is
centered, IC and VCE
can both make the
maximum possible
transitions above and
below their initial dc
values.

22
 DC Biasing + AC signal
When the Q-point is above
the centre on the load line,
the input signal may cause
the transistor to saturate.
When this happens, a part
of the output signal will be
clipped off.

When the Q-point is below

midpoint on the load line,
the input signal may cause
the transistor to cutoff.
This can also cause a
portion of the output signal
to be clipped.

23
DC Biasing + AC signal

24
 AC load line
Suppose an a.c. coupled load RL is added
VCC
 The AC load line
The AC load line is a straight line with a slope equal to
the AC impedance facing the nonlinear device, which is
in general different from the DC resistance.
Because the impedance of the reactive components will
vary with frequency, the slope of the AC load line
depends on the frequency of the applied signal.
So there are many AC load lines, that vary from the DC
load line (at low frequency) to a limiting AC load line,
all having a common intersection at the dc operating
point.
This limiting load line, generally referred to as the AC
load line, is the load line of the circuit at "infinite
frequency", and can be found by replacing capacitors
with short circuits, and inductors with open circuits.
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 Additional a.c. load
The ‘battery’ supplying the d.c. supply VCC has
negligible impedance compared to the other
resistors, in particular RC.
It therefore presents an effective ‘short-circuit’
for a.c. signals.
a.c. short via
d.c. supply
RC

iC
RL

GND
 Additional a.c. load
The effective a.c. load is the parallel
combination of RC and RL . (From the collector
C we can go through RC or RL to ground)

iC
RL RC vce

GND
 AC Equivalent Circuit
+V CC

RC
R1
rC
vin vce
RL

v in R1//R2
R2

RE

rC = RC//RL

Bias Circuit AC equivalent circuit

29
 AC Load Line
IC(sat) = VCC/(RC+RE) The ac load line of a given
amplifier will not follow
DCLoad Line the plot of the dc load line.
IC This is because the dc load
(mA) of an amplifier is different
VCE(off) = VCC
from the ac load.
VCE

IC(sat) = ICQ + (VCEQ/rC)

a c lo a d lin e

ac load line
IC IC Q - p o in t

d c lo a d lin e

VCE(off) = VCEQ + ICQrC

VCE
V CE

30
 IC(sat) = VCC/(RC+RE) Load line equation:
IC = mVCE + IC (VCE = 0) (1)
DCLoad Line
DC load line:
IC
m = -1/(RC + RE)
(mA)
VCE(off) = VCC IC (VCE = 0) = VCC /(RC + RE)

VCE AC load line:

m = -1/rC = -1/(RC // RL)
To find IC (VCE = 0), substitute values of IC,Q & VCE,Q into (1)

IC(sat) = ICQ + (VCEQ/rC) IC,Q = mVCE,Q + IC (VCE = 0)

a c lo a d lin e
ac load line
IC
IC Q - p o in t

d c lo a d lin e
VCE(off) = VCEQ + ICQrC

VCE
V CE 31
 AC Load Line
What does the ac load line tell you?
The ac load line is used to tell you the maximum
possible output voltage swing for a given common-
emitter amplifier.
In other words, the ac load line will tell you the
maximum possible peak-to-peak output voltage (Vpp)
from a given amplifier.
This maximum Vpp is referred to as the compliance
of the amplifier.
Also the AC Saturation Current, Ic(sat) and AC Cutoff
Voltage, VCE(off)

32
 Common Emitter Coupling

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The capacitor C1 is used to keep any DC component
from disturbing the carefully developed biasing which
establishes the operating point.

C1 must be chosen so that it does not appreciably

attenuate the lowest frequency which is to be
amplified.

The reactance of C1: X1 = 1/2 flowC < Rin

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Rin is the effective input impedance
Rin = R1 R2 RBE
where RBE is the input resistance of the transistor hie

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The capacitor C2 provides DC blocking and must also
be chosen so that it does not attenuate the signal.
X2 = 1/2 flowC2 < RL
The capacitor CE bypasses the emitter resistor RE,
making it an AC ground.
This is because a rise in the signal would increase the
current in the resistor and therefore VE. The change in
voltage VBE and the collector current would be
decreased
CE is chosen so that its reactance is small compared
to RE at the minimum frequency of operation.
XE = 1/2 fminCE < RE
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 Upper Cut-off Frequency
The upper cut-off frequency is determined by internal
capacitances of transistor structures.
These capacitances model the effects of depletion
regions at the boundary of pn junctions.
Generally one internal capacitance is included for each
internal pn junction
• For the BJT there are 2 components:
Base-emitter capacitor (Cbe)
Collector capacitance (Cc)

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