Set No.

1
Code No: RT42044C
R13
IV B.Tech II Semester Supplementary Examinations, September - 2020
LOW POWER VLSI DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Question paper consists of Part-A and Part-B
Answer ALL sub questions from Part-A
Answer any THREE questions from Part-B
*****

PART–A (22 Marks)

1. a) What is surface scattering? [4]
b) Compare between VTCMOS and MTCMOS for leakage power reduction. [3]
c) Write a short note on gate level capacitance estimation. [4]
d) Draw the carry look ahead adder architecture and identify its key components. [3]
e) Write a short note on Braun Multiplier. [4]
f) Compare SRAM and DRAM memories. [4]

PART–B (3x16 = 48 Marks)

2. a) What is the need for low power circuit design? Explain the issues involved in low
power VLSI Design. [8]
b) Discuss about (i) hot electron effect (ii) velocity saturation. [8]

3. a) Discuss about switched capacitance minimization approach.

[8]
b) Compare pipelining and parallel processing approaches with suitable examples. [8]

4. a) Discuss the Monte Carlo simulation techniques. [10]

b) Explain about the modeling and analysis of a transistor using SPICE. [6]

5. Design a conventional CMOS Full Adder and discuss its performance. [16]

6. Explain the multiplication process of a Booth’s multiplier. [16]

7. a) Discuss the features of a six transistor CMOS memory cell. [8]

b) Discuss about future trends and Development of DRAM. [8]

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