16

Simplified CMOS Voltage Transfer Curve Step 1. Finding VM

■ For CMOS inverters, the voltage transfer curve of the inverter is ideal enough ■ Goal: find VM = input voltage for the output = VM
that we can approximate it with a construction that is suitable for quick hand
both transistors are saturated at VIN = VM since
calculation

VOUT
VDSn = VM - 0 > VM - VTn

VOH = VMAX VSDp = VDD - VM = (VDD - VM) +VTp

Slope Av ■ Equate drain currents, omitting the channel length modulation terms
(1 + λn VDSn) and (1 + λp VSDp) since they tend to cancel out (if λn = λp,
they exactly cancel out)
VM

I Dn = µ n C ox  ------ ( V M – V Tn )
W 2
2L n
VOL = VMIN
VIL VM VIH VIN

– I Dp = µ p C ox  ------ ( V DD – V + V Tp )
W 2
■ We first observe that:  2L p M

V OH ≈ V MAX = V DD and V OL ≈ V MIN = 0 V

■ Letting kn = µn Cox (W/L)n and kp = µp Cox (W/L)p --
The edges of the transition region are then found as the intersections of the
tangent to the voltage transfer curve at VIN = VM (a line of slope Av)
■ In order to construct the VTC for a CMOS inverter (and to find estimates of the 1 2 1 2
--- k n ( V M – V Tn ) = --- kp ( V DD – V M + V Tp )
noise margins), we need to first: 2 2
(i) find the voltage VM
(ii) find the small-signal voltage gain Av at VIN = VM

EECS 105 Fall 1998 EECS 105 Fall 1998

Lecture 16 Lecture 16
 Finding VM (cont.) Step 2. Finding Av
s2
Result:
+
kp gmpvsg2
V Tn + ----- ( V DD + V Tp ) vsg2 rop
kn
V M = ---------------------------------------------------------- _
kp g1 = g2
1 + -----
kn d1=d2
+ vout
+
vin vgs1
gmnvgs1 ron
We can set VM = VDD / 2 and achieve a symmetrical transfer curve _
_
Example: suppose VTn = - VTp = 1 V and VDD = 5 V
s1
kp
1 + 4 -----
kn
V M = ---------------------- = 2.5 V --> kp = kn We note that vsg2 = - vin and can simplify the small-signal circuit
kp
1 + -----
kn
+ +
which makes sense since the transistors must have identical characteristics for the vin +
v gmnv gmpv vout
transfer curve to be symmetrical. − ron rop

The mobility of holes in p-channels is about half that of electrons in − −

n-channels, µp = µn / 2, which implies that we must adjust the width-length
ratios to compensate:

kn = kp --> (W/L)p = 2(W/L)n

EECS 105 Fall 1998 EECS 105 Fall 1998

Lecture 16 Lecture 16
 Approximate Transfer Curve Noise Margins

■ The small-signal gain (which is the slope of the transfer curve when the input is ■ For kN = kP, the mid-point voltage is VM = 2.5 V. For a slope Av = - 5, the input-
equal to the mid-point voltage) is: low voltage and input-high voltages are:

v out ⁄ v in = –( g mn + gmp ) ( r on r op ) = A v VIL = 2.5 V - (1/5) (2.5 V) = 2 V

VIH = 2.5 V + (1/5) (2.5 V) =3 V

CMOS inverters have a channel length that is as short as possible (to minimize the The low and high noise margins are therefore:
area ... and maximum the density) ... the output resistances are relatively small and a
NML = VIL - VOL = 2 - 0 = 2 V
typical value is vout / vin = - 5 to - 10.
NMH = VOH - VIH =5 - 3 = 2 V
* The input-low and input-high voltages are:
The transition region (or “gray area”) is the interval
VOUT
VIL < VIN < VIH or 2 V < VIN < 3 V
VOH = VDD

Av
■ Finding the actual transfer function requires solving the drain current equations
when the p-channel and n-channel are in the appropriate operating regions ... and
VDD − VM
finding the transition voltages for the regions.
Av
SPICE is good at this job!
VOL = 0 V
VIL VM VIH VIN

V IL = V M – ( V DD ⁄ ( 2 A v ) )

V IH = V M + ( V DD ⁄ ( 2 A v ) )

EECS 105 Fall 1998 EECS 105 Fall 1998

Lecture 16 Lecture 16
 CMOS Inverter: Propagation Delay Estimating the Load Capacitance

■ The propagation delays tPHL and tPLH are obviously of major importance for ■ The load capacitance CL consists of
digital circuit design ...
CG, the input capacitances of the inverters 2 and 3, and
Example:
CP, the parasitic capacitance to the substrate from the drain regions of inverter 1
clock frequency = 250 MHz --> clock period = 4 ns and the interconnections between the output of inverter 1 and the inputs of
inverters 2 and 3.
complex systems (e.g., microprocessor) have around 20-50 propagation delays
per clock period, so we need to have
tPLH and tPHL < 100 ps = 10-10 s VDD

W
L p2
VDD VDD 2
■ Hand calculation of propagation delays: use approximation that input changes W
instantaneously W L n2
L p1

VIN VIN 1
VIN + VDD

CL VOUT W
VOH L n1 W
L p3
tCYCLE −
3
VOL W
L n3
t

VOUT tPHL tPLH

(a) (b)

VOH VOH
tCYCLE ■ For hand calculation, we do a worst case estimate of CG by adding the maximum
50%
VOL
gate capacitances for inverters 2 and 3
t
C G = C ox [ ( W ⋅ L ) p2 + ( W ⋅ L ) + ( W ⋅ L ) p3 + ( W ⋅ L ) ]
n2 n3

EECS 105 Fall 1998 EECS 105 Fall 1998

Lecture 16 Lecture 16
 Parasitic Capacitance from Drain Depletion Regions Calculation of Parasitic Depletion Capacitance

■ The drain n and p regions have depletion regions whose stored charge changes ■ “Bottom” of depletion regions of the load inverters’ drain diffusions contribute a

,, ,,
during the transient. depletion capacitance
Take the worst case and use the zero-bias depletion capacitance (the maximum CBOTT = CJn(WnLdiffn) + CJp(WpLdiffp)
value) as a linear charge-storage element during the transient.
with CJn and CJp being the zero-bias junction capacitances (fF/µm2) for the n-

,,
active area (thin
channel MOSFET drain-bulk junction and the p-channel MOSFET drain-bulk
,,,,, , , , , ,
,,,,, , , , , , ,
,,,,, ,,,,,,,,,,,,
, , ,,,,,,,,,,,,,,
gate contact
oxide area)
,

gate polysilicon gate junction, respectively.

interconnect
contact ■ “Sidewall” of depletion regions of the load inverters’ drain diffusions make an
,

n+ polysilicon gate
additional contribution:
,,,
metal

,,
interconnect
,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,

,,,,,
, CSW = (Wn + 2Ldiffn)CJSWn + (Wp + 2Ldiffp)CJSWp
with CJSWn and CJSWp being the zero-bias sidewall capacitances (fF/µm) for the
,,,,
A
n-channel MOSFET drain-bulk junction and the p-channel MOSFET drain-bulk

,,,
source contacts junction, respectively.
W
bulk
contact
■ The total depletion capacitance CDB = CBOTT + CSW
drain
contacts

,,
source drain edge of
interconnect interconnect active area
L

L
(b) ■ Typical numbers: CJN and CJP are about 0.2 fF/µm2 and
CJSWn and CJSWp are about 0.5 fF/µm.

Ldiff

EECS 105 Fall 1998 EECS 105 Fall 1998

Lecture 16 Lecture 16
 Parasitic Capacitance from Interconnections

,,
■ “Wires” consist of metal lines connecting the output of the inverter to the input
of the next stage. In cross section,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
polysilicon metal interconnect
,

gate (width Wm, length Lm)

,,

,,
0.6 µm deposited oxide
0.5 µm thermal oxide

p+
p (grounded)

gate oxide

■ The p+ layer (i.e., heavily doped with acceptors) under the thick thermal oxide
(500 nm = 0.5 µm) and deposited oxide (600 nm = 0.6 µm) depletes only slightly
when positive voltages appear on the metal line, so the capacitance is
approximately the oxide capacitance:

C WIRE = C thickox ( W m ⋅ L m )

where the oxide thickness = 500 nm + 600 nm = 1.1 µm.

* For large digital systems, the parasitic interconnect capacitance can dominate the
load capacitance --

CL = CG + CP = CG + (CDB + CWIRE)

EECS 105 Fall 1998

Lecture 16