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A Novel High Speed Differential Ultra Low-Voltage CMOS Flip-Flop For High Speed Applications
A Novel High Speed Differential Ultra Low-Voltage CMOS Flip-Flop For High Speed Applications
A Novel High Speed Differential Ultra Low-Voltage CMOS Flip-Flop for High Speed
Applications
Yngvar Berg
Institute of Microsystems Technology
Vestfold University College
Horten, Norway
Email: Yngvar.Berg@hive.no
dependent on the applied offset voltages Vof f set− and/or tDQM tCQ
Vof f set+ as well. Assuming a positive input transition, the tDQ
Set up
floating-gates will be moved by kin VDD and the output will
Master Slave
be pulled down to 0 in a similar manner as a complementary
inverter. The active current will be larger due to the boost QMN
QMN
of the evaluate transistors.
The ULV inverters shown in Figure 1 recharge simultane-
D D
ously when φ = 1. The precharge level is different, the Pφ VDD
φ QMN
precharges to 1 and while the output of the Nφ precharges φ Q
to 0. The Pφ gate is susceptible to a positive input transition [V]
when the evaluate phase starts, i.e. φ = 0. QMP
then QM P = D and QM N ≈ D, and if D = 1 then The most critical timing issue in the ULV Flip-Flop is the
QM N = D and QM P ≈ D. The slave latch will not setup time of the master latch. The elevated current level of
be influenced by any changes in QM P or QM N due the evaluation transistors in a slave latch, i.e. slave latch
to the inverters at the output. The inverters must be in Figure 2, will pull the output quickly to the right value.
strong enough to hold a stable output value when the Typically, the clock to output delay is negative due to the
master latch is transparent. extremely low rise and fall time of the output Q.
2) E2 . Input D is stable. The critical timing restriction is
the setup time and thus only dependent on the delay
through a pass transistor. IV. M ASTER LATCHES
3) R1 . QM N and QM P will be set to D. More specif-
ically, VQMN = VDD if D = 1 and VQMN ≈ VDD /2 In this section we present new master latch configurations
if D = 0, and VQMP = 0V if D = 0 and aimed for ultra low-voltage applications including a novel
VQMP ≈ VDD /2 if D = 1. low power version. The master latches presented are differ-
4) E2 → R1 . Data to QM delay tDQM . ent from previously published ULV Flip-Flops [9] in several
5) E3 . Clock signal φ switches from 0 to 1. One of the aspects. The inputs to the Flip-Flops are used to control the
evaluate transistors are activated trough a boosted QM recharge transistors and are used to reduce the static power
voltage. The activated evaluate transistor will drive the consumption. By adding transistors to increase the control
output Q to D because the current level provided by of the semi floating-gates, i.e. QM voltages, we can turn
the evaluate transistor is significantly larger than the off the non active evaluation transistors. Compared to the
current level of the inverters. This is the only event that ULV Flip-Flop in [9] all the presented master latches and
may trigger the slave latch and determine the output Flip-Flops described in this paper are low power.
of the Flip-Flop. The master latch becomes non active. Different implementations of ultra low voltage master
latches are shown in Figure 4. The basic master latch is
6) R2 . Slave latch will respond to QM N or QM P and shown in Figure 2 where the input D is applied through pass
set the slave latch output Q = D and Q = DB. transistors. In Figure 4 2) additional recharge transistors,
labeled Kn2 and Kp2 , are applied to the QM nodes. The
7) E1 → E3 . The master latch is active and output Q is
effect of these transistors is provide a way to turn the
stable due to the cross coupled inverters at the output.
evaluate transistors off and thereby reducing the power
consumption when φ = 1. The QM 2N and QM 2P will
8) E2 → E3 . Setup time for the input. This is the only be affected while the clock signal switches and the full
significant delay of the ULV Flip-Flop. effect of the signal through the floating capacitor may be
9) E2 → R2 . Data to output time. reduced. In Figure 4 3) a differential input master latch is
10) E3 → E1 . The slave latch is active and master latch shown where we use the D input to turn off the most active
is non active. evaluate transistor. This configuration will not be as robust
as the master latch in 2). The master latch shown in Figure
The simple ULV master latch is shown in Figure 2. D 4 4) resembles the circuit in 2). The effect of the keeper
is loaded onto QM 1P and QM 1N when φ = 0. More transistors Kn4 and Kp4 will be delayed slightly compared
specifically if D = 1 then QM 1N = D = 1 and to Kn2 and Kp2 and the effect of the signal applied to
QM 1P < D due to the body effect, and if D = 0 then the floating capacitors are more evident. In Figure 4 5) the
QM 1P = D = 0 and QM 1N > D. When the clock signal additional transistors are controlled by the output of the slave
φ switches from 0 to 1 the recharge transistors Rn1 and latch Q. If the output Q = 1 the Kn5 transistor will be
Rp1 closes and the capacitive input will increase the voltage turned on and reduce the current running through transistor
level of QM 1N and decrease the voltage level at QM 1P . En5 and hence reduce the power consumption and increase
In the case of D being equal to 1 the resultant voltage at the noise margin of a slave latch.
QM 1N is >> VDD hence >> D andQM 1P is ≈ 0 hence Simulated responses for different master latches are shown
≈ D. In this case the nMOS transistor En1 is more enhanced in Figure 5. The supply voltage is 200mV and timing details
than the Ep1 transistor and the output Q will be pulled for event E1 and E2 are shown. The master latches become
to 0 = D through a large current provided by En1 . The active when φ switches from 1 to 0 and D is passed onto
QM nodes will be floating until the next event determined the QM nodes through the recharge transistors. At event
by the clock switching from 1 to 0. Hence, the En1 and E2 the input changes from 0 to 1 and the QM are affected.
Ep1 transistors will be ON until this event and contribute to QM 2N , QM 2N and QM 4N will be pulled to 0 after right
power consumption. One or both of these transistors should after the output of the slave is pulled to 0. Master latches
be turned OFF to save power while the slave is active. 1), 3) and 5) require less set-up time than 2) and 4).
D E1 E3 E3
φ QM3P D φ
QM2P
0.35
Kp2 Kp3 QM4P
QM1N
0.3 QM5N
QM2P QM3P QM4N
φ Ep2 φ Ep3 QM3N
0.25
QM2P
Rn2 Rn3 D D QM2N
0.2
φ QM5P
D D 0.15 QM4P
QM2P
Rp2 Rp3 0.1
[V] QM3P
QM4P
QM2N QM3N QM1P QM5P
φ En2 φ En3 0.05
QM5P φ
D
Kn2 Kn3 0 D
QM5N
QM5N
−0.05
QM4N QM1P
QM4N QM3P
D
−0.1
2) 3) QM2N
φ −0.15
6 7 8 9 10 11 12
−7
Time [s] x10
Kp4
Figure 5. Simulated response for different master latches.
QM4P QM5P
φ Ep4 φ Ep5
D φ QMP QMP
φ Ep1 Ep2 φ
D
Rp4 φ
Rn1 Rn2
QM4N
φ En4
Rp5 Kn5
Kn4
φ En5
QM5N Q Q
φ D D
4) 5)
Rp1 Rp2
Figure 4. Different master latch configurations. The input D can QMN QMN
be used to provide a reference to Ep1 and Ep2 , and D can be used φ En1 En2 φ
to provide a reference to En1 and En2 .
D D
V. S YMMETRIC DIFFERENTIAL ULTRA LOW- VOLTAGE
F LIP -F LOPS Figure 6. The symmetric high-speed ULV Flip-Flop.
A symmetric and differential ULV Flip-Flop is shown in
Figure 6. The master latches are similar to that of Figure 4 2) Ep1 and Ep2 can be connected directly to VDD , and En1
and the slave latches resemble the basic slave latch shown in and En2 can be connected directly to gnd. This will only
Figure 2. The presented Flip-Flop is different from the Flip- affect the response of the Flip-Flop slightly.
Flop presented in [9] by using the input D, and D, to power An alternative Flip-Flop with reduced input load and
the evaluation transistors En1 , En2 , Ep1 and Ep2 directly. increased output- and clock load is shown in Figure 7.
This reduces the signal path from input to output of the ULV
Flip-Flops described. The most critical timing issue of the A. Set-up details
master latches presented is the set-up time. By using the D In Figure 8 the set-up details for input D = 1 and Q = 0
and D inputs directly to the evaluate transistors as if they are shown. The recharge transistor Rn1 will pass the D = 0
were pass transistors the Flip-Flop will react more quickly onto the gate of evaluate transistor Ep1 . This node is labeled
because all evaluate transistors will the pull the outputs in QM P . In the set-up phase QM P becomes 0 and QM N
the same direction. will be close to 0. Transistor Ep1 will be activated when φ
In order to reduce the input load the evaluate transistors switches from 1 to 0. At the same time the recharge transistor