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Application Note: Sample Schematic Ethercat Slave Controller (Et1100) With 2 Mii Ports (Micrel Ks8721Bl)
Application Note: Sample Schematic Ethercat Slave Controller (Et1100) With 2 Mii Ports (Micrel Ks8721Bl)
D D
Application Note
Sample Schematic
EtherCAT Slave Controller (ET1100 ) with 2 MII Ports (Micrel KS8721BL)
C C
Page Index
A A
Date: Sheet 1 of 8
5 4 3 2 1
5 4 3 2 1
REVISION HISTORY
08.10.2007 U401 changed fom 32k to 16k; R401 removed; comments added for LED's. 0.2
29.01.2008 added pull-down values for the different MII configurations (Page 7) 1.0
C C
B B
A A
Date: Sheet 2 of 8
5 4 3 2 1
5 4 3 2 1
D EtherCAT D
Configuration
PROM
Address 0
Configuration
MII Connector
PHY
Magnetics
PORT 0 (IN) RJ45
C PDI EtherCAT C
Reset
SlaveController
PHY Clock
ET1100
MII Connector
PHY
B Magnetics B
Address 1
Configuration
Power +3.3V
Clock
Supply
25 MHz
A A
Date: Sheet 3 of 8
5 4 3 2 1
5 4 3 2 1
Date: Sheet 4 of 8
5 4 3 2 1
1 2 3 4 5 6 7 8 9 10
A A
U500
35 36 C500 C501
GND3 GND7
23 GND2 GND6 39
12 43 50V 100nF 50V 100nF
GND1 GND5 0603 0603
8 GND0 GND4 44
PHY0_AD0 25 7 +3V3_PHY
INT/PHYAD0 VDDIO1
B MI_CLK/LINKPOL 2 MDC VDDIO0 24 B
1 13 PHY0_2V5
MI_DATA MDIO VDDC PHY0_2V5A
VDDRX 31
34 FXSD/FXEN VCCRCV 38
VDDTX 42
CRS0 22 47 PHY0_VPLL
COL0 CRS/RMII_BTB VDDPLL
21 COL/RMII
RX_ERR[0] 11 R500
RXER/ISO
RX_CLK[0] 10 RXC +3V3_PHY
RX_DV[0] 9 RXDV/PCS_LPBK 4.7k 5%
37 REXT PD 30 0603
PHY0_RX3 3
R501 PHY0_RX[0..3] PHY0_RX2 RXD3/PHYADR1
PHY0_RX[0..3] 4 RXD2/PHYADR2 RST 48 #RESET
6.49k PHY0_RX1 5
PHY0_RX0 RXD1/PHYADR3 0603
0603 6 RXD0/PHYADR4
C
46 100nF 50V C
1% XI CLK25OUT1
15 TXC/REFCLK C502 T500
14 TXER XO 45
TX_ENA[0] 16 TXEN
PHY0_TX3 20 DP_PHY0_TD+ 1 16 DP_PHY0_TX+
PHY0_TX[0..3] PHY0_TX2 TXD3 TD+ TX+
PHY0_TX[0..3] 19 TXD2
PHY0_TX1 18 PHY0_2V5A 2 15
PHY0_TX0 TXD1 TDCT TXCT
S1
17 TXD0 TX+ 41
40 DP_PHY0_TD- 3 14 DP_PHY0_TX- CON500
TX- TD- TX-
29
Molex 43860-0016
LED3/NWAYEN
28 LED2/DUPLEX RX+ 33 4 NC1 NC3 13
LINK_MII[0] 27 LED1/SPD100 RX- 32
26 LED0/TEST 5 NC2 NC4 12 1
2
D DP_PHY0_RD+ 6 11 DP_PHY0_RX+ 3 D
KS8721BL_LQFP48 RD+ RX+
4
7 RDCT RXCT 10 5
6
DP_PHY0_RD- 8 9 DP_PHY0_RX- 7
RD- RX-
8
H1102_Magnetics
R502
C503
49.9R 1%
0805 100nF 50V R503 R504
S2
0603 75R 75R
R505
0805 0805 Shield
49.9R 1% 5% 5% C504
0805 R506
E E
75R R508
R507
0805 75R
10nF 500V
49.9R 1% 5% 0805 1206
0805 5% R510
C505
R509
1M 5%
50V 100nF 1206
49.9R 1%
0805 0603
GND_Earth
C506
GND_virtual_0
10nF 500V
F 1206 F
R511
R512
1M 5%
4.7k 5% PHY0_AD0
1206
0603
PHY0_2V5A
C507 C508 C511 C512
4Y4.7k RN501A CRS0 RMII back-to-back diabled
2 1 C509 C510
100nF 10uF 100nF 10nF
4Y4.7k RN501B COL0 RMII disabled 50V 100nF 100nF 6.3V 50V 50V
4 3 0603
0603 50V 50V 0805 0603
4Y4.7k RN501C RX_ERR[0] ISOLATE Mode disabled 0603 0603
6 5
A A
U600
35 36 C600 C601
GND3 GND7
23 GND2 GND6 39
12 43 50V 100nF 50V 100nF
GND1 GND5 0603 0603
8 GND0 GND4 44
PHY1_AD0 25 7 +3V3_PHY
INT/PHYAD0 VDDIO1
B MI_CLK/LINKPOL 2 MDC VDDIO0 24 B
1 13 PHY1_2V5
MI_DATA MDIO VDDC PHY1_2V5A
VDDRX 31
34 FXSD/FXEN VCCRCV 38
VDDTX 42
CRS1 22 47 PHY1_VPLL
COL1 CRS/RMII_BTB VDDPLL
21 COL/RMII
RX_ERR[1] 11 R600
RXER/ISO
RX_CLK[1] 10 RXC +3V3_PHY
RX_DV[1] 9 RXDV/PCS_LPBK 4.7k 5%
37 REXT PD 30 0603
PHY1_RX3 3
R601 PHY1_RX[0..3] PHY1_RX2 RXD3/PHYADR1
PHY1_RX[0..3] 4 RXD2/PHYADR2 RST 48 #RESET
6.49k PHY1_RX1 5
PHY1_RX0 RXD1/PHYADR3 C602
0603 6 RXD0/PHYADR4
C 100nF 50V C
1% XI 46 CLK25OUT1
15 TXC/REFCLK
14 45 0603 T600
TXER XO
TX_ENA[1] 16 TXEN
PHY1_TX3 20 DP_PHY1_TD+ 1 16 DP_PHY1_TX+
PHY1_TX[0..3] PHY1_TX2 TXD3 TD+ TX+
PHY1_TX[0..3] 19 TXD2
PHY1_TX1 18 PHY1_2V5A 2 15
PHY1_TX0 TXD1 TDCT TXCT
S1
17 TXD0 TX+ 41
40 DP_PHY1_TD- 3 14 DP_PHY1_TX- CON600
TX- TD- TX-
29
Molex 43860-0016
LED3/NWAYEN
28 LED2/DUPLEX RX+ 33 4 NC1 NC3 13
LINK_MII[1] 27 LED1/SPD100 RX- 32
26 LED0/TEST 5 NC2 NC4 12 1
2
D DP_PHY1_RD+ 6 11 DP_PHY1_RX+ 3 D
KS8721BL_LQFP48 RD+ RX+
4
7 RDCT RXCT 10 5
6
DP_PHY1_RD- 8 9 DP_PHY1_RX- 7
RD- RX-
8
H1102_Magnetics
R602
C603
49.9R 1%
0805 100nF 50V R603 R604
S2
0603 75R 75R
R605
0805 0805 Shield
49.9R 1% 5% 5%
0805 R606 C604
E E
75R R608
R607
0805 75R
0805 10nF 500V
49.9R 1% 5% 1206
0805 5% R609
C605
R610
1M 5%
50V 100nF 1206
49.9R 1%
0805 0603
GND_Earth
C606
GND_virtual_1
10nF 500V
F 1206 F
R611
R612 1M 5%
+3V3_PHY 4.7k 5% PHY1_AD0 1206
0603
PHY1_2V5A
C607 C610 C611 C612
4Y4.7k RN601A CRS1 RMII back-to-back diabled
2 1 C608 C609
100nF 10uF 100nF 10nF
4Y4.7k RN601B COL1 RMII disabled 50V 100nF 100nF 50V 50V
4 3 6.3V 0603
0603 50V 50V 0603
RN601C 0603 0603 0805
4Y4.7k 6 5 RX_ERR[1] ISOLATE Mode disabled
For specific PDI configuration refer to the ET1100 Datasheet and Configuration and Pinout.XLS
http://www.beckhoff.com/english/download/ethercat_development_products.htm R700
C25_ENA CLK25OUT2 (PDI31) disabled
4.7k 1%
0603
For LEDs please refer to the EtherCAT Indicator Specification.
C C
D701
R710
2 1 +3V3
470R 5%
0603 R711
green CL-190G
0603 Trans-Mode-Ena Transparent Mode disabled (TRANS_MODE_ENA = 0)
POR Value: 4.7k 1%
P_CONF[1]= 1 (Port1 = MII) 0603
B B
The RUN-LED shall be viewable without removing covers or parts from the devices
R712
PHYAD_OFF PHY Address Offset = 0
4.7k 1%
RUN/E²PROM-Size 0603
D702 R713
RUN/EEPROM_SIZE 1 2
470R 5%
green CL-190G 0603
0603
R714
4.7k 1% Link Polarity = 0 MII Ports PD (R715) cross current MI_CLK current (max.)
0603 POR Value: R715
E²PPROM-Size = 0 (16 kBit) MI_CLK/LINKPOL 1 Port R=2K 5% Iq=0,3mA Ip=1,5mA
1k 5% (specific for Micrel KS8721BL,
0603 2 Ports R=1K 5% Iq=0,7mA Ip=2,7mA
because of undocumented 3 Ports R=680R 5% Iq=1,0mA Ip=3,5mA (ext. clk_driver recommended)
internal Pull-Up of 12.5K+-30% ) 4 Ports R=510R 1% Iq=1,4mA Ip=4,25mA (ext. clk_driver recommended)
A A
D D
+3V3 +3V3
U800B
C806
C807 C808 C809 C800 C801 C802 C803 C804 C805 C810 +2V5_CORE C6 D6
10uF VCC-CORE0 GND-CORE0
220pF 220pF 220pF 220pF 220pF 220pF 220pF 220pF 220pF 220pF C7 VCC-CORE1 GND-CORE1 D7
6.3V K6 J6
50V 50V 50V 50V 50V 50V 50V 50V 50V 50V VCC-CORE2 GND-CORE2
0805 K7 J7
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 +3V3 VCC-CORE3 GND-CORE3
C5 VCC-IO0
D10 VCC-IO1 GND-IO0 D4
D3 VCC-IO2 GND-IO1 D5
E9 VCC-IO3 GND-IO2 D9
F10 VCC-IO4 GND-IO3 F9
J10 VCC-IO5 GND-IO4 J4
J3 VCC-IO6 GND-IO5 J5
K5 VCC-IO7 GND-IO6 J8
K8 VCC-IO8 GND-IO7 J9
+3V3
+2V5_PLL G10 G9
C VCC-PLL GND-PLL C
nc1 E4
nc2 G3
nc3 G4
C811 C812 C813 C814 C815 C816 C817 C818 C819 C820 C821 +3V3 E10
nc4
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF F3 TESTCONF[0]/VCC-IO nc5 C8
50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V H4 TESTCONF[1]/GND-IO nc6 H10
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 K9 TESTCONF[2]/GND-IO nc7 F4
H9 TESTCONF[3]/VCC-IO nc8 D8
+3V3
ET1100_BGA128_generic
+2V5_CORE +2V5_PLL
C822 C823 C824 C825 C826 C827 C828 C829 C830 C831 C832
10uF 100nF 100nF 100nF 100nF 100nF 220pF 220pF 220pF 220pF 220pF
B 6.3V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V B
0805 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
A A