CAN Signals, Data Packets & Cyclic Redundancy Check

Differential CAN Signal Inversion for Dominant and Recessive Bus States
Transmitter Transceiver
Input Signal Transmit
Logic 1 = High Transceiver
Logic 0 = Low Input
CAN Bus (Inverted) High
Logic 1 = Low Speed
⇒ Recessive
Logic 0 = High
CAN Bus
⇒ Dominant Signals
Receiver Transceiver Receive
Output Signal Transceiver
Logic 1 = High Output
Logic 0 = Low

Logic 0 ⇒ Tranceiver output: Dominant (high) Logic 1 ⇒ Tranceiver output: Recessive (low)

CAN Data Frame Bit Field Format

Length
Field name Purpose
(bits)
Start-of-frame 1 Denotes the start of frame transmission [Dominant (0)]
Identifier 11 Mesage identifier which also represents the message priority
Remote Transmission Request a data frame from a remote node. Least significant bit of
1
Request (RTR) arbitration field
Dominant (0) for standard frame format,
IDentifier Extension (IDE) 1
Recessive (1) indicates extended frame format
Reserved bit is dominant (0), but accepted as either dominant or
Reserved bit (R0) 1
recessive
Data length code (DLC)* 4 Number of bytes of data (0–8 bytes)
Data field [red] 0–64 Data to be transmitted (length in bytes dictated by DLC field)
CRC 15 Cyclic Redundancy Check
CRC delimiter 1 Must be recessive (1)
ACK slot 1 Transmitter sends recessive (1) and receiver asserts dominant (0)
ACK delimiter 1 Must be recessive (1)
End-of-frame (EOF) 7 Must be recessive (1)
Modified from http://en.wikipedia.org/wiki/CAN_bus
 CAN Data Packets with Signal Inversion and Arbitration
Dominant Bus State Recessive Bus State

(Electrical
Signals) 1 8

(Transceiver
Input) 5 6

2 4
(Transceiver 7
Input)
3

(Transceiver
Input)
1. Node A is transmitting 5. Nodes A & B AckNode C transmission
2. Nodes B & C Ack Node A 6. Node B transmits without contention
3. Nodes B & C compete for bus 7. Nodes A & C Ack Node B
4. Node C wins arbitration and transmits 8. Node A transmits without contention

Cyclic Redundancy Check (CRC)

In CAN 2.0, the cyclic redundancy check (CRC) method is used for detection of bit errors. The
polynomial used in CAN 2.0 is:
gCAN (x) = x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1 = 1100 0101 1001 10012
When coding a data block, 15 zero bits are appended to the bits assembled so far. This extended block is
then interpreted as a polynomial (where the data bits serve as binary coefficients) and is divided by the
polynomial gCAN (x). Binary modulo 2 arithmetic is used meaning that borrows and carries are discarded.
The remainder of this division is a polynomial r(x) which has a degree of 14 (or less) replaces the 15 zero
bits at the end of the extended block. This ensures that the division of the so formed extended block by
gCAN (x) will produce a remainder of zero in the CAN receiver. If the remainder is non-zero, one or more
bit errors have occurred. The polynomial divisions are usually realized in hardware using binary shift
registers and XOR gates.
E. Zivi March 23, 2015