UNIT I - The 8086 Microprocessor

Microprocessor:
A silicon chip that contains a CPU. In the world of personal Computers, the
terms microprocessor and CPU are used interchangeably. A microprocessor
(sometimes abbreviated μP) is a digital electronic component with miniaturized
transistors on a single semiconductor integrated circuit (IC).
Introduction:
• First Microprocessor – IN 4004 in1971
• First 8 – bit microprocessor – IN 8008 in1972
• IN 8085 – Functionally complete microprocessor.
Introduction to 8086:
8086 Overview:
• It is a 16 bit µp. Introduced in the year1978.
• 8086has 16-bit ALU; this means 16-bit numbers are directly processed by8086.
• It has 16-bit data bus, so it can read data or write data to memory or I/O ports
either 16 bits or 8 bits at a time.
• 8086 is first x86microprocessor.
The term x86 refers to a family of instruction set architectures based on the Intel 8086
CPU.
8086 Features:
• It is a 16-bitμp.
• 8086 has a 20 bit address bus can access up to 220 memory locations (1MB).
• It can support up to 64K I/O ports.
• It provides 14, 16 –bit registers.
• It has multiplexed address and data bus AD0- AD15 and A16 –A19.
• It requires single phase clock with 33% duty cycle to provide internal timing.
• 8086 is designed to operate in two modes, Minimum and Maximum.
• It can prefetches up to 6 instruction bytes from memory and queues
them in order to speed up instruction execution.
• It requires +5V power supply.
• A 40 pin dual in line package
Microprocessor Architecture:
8086 has two blocks BIU and EU.
• BIU(bus interface unit) sends out addresses, fetches instructions from memory,
reads data from ports and memory, and writes data to ports and memory. In other
words, the BIU handles all transfers of data and addresses on the buses for the
execution unit.
• The instruction bytes are transferred to the instruction queue (6-byteslong).
• EU (execution unit) of the 8086 tells the BIU where to fetch instructions or data
from, decodes instructions, and executes instructions.
Memory segmentation:
• 16 – Logical segments.
• The 16-bit contents of the segment register actually point to the starting
location of the particular segment.
• To address a specific memory location within a segment, we need an offset
address.
• The offset address is also 16-bits long – Size of each segment: 64K.

Advantages of Segmented Memory Scheme:

1. Allows the memory capacity to be on 1- Mbytes although the actual addresses
to be handled are of 16-bitsize.
2. Allows the placing of code, data and stack portions of the same program in
different parts (Segments) of memory, for data and code protection
3. Permits a program and / or its data to be put into different areas of memory
each time the program is executed, i.e., provision for relocation is done.
 Generating Physical Address:
Example:
• Segment address – 1005 H
• Offset address - 5555H
• Segment address - 0001 0000 00000101
• Shifted by 4-bit positions - 0001 0000 0000 0101 left
+
Offset Address- 0101 0101 0101 0101
Physical Address – 0001 0101 0101 0101 0101
1 5 5 A 5
20 bits address bus:
• It can address any one of 1,048,576 (=220) memory locations/addresses.
• Each memory location is one byte wide.
• To store a word of 16 bit 2 memory locations are required.
• If the first byte of the word is at even address 8086 can read the entire word in
one operation.
• If the first byte of the word is at an odd address, the 8086 will read the first
byte with one bus operation and the second byte with another bus operation.
Pipelining:
• The time slot is utilized in 8086 to achieve the overlapped fetch and execution
cycle.
• While the opcode is fetched by the Bus Interface unit (BIU), the Execution
Unit (EU) executes the previously decoded instruction concurrently by using
the instruction byte queue arrangement. Thus the BIU along with the
Execution Unit (EU) forms a pipeline.
Register Organization of 8086: General data registers:
Registers and its special functions:
Register Operations
AX Word multiply, Word Divide, Word I/O, Word String
AL Byte Multiply, Byte Divide, Byte I/O, Translate, Decimal/ ASCII
Arithmetic,
AH Byte Multiply, Byte Divide
BX Translate
CX Counter for String operations, Loops
CL Counter for Variable Shift and Rotate
DX Word Multiply, Word Divide, Indirect I/O.
Pointer and Index registers:
Pointer register Default Segment Register
BX DS
SI DS
DI DS (ES in case of String operations)
SP SS
BP SS
IP CS

Segment registers:
 The advantage of using segmented memory scheme is that, instead of using a
20-bit register for a physical address, the processor just maintains two 16-bit registers
which are within the word length capacity of the machine.
Code segment Register (CS): It is a 16-bit register which stores the starting or base
of the code segment.
Stack segment (SS): It is a 16-bit register which stores the starting or base of the
stack segment.
Data segment (DS): It is a 16-bit register which stores the starting or base of the data
segment.
Extra segment (ES): It is a 16-bit register which stores the starting or base of the
extra data segment.
Flag Register or Program Status Word (PSW):
Flags are a 16-bit register containing 9 one bit flags.
Overflow Flag (OF) –it is set when arithmetic overflow has occurred.
Direction Flag (DF) - If set then string manipulation instructions will auto-decrement
index registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Trap Flag (TF) - if set, it executes one instruction at a time.
Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result in accumulator is zero
Auxiliary carry Flag (AF) - set if there was a carry from D3 to D4 in the AL
register.
Parity Flag (PF) –when result in the accumulator has even number of 1PF is set 1.
Carry Flag (CF) - When carry come out of the last bit or MSB , CF is set to 1.
Addressing Modes:
Addressing mode is a method of locating data or operands. According to the
flow of instruction execution,
A] Sequential Control flow instructions
Ex, Arithmetic, Logical, data transfer, etc.
B] Control Transfer instructions
INT, Call, Ret and Jump.
A] Sequential Control flow instructions
1) Immediate Addressing
MOVAX, 0005H, MOV CL, 8FH
2) Direct Addressing ( Segment Override prefix)
MOV AX,[5000H]
Physical Address: (10H * DS) + 5000H
3) Register Addressing
MOVBX, AX MOV AL, CL
4) Register Indirect Addressing
MOV AX,[BX]
Effective / Physical Address: (10H * DS) + [BX]
5) Indexed Addressing
MOV AX,[SI]
Effective / Physical Address: (10H * DS) + [BX]
DS – default segment register for SI and DI except String manipulation instructions.
6) Register Relative addressing
MOV AX,50H[BX]
 • Here 50H : 8 – bit Immediate Displacement
• Effective Address: (10H * DS) + 50H+[BX]
7) Based Indexed addressing
• MOV AX,[BX][SI]
• Effective Address: (10H * DS) +[BX] +[SI]
8) Relative Based Indexed addressing
• MOV AX, 50H [BX][SI]
• Effective Address: (10H * DS) + 50H +[BX] +[SI]
B] Branch Category / Control transfer
Inter Segment: Control is transferred to different segment Intra Segment: Same or
within the segment
1) Intra-segment Direct
JMP SHORT NEXT; same segment, NEXT - Label
2) Intra-segment Indirect
JMP [BX]; Jump to effective address stored in BX
3) Intersegment Direct
JMP 5000H:2000H; Jump to effective address 2000H in segment 5000H.
4) Intersegment Indirect
JMP [2000H] ; Jump to an address in the other segment specified at effective
address 2000H in DS, that points to the memory block as shown below:
Address of Destination is at: (10H * DS) + 2000H
Assume DS = 3000H. Therefore at 32000H – 32003 H Locations both segment and
offset address are available
INSTRUCTION SET OF8086
The 8086 instructions are categorized into the following main types.
1. Data Copy / Transfer Instructions
2. Arithmetic and Logical Instructions
3. Shift and Rotate Instructions
4. Loop Instructions
5. Branch Instructions
6. String Instructions
7. Flag Manipulation Instructions
8. Machine Control Instructions
Data Copy / Transfer Instructions:
MOV move byte or word to register or memory
IN,OUT input byte or word from port, output word to port
LEA load effective address
LDS, LES load pointer using data segment, extra segment
PUSH, POP push word onto stack, pop word off stack
XCHG exchange byte or word
XLAT translate byte using look-up table
Arithmetical and Logical Instructions:
ADD, SUB Add, subtract byte or word
ADC, SBB Add, subtract byte or word and carry
INC, DEC increment, decrement byte or word
NEG negate byte or word (two’s complement)
CMP compare byte or word
MUL, DIV multiply, divide byte or word
IMUL, IDIV integer multiply, divide byte or word (Signed)
CBW, CWD convert byte to word, word to double word
AAA,AAS,AAM,AAD Ascii adjust for addition, subtraction, multiplication, division
DAA,DAS Decimal adjust for addition, subtraction
 NOT Logical not of byte or word (one’s complement)
AND Logical and of byte or word
OR Logical or of byte or word
XOR Logical x-or of byte or word
TEST test byte of word
Shift and Rotate
SHL,SHR Logical shift left, right byte or word by 1 or CL
SAL,SAR arithmetic shift left, right byte or word by 1 or CL
ROL, ROR Rotate left, right byte or word by 1 or CL
RCL, RCR rotate left, right through carry byte or word by 1 or CL
Loop and Branch Instruction
JMP Unconditional jump
JA (JNBE) Jump if above
JAE Jump if above or equal
JB Jump if below
JBE Jump if below or equal
JE Jump if equal
JG Jump if greater
JGE Jump if greater or equal
CALL, RET Call, return from procedure
INT, INT0 Software interrupt, interrupt if overflow
IRET Return from interrupt
String Instructions
MOVS Move byte or word string
MOVSB,MOVSW Move byte, word string
CMPS Compare byte or word string
SCAS Scan byte or word string
LODS, STOS Load, store byte or word string
REP Repeat
REPE, REPZ Repeat while equal, zero
REPNE,REPNZ Repeat while not equal zero
Processor Control Instructions
STC, CLC, CMC Set, clear, complement carry flag
STD, CLD Set, clear direction flag
STI, CLI Set, clear interrupt enable flag
LAHF,SAHF Load AH from flags, store AH into flags
PUSHF, POPF Push flags onto stack, pop flags off stack
ESC Escape to external processor interface
LOCK Lock bus during next instruction
NOP No operation
WAIT Wait for signal on test input
HLT Halt processor

Assembler directives:
There are some instructions in the assembly language which are not a part of processor
instruction set. These instructions are instructions to the assembler, linker and loader.
 These are referred to as pseudo-operations or as assembler directives.
ALIGN – aligns next variable or instruction to byte which is multiple of operand.
ASSUME – selects segment registers to be default for all symbol in segments.
COMMENT- indicates a comment
DB- allocates and optionally initializes bytes of storage
DW-allocates and optionally initializes words of storage
DD-allocates and optionally initializes double words of storage
DQ- allocates and optionally initializes quad words of storage
DT- allocates and optionally initializes 10 byte long storage units
END- terminates assembly; optionally indices program entry point
ENDM- terminates a macro definition
ENDP- marks end of procedure definition
ENDS- marks end of segment or structure
EQU- assigns expression to name
EVEN- aligns next variable or instruction to even byte
EXITM- terminates macro definition
EXTRN- indicates externally defined symbols
LABEL- creates a new label with specified type and current location counter
LOCAL- declares local variable in macro definition
MACRO-starts macro definition
MODEL- specifies mode for assembling the program
ORG-sets locations counter to argument
PAGE-sets length and width of program listing; generates page break PROC- starts
procedure definition
PTR-assigns a specific type to a variable or to a label
PUBLIC- identifies symbols to be visible outside module
TITLE- defines the program listing title.
Assembly language programming:
In any microprocessor system the microprocessor only understands the
instructions in the binary form. There are three language levels that can be used to write
a program.
1. Machine level language programs
2. Assembly language level programs
3. High level language programs.
4. Assembler translates a source file that was created using the editor into machine
language such as binary or object code. First file is object file; second file is assembler
list file.
A linker is a program used to join together several object files into one large object file.
Modular Programming:
Usually, programming task is divided into subtasks, separate modules are
written for performing subtasks. Each module is tested separately. The common
routine required in modules are written in separate module and they are called from
individual modules as per requirements. Programming done in this fashion is called
modular programming.
Advantages:
1. Code is short, simple and easy to understand.
2. The scoping of variables can easily be controlled.
3. Documents can be easily understood.
While designing the modules programmers must consider the two things:
1. Control coupling between modules
2. Data coupling between modules
Control coupling refers to how and under what conditions the modules are entered and
excited.
Data coupling refers to how information is communicated between the modules.
Three assembly language components are used for the development of modular
programs.
1. Structures
2. Procedures or subroutines, Macros.
Linking and Relocation:
Generating machine code from assembly language program manually is very
time consuming and complex process. Thus assembly language tools such as
assembler, linker, loader and debugger are used to develop and execute assembly
language programs.
The first step in the development process is to write an assembly language. It is
input to the assembler. The assembler translates assembly language statements to their
binary equivalents usually known as object code. Time required to translate assembly
code to object code is called assemble time.
Assembler translates a source file that was created using the editor into machine
language such as binary or object code. First file is object file; second file is assembler
list file.
A linker is a program used to join together several object files into one large
object file. At the load time, the program loader copies the program into the computers
main memory and at execution time, the program execution begins.
Segment combination:
The segment with the same name is joined together according to the combined
type specified in the segment derivatives.
The segment derivatives take the form: Segment name Segment combine-type. Segment
with the same name but no combine-type will cause a linker error.
There are five possible combine-types:
1. PUBLIC
2. COMMON
3. STACK
4. AT
5. MEMORY
AT combine- type allows the user to specify the exact starting address of a
segment of code or data. Here the address of Variables and Labels set by the linker
and loader process and they are said to be relocatable.
AT combine- type the address of Variables and Labels set by the Programmer
and Assembler process and such variables and labels are known as absolute variables
and labels.

Access to External identifiers:

The variables and/or labels defined in the module itself are called local
(internal) identifiers) relative to the module. However, if they are not defined in the
module and defined in one of the other modules being linked, then they are called
external (global) identifiers relative to the module.
In order for a linker to be able to access data or procedure in another assembly
module correctly, use two assembly language directives: PUBLIC and EXTRN.
Every address has two parts.
1. Offset address
2. Segment address
The offset for local identifiers are inserted by the assembler. However, the
offset for the external identifiers and all segment address are inserted by the linking
process. Linking process determines the exact address for segment to be put in
memory and then the addresses are assigned to segment. This process is known as
relocation.
STACK:
The stack is a portion of read/write memory set aside by the user for the purpose of
storing information temporarily. When the information is written on the stack, the
operation is called PUSH. When the information is read from stack, the operation is
called POP.
Stack structure of 8086: SP is a 16 bit register. The stack pointer register contains 16
bit offset from the start of the segment to the top of the stack. For stack operation,
physical address is produced by adding the contents of stack pointer register to the
segment base address in 8086.
PUSH and POP operations:
Temporarily stores the contents of 16 bit register or memory location or program
status word and retrieves when required.
PUSH Operation: The PUSH instruction decrements stack pointer by two and copies
a word from source location in the stack where the stack pointer points. Here the
source must be a word. The source of the word can be a general purpose register, or a
segment register or memory.
POP Operation:
POP Operation: The POP instruction copies a word from the stack location pointed
by the stack pointer to the destination. The destination can be a general purpose
register, a segment register or a memory location. After the word is copied to the
specified destination, the stack pointer is automatically incremented by 2.
Procedures: Whenever we need to use a group of instructions several times
throughout the program there are two ways, one way is to write the group of
instructions as a separate procedure. Another way is to write the group of instructions
as Macros.
The type of procedure depends on where the procedure is stored in the
memory. If it is in the same code segment where the main program is stored then it is
called near procedure otherwise it is referred to as far procedure.
Re-entrant Procedure:
In some situations it may happen that procedure 1 is called from main
program, procedure 2 is called from procedure 1 and procedure 1 is again called from
procedure 2. In this situation program execution flow reenters in the procedure 1. This
type of procedures is called reentrant procedures.
Recursive Procedure:
A recursive procedure is a procedure which calls itself, Recursive procedures
are used to work with complex data structures called Trees.
Passing Parameters:
For processing it is necessary to pass these address variables or data, usually
referred as passing parameters to the procedure. There are four ways to pass
parameters to and from the procedure.
1. Using registers.
2. Using general memory
3. Using pointers
4. Using stack
Macros:
Macro is a group of instruction. The macro assembler generates the code in the
program each time where the macro is called. Macros are defined by MACRO & END
directives. Creating macro is similar to creating new opcode that can be used in the
program. The assembler places the macro instructions in the program each time when
it is invoked. This procedure is known as Macro expansion.
Passing parameters in Macro: In Macro, parameters are passed as a part of
statement which calls Macro.
Local variables in a macro: Body of the Macro can use local variables. A local
variable defined in the Macro is available in the Macro; however it is not available
outside the Macro. To define a local variable, LOCAL derivative is used.
Placing Macro definition in their own module: Macro module is a file which
contains only macros that are to be included in other program files. A macro module
file has extension.MAC or.INC.
Nested Macros: When macro call appears within a macro definition, the macros are
called nested macros.
Controlled Expansion (Conditional Assembly) Statements in Macros: In macros,
using parameters passed, it is possible to determine whether or not some part of the
prototype code should be ignored or which of the two alternate sets of prototype code
is to be used. Such ability of an assembler to select the code that is to be assembled is
called controlled expansion or conditional assembly.
Interrupts and interrupt service routines:
An interrupt is the method of processing the microprocessor by peripheral
device. An interrupt is used to cause a temporary halt in the execution of program.
Microprocessor responds to the interrupt with an interrupt service routine, which is
short program or subroutine that instructs the microprocessor on how to handle the
interrupt.
There are two basic type of interrupt, maskable and non-maskable, non-
maskable interrupt requires an immediate response by microprocessor, it usually used
for serious circumstances like power failure. A maskable interrupt is an interrupt that
the microprocessor can ignore depending upon some predetermined upon some
predetermined condition defined by status register.
Interrupt can be divided to five groups:
1. Hardware interrupt
2. Non-maskable interrupts
3. Maskable Interrupt
4. Software interrupt
Hardware, software and internal interrupt are serviced on priority basis. Each
interrupt is given a different priority level by assigning a type number. Type 0
identifies the highest-priority and type 255 identifies the lowest- priorities interrupt.
 The 8086 allow up to 256 vectored interrupts. This means that you can have up
to 256 different sources for an interrupt and the 80x86 will directly call the service
routine for that interrupt without any software processing. This is in contrast to non-
vectored interrupts that transfer control directly to a single interrupt service routine,
regardless of the interrupt source.
The 8086 provides a 256 entry of interrupt vector table. This is a 1K table
containing 256 4-byte entries. Each entry in this table contains a segmented address
that points at the interrupt service routine in memory. The lowest five types are
dedicated to specific interrupts such as the divide by zero interrupt and the non
maskable interrupt. The next 27 interrupt types, from 5 to 31 are reserved by Intel for
use in future microprocessors. The upper 224 interrupt types, from32 to 255, are
available to use for hardware and software interrupts.
When an interrupt occurs regardless of source, the 80x86 does the following:
1. The CPU pushes the flag register onto the stack.
2. The CPU pushes a far return address (segment: offset) onto the stack, segment value
first.
3. The CPU determines the cause of the interrupt (i.e., the interrupt number) and
fetches the four byte interrupt vector from address 0: vector*4.
4. The CPU transfers control to the routine specified by the interrupt
When the interrupt service routine wants to return control, it must execute an
IRET (interrupt return) instruction. The interrupt return pops the far return address and
the flags off the stack. Note that executing a far return is insufficient since that would
leave the flags on the stack.
1. HARDWARE INTERRUPT
Hardware interrupt is caused by any peripheral device by sending a signal through a
specified pin to the microprocessor.
2. NON-MASKABLE INTERRUPT (NMI)
The processor provides a single non-maskable interrupt pin (NMI) which has higher
priority than the maskable interrupt request pin (INTR). A typical use would be to
activate a power failure routine. The NMI is edge-triggered on a LOW-to-HIGH
transition. The activation of this pin causes a type 2 interrupt. NMI is required to have
duration in the HIGH state of greater than two CLK cycles, but is not required to be
synchronized to the clock. Any high-going transition of NMI is latched on-chip and
will be serviced at the end of the current instruction or between whole moves of a
block-type instruction. Worst case response to NMI would be for multiply, divide, and
variable shift instructions. There is no specification on the occurrence of the low-
going edge; it may occur before, during, or after the servicing of NMI.
Another High-going edge triggers another response if it occurs after the start of
the NMI procedure. The signal must be free of logical spikes in general and be free of
bounces on the low-going edge to avoid triggering extraneous responses.
3. MASKABLE INTERRUPT
Whenever an external signal activates the INTR pin, the microprocessor will be
interrupted only if interrupts are enabled using set interrupt Flag instruction. If the
interrupts are disabled using clear interrupt Flag instruction, the microprocessor will
not get interrupted even if INTR is activated. That is, INTR can be masked. INTR is a
non-vectored interrupt, which means, the 8086 does not know where to branch to
service the interrupt. The 8086 has to be told by an external device like a
Programmable Interrupt controller regarding the branch. Whenever the INTR pin is
activated by an I/O port, if Interrupts are enabled and NMI is not active at that time,
the microprocessor finishes the current instruction that is being executed and gives out
a ‘0’ on INTA pin twice. When INTA pin goes low for the first time, it asks the
external device to get ready. In response to the second INTA the microprocessor
receives the 8 bit, say N, from a programmable Interrupt controller. The action taken is
as follows.
1. Complete the current instruction.
2. Activates INTA output, and receives type Number, say N
3. Flag register value; CS value of the return address &IP value of their turn
address are pushed on to the stack.
4. IP value is loaded from contents of word location N x4.
5. CS is loaded from contents of the next word location.
6. Interrupt Flag and trap Flag are reset to0.
At the end of the ISS, there will be an IRET instruction. This performs popping
off from the stack top to IP, CS and Flag registers. Finally, the register values
which are also saved on the stack at the start of ISS are restored from the stack
and a return to the interrupted program takes place using the IRET instruction.
4. SOFTWARE INTERRUPTS
There are instructions in 8086 which cause an interrupt. They are
1. INT instructions with type number specified.
2. INT 3, Break Point Interrupt instruction.
3. INTO, interrupt on overflow instruction.
These are instructions at the desired places in a program. When one of these
instructions is executed a branch to an ISS takes place. Because their execution results
in a branch to an ISS, they are called interrupts. Software Interrupt instructions can be
used to test the working of the various Interrupt handlers- For example, we can
execute INTO instruction to execute type 0 ISS, without really having to divide a
number by 0. Similarly, we can execute INT 2 instruction to test NMIISS.
When the external device interrupts the processor, processor has to execute interrupt
service routine for servicing the interrupt. If the internal control circuit of the
processor produces a CALL to a predefined memory location which is the starting
address of interrupt service routine, then that address is called Vector address and such
interrupts are called vector interrupts.
The event that causes the interruption is called interrupt and the special routine
executed to service the interrupt is called interrupt service routine.
When the external device interrupts the processor, processor has to execute interrupt
service routine for servicing the interrupt. If the internal control circuit of the
processor produces a CALL to a predefined memory location which is the starting
address of interrupt service routine, then that address is called Vector address and such
interrupts are called vector interrupts.
In an 8086 system the first 1 Kbyte of memory from 00000H to 003FFH is reserved
for storing the stating address of interrupt service routines. This block of memory is
often called interrupt vector table or the interrupt pointer table.