TAMPERING DETECTION OF TRANSMISSION LINE
R LALIT KUMAR (071091101112),GYANENDRA
SINGH(071091101084),
GOURAV Kr. MISHRA(071091101081), JAYANT KUMAR
(071091101094)
GOUTHAM KUMAR (071091101082), GAURAV KRISHNA
(071091101075)
Department of Electrical and Electronics Engineering
Dr. MGR EDUCATIONAL AND RESEARCH INSTITUTE
(Dr. M.G.R University)
ABSTRACT:
The aim of our project is to detect the tamper
condition of transmission lines and also we
are finding the location name and substation
name. This fault will be detected by
comparing the two current transformers
output by using microcontroller. If the
difference exits between the CT’s output then
microcontroller will send as message via the
GSM modem. Today energy theft is a
worldwide problem that contributes heavily to
revenue losses. Transmission Lines can be
tampered using various ways like Partial
Earth Fault Condition. Swapping phase and
neutral, Disconnection of neutral Attaching
loads the between the sub stations. This
Project Detects the Transmission Lines
Tampering to the load by using tamper
Circuit that can done by using two current
transformers outputs which is connected in
the corresponding substations. It also alerts
the Electricity Board regarding the tampering
using a GSM Modem. This GSM message
Contains the information about the
substation name and location.
INTRODUCTION:
The AT89S52 is a low-power, high-
performance CMOS 8-bit microcontroller with
8K bytes of in-system programmable Flash
memory. The device is manufactured using
Atmel’s high-density nonvolatile memory
technology and is compatible with the Indus-
try-standard 80C51 instruction set and pin out.
The on-chip Flash allows the program memory
to be reprogrammed in-system or by a
conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU
with in-system programmable Flash on a
monolithic chip, the Atmel AT89S52 is a
powerful microcontroller which provides a
highly-flexible and cost-effective solution to
many embedded control applications. The
AT89S52 provides the following standard
features: 8K bytes of Flash, 256 bytes of RAM,
32 I/O lines, Watchdog timer, two data
pointers, three 16-bit timer/counters, a six-
vector two-level interrupt architecture, a full
duplex serial port, on-chip oscillator, and clock
circuitry. In addition, the AT89S52 is designed
with static logic for operation down to zero
frequency and supports two software selectable
power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters,
serial port, and interrupt system to continue
functioning. The Power-down mode saves the
RAM con-tents but freezes the oscillator,
disabling all other chip functions until the next
interrupt or hardware reset.
 • Embedded C language
FEATURES:
HARDWARE REQUIRMENT:
 Compatible with MCS®-51 Products
• Microcontroller
 8K Bytes of In-System Programmable
• CT’s
(ISP) Flash Memory –
Endurance: 1000 Write/Erase Cycles • GSM Modem

 4.0V to 5.5V Operating Range

 Fully Static Operation: 0 Hz to 33
MHz
 Three-level Program Memory Lock
 256 x 8-bit Internal RAM
 32 Programmable I/O Lines
 Three 16-bit Timer/Counters
 Eight Interrupt Sources
 Full Duplex UART Serial Channel
 Low-power Idle and Power-down
Modes
 Interrupt Recovery from Power-down Fig1: The figure above shows the block
Mode diagram of AT89s52 Microcontroller.

 Watchdog Timer
 Dual Data Pointer
 Power-off Flag
 Fast Programming Time
 Flexible ISP Programming (Byte and
Page Mode)

 Green (Pb/Halide-free) Packaging

Option.
CURRENT IMPLEMENTATION:

 To implement central observer Fig2: block diagram for the proposed project.
 meter along with transformer
 Central observer meter for
 monitoring power theft
 GSM communication for transferring
 information to station

SOFTWARE REQUIRMENT:
• Keil Uversion3
 TTL inputs. When 1s are written to port 0 pins,
the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the
multiplexed low-order address/data bus during
accesses to external program and data memory.
In this mode, P0 has internal pull-ups. Port 0
also receives the code bytes during Flash
programming and outputs the code bytes
during program verification. External pull-ups
Fig3:circuit diagram are required during program verification.

Port 1:
Port 1 is an 8-bit bidirectional I/O port with
internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are
PIN CONFIGURATIONS:
written to Port 1 pins, they are pulled high by
the inter-nal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are
externally being pulled low will source current
(IIL) because of the internal pull-ups. In
addition, P1.0 and P1.1 can be configured to be
the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input
(P1.1/T2EX), respectively, as shown in the
following table. Port 1 also receives the low-
order address bytes during Flash programming
and verification.

Fig2: The above figure depicts the pin diagram

for the microcontroller.
Pin Description:

VCC: Supply voltage.

GND :Ground.

Port 2:
Port 0:
Port 2 is an 8-bit bidirectional I/O port with
Port 0 is an 8-bit open drain bidirectional I/O
internal pull-ups. The Port 2 output buffers can
port. As an output port, each pin can sink eight
sink/source four TTL inputs. When 1s are
written to Port 2 pins, they are pulled high by
the internal pull-ups and can be used as inputs.
As inputs, Port 2 pins that are externally being
pulled low will source current (IIL) because of
the internal pull-ups. Port 2 emits the high-
order address byte during fetches from external
program memory and during accesses to
external data memory that uses 16-bit
addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups
when emitting 1s. During accesses to external
data memory that uses 8-bit addresses (MOVX
@ RI), Port 2 emits the contents of the P2
RST:
Special Function Register. Port 2 also receives
Reset input. A high on this pin for two
the high-order address bits and some control
machine cycles while the oscillator is running
signals during Flash programming and
resets the device. This pin drives high for 98
verification. Port Pin Alternate Functions
oscillator periods after the Watchdog times
P1.0 T2 (external count input to Timer/Counter
out. The DISRTO bit in SFR AUXR (address
2), clock-out P1.1 T2EX (Timer/Counter 2
8EH) can be used to disable this feature. In the
capture/reload trigger and direction control)
default state of bit DISRTO, the RESET HIGH
P1.5 MOSI (used for In-System Programming)
out feature is enabled.
P1.6 MISO (used for In-System Programming)
ALE/PROG:
P1.7 SCK (used for In-System Programming)
Address Latch Enable (ALE) is an output pulse
Port 3:
for latching the low byte of the address during
Port 3 is an 8-bit bidirectional I/O port with
accesses to external memory. This pin is also
internal pull-ups. The Port 3 output buffers can
the program pulse input (PROG) during Flash
sink/source four TTL inputs. When 1s are
programming. In normal operation, ALE is
written to Port 3 pins, they are pulled high by
emitted at a constant rate of 1/6 the oscillator
the internal pull-ups and can be used as inputs.
frequency and may be used for external timing
As inputs, Port 3 pins that are externally being
or clocking purposes. Note, however, that one
pulled low will source current (IIL) because of
ALE pulse is skipped during each access to
the pull-ups. Port 3 receives some control
external data memory. If desired, ALE
signals for Flash programming and
operation can be disabled by setting bit 0 of
verification. Port 3 also serves the functions of
SFR location 8EH. With the bit set, ALE is
various special features of the AT89S52, as
active only during a MOVX or MOVC
shown in the following table.
instruction. Otherwise, the pin is weakly pulled
high. Setting the ALE-disable bit has no effect
if the microcontroller is in external execution
mode.
PSEN:
Program Store Enable (PSEN) is the read
strobe to external program memory. When the
AT89S52 is executing code from external
program memory, PSEN is activated twice
each machine cycle, except that two PSEN
activations are skipped during each access to
external data memory.
EA/VPP:
External Access Enable. EA must be strapped
to GND in order to enable the device to fetch
code from external program memory locations
starting at 0000H up to FFFFH. Note,
however, that if lock bit 1 is programmed, EA
will be internally latched on reset. EA should
be strapped to VCC for internal program
executions. This pin also receives the 12-volt
programming enable voltage (VPP) during
Flash programming.
XTAL1:
Input to the inverting oscillator amplifier and
input to the internal clock operating circuit.
XTAL2:
Output from the inverting oscillator amplifier.
Memory Organization:
MCS-51 devices have a separate address
space for Program and Data Memory. Up to
64K bytes each of external Program and Data
Memory can be addressed.
Program Memory:
If the EA pin is connected to GND, all
program fetches are directed to external
memory. On the AT89S52, if EA is connected
to VCC, program fetches to addresses 0000H
through 1FFFH are directed to internal
memory and fetches to addresses 2000H
through FFFFH are to external memory.
Data Memory:
The AT89S52 implements 256 bytes of on-
chip RAM. The upper 128 bytes occupy a
parallel address space to the Special Function
Registers. This means that the upper 128 bytes
have the same addresses as the SFR space but
are physically separate from SFR space. When
an instruction accesses an internal location
above address 7FH, the address mode used in
the instruction specifies whether the CPU
accesses the upper 128 bytes of RAM or the
SFR space. Instructions which use direct
addressing access the SFR space. For example,
the following direct addressing instruction
accesses the SFR at location 0A0H (which is
P2). MOV 0A0H, #data Instructions that use
indirect addressing access the upper 128 bytes
of RAM. For example, the following indirect
addressing instruction, where R0 contains
0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H). MOV
@R0, #data Note that stack operations are
examples of indirect addressing, so the upper
128 bytes of data RAM are available as stack
space.
Watchdog Timer (One-time Enabled with
Reset-out):
The WDT is intended as a recovery method in
situations where the CPU may be subjected to
software upsets. The WDT consists of a 14-bit
counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to
disable from exiting reset. To enable the WDT,
a user must write 01EH and 0E1H in sequence
to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, it will increment
every machine cycle while the oscillator is
running. The WDT timeout period is
dependent on the external clock frequency.
There is no way to disable the WDT except
through reset (either hardware reset or WDT
overflow reset). When WDT over-flows, it will
drive an output RESET HIGH pulse at the RST
pin.
Using the WDT:
To enable the WDT, a user must write 01EH
and 0E1H in sequence to the WDTRST
register (SFR location 0A6H). When the WDT
is enabled, the user needs to service it by
writing 01EH and 0E1H to WDTRST to avoid
a WDT overflow. The 14-bit counter
overflows when it reaches 16383 (3FFFH), and
this will reset the device. When the WDT is
enabled, it will increment every machine cycle
while the oscillator is running. This means the
user must reset the WDT at least every 16383
machine cycles. To reset the WDT the user
must write 01EH and 0E1H to WDTRST.
WDTRST is a write-only register. The WDT
counter cannot be read or written. When WDT
overflows, it will generate an output RESET
pulse at the RST pin. The RESET pulse
duration is 98xTOSC, where TOSC = 1/FOSC.
To make the best use of the WDT, it should be
serviced in those sections of code that will
periodically be executed within the time
required to prevent a WDT reset.
WDT during Power-down and Idle:
In Power-down mode the oscillator stops,
which means the WDT also stops. While in
Power-down mode, the user does not need to
service the WDT. There are two methods of
exiting Power-down mode: by a hardware reset
or via a level-activated external interrupt which
is enabled prior to entering Power-down mode.
When Power-down is exited with hardware
reset, servicing the WDT should occur as it
normally does whenever the AT89S52 is reset.
Exiting Power-down with an interrupt is
significantly different. The interrupt is held
low long enough for the oscillator to stabilize.
When the interrupt is brought high, the
interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is
held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the
WDT be reset during the interrupt service for
the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow
within a few states of exiting Power-down, it is
best to reset the WDT just before entering
Power-down mode. Before going into the
IDLE mode, the WDIDLE bit in SFR AUXR
is used to determine whether the WDT
continues to count if enabled. The WDT keeps
counting during IDLE (WDIDLE bit = 0) as
the default state. To prevent the WDT from
resetting the AT89S52 while in IDLE mode,
the user should always set up a timer that will
periodically exit IDLE, service the WDT, and
reenter IDLE mode. With WDIDLE bit
enabled, the WDT will stop to count in IDLE
mode and resumes the count upon exit from
IDLE.
In order to further continue the process UART
is used to connect microcontroller to a gsm
Modem which acts as a device for output.
Fig: energy meter for the proposed system.
UART:
A universal asynchronous receiver/transmitter
is a piece of computer hardware that translates
data between parallel and serial forms. UARTs
are commonly used in conjunction with other useful for implementing RS-232 in devices that
communication standards such as EIA RS-232. otherwise do not need any voltages outside the
0 V to + 5 V range, as power supply design
A UART is usually an individual (or does not need to be made more complicated
part of an) integrated circuit used for serial just for driving the RS-232 in this case.The
communications over a computer or peripheral receivers reduce RS-232 inputs (which may be
device serial port. UARTs are now commonly as high as ± 25 V), to standard 5 V TTL levels.
included in microcontrollers. A dual UART or These receivers have a typical threshold of
DUART combines two UARTs into a single 1.3 V, and a typical hysteresis of 0.5 V.The
chip. Many modern ICs now come with a later MAX232A is backwards compatible with
UART that can also communicate the original MAX232 but may operate at
synchronously; these devices are called higher baud rates and can use smaller external
USARTs.The Universal Asynchronous capacitors – 0.1 μF in place of the 1.0 μF
Receiver/Transmitter (UART) controller is the capacitors used with the original device.
key component of the serial communications
subsystem of a computer. The UART takes
bytes of data and transmits the individual bits
in a sequential fashion. At the destination, a
second UART re-assembles the bits into
complete bytes. Serial transmission of digital
information (bits) through a single wire or
other medium is much more cost effective than
parallel transmission through multiple wires. A
UART is used to convert the transmitted
information between its sequential and parallel
form at each end of the link. Each UART
contains a shift register which is the Fig3: pin diagram for UART
fundamental method of conversion between Now comes the global systems for the mobile
serial and parallel forms. communicatins viz; GSM
It is the most popular standard for mobile
MAX232: phones in the world. Its promoter, the GSM
Association, estimates that 80% of the global
The MAX232 is an integrated circuit that
mobile market uses the standard. GSM is used
converts signals from an RS-232 serial port to
by over 3 billion people across more than 212
signals suitable for use in TTL compatible
countries and territories. Its ubiquity makes
digital logic circuits. The MAX232 is a dual
international roaming very common between
driver/receiver and typically converts the RX,
mobile phone operators, enabling subscribers
TX, CTS and RTS signals.The drivers provide
to use their phones in many parts of the world.
RS-232 voltage level outputs (approx. ± 7.5 V)
GSM differs from its predecessors in that both
from a single + 5 V supply via on-chip charge
signaling and speech channels are digital, and
pumps and external capacitors. This makes it
thus is considered a second generation (2G)
mobile phone system. This has also meant that
data communication was easy to build into the
system. GSM EDGE is a 3G version of the
protocol.
Fig: a prototype of Global system for mobile
communications (GSM)
SALIENT FEATURES OF GSM:
• DB9 RS232 interface with voice
function
• Based on Waveform module Q2303A
• 3V SIM card slot
• SIM Application Toolkit
• Double tone multi-frequency function
(DTMF)
• Send and receive data and SMS
• Antenna with high sensitivity
• Comply with ETSI GSM Phase2+
• Dual-band
• Class 42W @ 900MHz
• Class 11W @ 1800MHz
• Input voltage6V-36V DC
• Input current1A-2A
• Standby current: 56mA
• Working current: 100-140mA
• Working temperature -20 -+55
• Storage temperature:-25 -+70
• Accessories: AC/DC adaptor, DB9
RS232 cable, antenna, 2 mounting
plates, CD
• Data transfer CSD up to 14.4 kbps,
USSD, Non transparent mode, V.110
supports different character framing.
ADVANTAGES:
 Easy for Identification.
 Implementation is very simple.
 Power saving
 Computer need not necessary
 High reliability
APPLICATIONS:
 Power theft
 Fault identification
 Transformer monitoring
CONCLUSION:
Power theft can be monitored easily. Tampered
meters monitored through central observer
unit. Energy Billing are done automatically.
Efficient way of communication between
users and transformers. High reliability.
REFERENCES:
 Bandim, C.J., Pinto Junior, A.V.,
Alvarenga, L.M., Loureiro, M.R.B.,
Santos, J.C.R., Galvez-Durand, F.,
“Loss Evaluation in Distribution
Systems”
 Singhal, S. , “ The role of metering
in revenue protection” Metering
and Tariffs for Energy Supply, 1999
 Bandim, C.J., Souza, F.C.,
Alvarenga, L.M., Pinto Junior, A.V.,
Luiz, F.C., Alves Junior, J.E.R.,
F., Loureiro, M.R.B., Dantas,
R.,- “Centralized Metering System
In Buildings”