VLSI Lab Report

Lab Report on 3-input NOR gate (DRC and LVS check)

Submitted To:

Md. Asaduz Zaman Mamun

Lecturer,
Department of EEE, SUST.

Submitted by:
Md. Faiyaz Bin Hassan
Reg. No: 2016338003
and
Sanjida Sultana
Reg. No: 2016338004
Group No: 03

Date of Submission: 28th March, 2020

Contents
1 Objective 2

2 Introductory theory 2

3 Designing the 3-input NOR layout 3

3.1 Designing PMOS layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Designing NMOS layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Adding the Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.4 Creating Input-Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5 Final Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Problems and Solutions 6

4.1 Finding and solving the DRC errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1.1 What are DRC errors? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1.2 Finding the DRC errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1.3 Solving the DRC errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Finding and Solving LVS mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.1 What are LVS mismatches? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.2 Finding the LVS mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Area Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Discussion 10

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1 Objective
• To make a 3-input NOR Gate layout using the Layout Editor of Cadence.

• To perform a Design Rule Check (DRC) of the layout.

• To perform the Layout Vs. Schematic (LVS) check of NOR Gate layout.

2 Introductory theory
A NOR gate is a universal logic gate which produces a ‘true/high’ output only when all the values
in the input are ‘false/low’. For an OR gate, we get a ‘high’ output when at least one of the input
values is ‘high’. A NOR gate produces a complement of the result of an OR gate justifying the name
NOR (Not-OR). Therefore, if we combine an OR gate with a NOT gate, we’ll get a NOR gate. In this
experiment, we’ll be using cadence’s layout editor to make a 3-input NOR gate layout with PMOS
and NMOS. After that, we’ll run DRC and LVS check of the design for possible errors. For a 3-input
NOR gate, the logic gate OR truth table go as the following figure:

Figure 1: The logic gate symbol and the truth table of a 3-input NOR gate

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The NMOS transistors will consist of Poly, Nimp, Metal1, Oxide and Cont layers. We’ll change the
parameters of all the shapes according to the pre-specified parameters. PMOS transistors have an
extra Nwell layer and instead of Nimp, we’ll use the Pimp layer. As similar to the NMOS transistors,
we’ll change the parameters of all the shapes made with these layers according to the given data.
Next, we’ll add the ground and Vdd bus using two metal2 layers.
We’ll add input/output pads and define the I/O, gnd, and Vdd pins.
We’ll use bus wiring to interconnect the components.
After that, we’ll bias the p-substrate and n-well using nimp, pimp, oxide, and contact layer. We’ll
need to create more contacts for establishing contacts between the metal layers, poly gates, and IO
pads etc.
We’ll use Virtuoso Layout Suite L. for creating the NOR layout.

3 Designing the 3-input NOR layout

3.1 Designing PMOS layout
We used Contact, Metal1, Oxide, Poly, Pimp, and Nwell layers to create the PMOS. For biasing, we
added an n-substrate to the PMOS which required us to use Contact, Metal1, Oxide, and Nimp layer.

Figure 2: PMOS Layout

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3.2 Designing NMOS layout
We used Contact, Metal1, Oxide, Poly,and Nimp layers to create the NMOS. For biasing, we added a
p-substrate to the NMOS which required us to use Contact, Metal1, Oxide, and Pimp layer.

Figure 3: NMOS Layout

3.3 Adding the Sources

In this step, we added two metal2 layers at a specific distance from the PMOS and NMOS layouts.
These two are used as Vdd and Gnd. We connected the PMOS to the Vdd and the NMOS to the Gnd.
The figures looks like the below given pictures.

Figure 4: PMOS with Vdd Figure 5: NMOS with Gnd

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3.4 Creating Input-Output Pins
We created 6 metal1 boxes outside the circuit area. These bxes represent the Vdd , Gnd, Output, and
Input pins (Ain , Cin , and Cin ). After that, we used bus wiring to make connections between metal1
to metal1, metal2, and poly layers to complete the layout. We created ’via’ to establish connections
between different layers. The Final connections look like the following picture.

Figure 6: Complete layout with Input-Output pin connections to the MOSFETs

3.5 Final Layout

Figure 6 shows us the complete layout including the I/O pin connections. The overall layout without
the input output pins looks like the following-

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 Figure 7: Final Layout (without I/O pins)

4 Problems and Solutions

4.1 Finding and solving the DRC errors
4.1.1 What are DRC errors?
For making a layout, we used many different layers including cont, metal1, metal 2, oxide, nimp, pimp,
poly, etc layers. While designing, we used one layer to enclose another, or overlap on another. The
technology library that we used for making the layout is gpdk090. This library has a certain design
rule guide. We have to-
• Maintain a proper area for certain layers when we create shapes.
• Maintain pre-specified spacing from one layer to another.
• Maintain a minimum distance for enclosing and overlapping objects.
If such rules are not followed properly, we find the DRC errors. Upon solving those erros, we can find
the efficient an efficient layout.

4.1.2 Finding the DRC errors

We used the DRC Run option from the Assura menu to find the Design Rule Check(DRC) errors. For
the layout we designed, we found the following errors:

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 Figure 8: DRC Errors

The meanings of these error messages are as following:

1. The first error means the p-substrate is not properly placed.

2. The nwell isn’t placed properly.

3. Two oxide layers were left uncovered without Nimp or Pimp layer.

4. Some Poly layers’ area were less than 0.1 um.

5. Some Cont shapes had areas greater or less than 0.12*0.12 um.

6. Poly to Contact area’s enclosing distance ere less than 0.04 um.

7. Some Contact layers weren’t covered by oxide or poly layer.

8. Two contact layers had no spacing with the enclosing metal1 layers,

9. Metal1 area was less than 0.07 um.

10. The Vdd Metal2 layer was at more than 25 um distance from the PMOS.

11. The Gnd Metal2 layer was at more than 25 um distance from the NMOS.

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4.1.3 Solving the DRC errors
From the previous section, we know the meaning of each of these errors. We fixed them as per the
requirement. Bringing change to these criteria, we were able to solve all the design errors.

Figure 9: DRC errors solved

4.2 Finding and Solving LVS mismatches

4.2.1 What are LVS mismatches?
LVS stands as an Acronym for Layout VS Schematic. When we make a schematic for a circuit and
design its layout, the parameters and networks of the layout and schematic will match with each
others’ if we maintain the correct parameters of the components.
However, when the area, length, width, etc parameters and the connections of the Schematic’s and
Layout’s components don’t match, we find LVS errors after LVS run.

4.2.2 Finding the LVS mismatches

We designed a schematic of a 3-input NOR gate using cadence’s schematic editor. We used the
LVS Run option from the Assura menu in Cadence’s layout editor to find the Layout VS. Schematic
(LVS) mismatches. For the schematic and layout we designed, we found no LVS mismatches.

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 Figure 10: LVS Run output

4.3 Area Measurement

Using the Ruler Attribute, we can obtain the total area of the layout.
We couldn’t achieve the minimum size of the layout. We were given pre-specified data about the
width of the layers, spacing between them, etc. When we used those data, we found some errors in
the layout. Therefore, we had to change some parameters. Due to fixing the errors by changing the
measurements, we could not achieve the minimum size.

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 Figure 11: Area of the layout

For our layout, the total area, as we see from figure-11, is 139.045nmX91.175nm
The distance from PMOS to NMOS is 2.99nm.

5 Discussion
1. Section 4.2.2 shows us a list of errors found from the DRC run. These errors occurred due to
not using the parameters properly. Also, we should have followed the λ-rule (lambda rule) so
that we could design a minimum sized layout.

2. We can use the 3-input NOR gate layout in building other macro-level layouts that use NOR
gate as a constituent. We can make use of the hierarchical designing to build complex systems
using this layout. This will reduce our time and effort to make same layout again and again.
The error fixing will also become trouble-free.
However, for digital designing, NOR gate layout is used less as a constituent than a NAND gate
layout. This is because NOR gate occupies more area than a NAND gate. The logical effort for
NOR is higher, and hence, the delay in NOR gate is also higher.

The END

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