IEEE Int. Conf.

Neural Networks 8 Signal Processing

Nanjing, China, December 14-17. 2003

HIGH SPEED VIDEO SIGNAL ACQUISITION AND PROCESSING SYSTEM

BASED ON FPGA TECHNIQUE
Dongming Lu, Qian Chen. Kefeng Weng, Ageng Zhang

Optoelectronic Engineering Research Center

441 lab, Elec. Eng. & Opto. Tech. College, Nanjing University of Science and Technology,
Nanjing, Jiangsu, 210094, P.R.China

ABSTRACT and adopt the art of FPGA to fulfill )he operation.

PCI bus structure, for its high transmission speed and
In the past few years, there has been significant progress in excellent transfer performance, is employed to perform the
the communications and computer technology, which interface between the system and the computer.
requires stable, clear video image display. On the other In this way, we achieve the digital video signal
hand, conventional analog video processing method, due acquiring and processing system that is mainly applied to
to its intrinsic limitations, can not meet the requirement of signal with low signal to noise ratio.
high quality and high spced operation. Meanwhile, the
digital video processing technique that integrates with the 2. DIGITAL VIDEO SIGNAL PROCESSING
computer technology is growing rapidly. In this paper, we METHOD
introduce the art of FPGA (Field Programmable Gate
Array) that has been widely used for video signal
processing, and develop the video signal acquisition and
processing system that based on FPGA, thereby achieve
real-time video signal acquiring, processing, and
transferring.

1. INTRODUCTION
For video signal processing, there are two characteristics,
one is the mass of data to handle; the other is the
requirement of high speed and real-time process. In this
regard, there are many limitations in the analog video
processing system: analog information is difficult to store
up; signal is vulnerable to disturbance and noise could
accumulate easily; transmission channel with strict
standard is demanded brightness and color often interfere
with each other, and so on. These intrinsic flaws in analog
video system can not be resolved within the system itself.
Digital operating technique not only can improve the
quality of image signal, hut more importantly, it can also
be integrated with the modem digital communications and
computer technology. Moreover, the digital processing
method can accomplish from one dimension, two
dimension, to three dimension geometly transform, and all
kinds of brightness and color transform, which makes
video signal processing approximate to optical operating
effect.
Therefore, we combine the well-developed digital
signal processing method with the computer technology,
Fig.1 Front End Operation
From the early days of analog mode, to the introductionof
digital processing method, until the naissance of HDTV,
TV and related video signal operation technique have gone
through a evolution of more than 70 years. During this
period, a series of digital video operating methods have
been developed, such as digital clamping, digital filter,
auto gain control, brightness and color separation and
chroma demodulation; chroma, contrast and saturation
adjusting; and digital phase-locked loop technique. Fig. 1
shows the structure of digital video signal acquiring
front-end. Introducing these digital front-end operating
method can eliminate a variety of instahility, and ensure
more precise image pixel read. Furthermore, the HDTV
revolutionizes the existing analog TV system standard,
aiming to establish a complete set of exclusively digital
video processing, transmitting and display system.
2.1. Digital Clamping Technique
The DC component in the analog video signal does not

0-7803-7702-8/03/ $17.00 02003 IEEE 1233

come out with the signal. Therefore, as the fust step, fulfilled by FPGA internal programmable logic. In this
(nonlinear operation in particular), we have to recover the way, the operation time can be reduced significantly.
DC voltage by clamping the image signal. Digital
feedback clamping circuit is generally adopted.

2.2. Digital phase-locked loop

Digital phase-locked loop is a sort of feedback control

system all the same. Unlike the analog phase-locked loop,
the digital phase-locked loop realizes exact phase locking
by the reversible counter generating cany or borrow pulse.
It synchronizes the frequency and the phase of the output
with those of the input video horizontal sync. Furthermore,
it utilizes the output oscillation signal as pixel clock for the
digitization circuit.

2.3. Digital Filter

In digital video signal processing system, digital filter is

generally used for the frequency domain processing, for
instance, brightness and color separation, chroma decoding,
figure enhancement, noise suppression. Digital filter has
simple structure, and can be easily adjusted. Moreover, it
can achieve good filter effect that could not be attained by
some analog filter, and has good linear phase performance.
3. FPGAAND FUNCTION
Fig 3 The block Diagram of FPGA internal logic
In this paper, we only focus on the algorithm that can
improve the signal-to-noise ratio, which we called digital
multi-frameaccumulation (Fig. 2).
Based on the theory of correlation detection, the time
distribution characteristics of noise is random and
un-correlated, while the signal is correlated. Then after m
frames image accumulation, the signal power is enhanced
by m*m times, whereas the noise power is only increased
by m times. Therefore, the signal-to-noise ratio of the
image can he improved m times after m frames imagg
accumulation. According to the analysis of experiment

nmI I I data, the image accumulation method is very effective in

suppressing the temporal noise.

4. PCI BUS INTERFACE TECHNIQUE

I I U

Fig2 Digital multi-frame accumulation

FPGA is a kind of PLD used widely, which bas the

flexibility of on-line programmable function. We employ it
907
32-bitEMkLccalBs

as the core controller of the whole processing system. It

serves as follows (See Fig 3):
1) control the input and output of the analog video
signal; I
2) accomplish digital image transmission by reading the
image data to PC memory;
3 ) its arithmetic module performs various image
n I 32-bit 3Bth Sptm FCI Bs h

operation; Fig.4 PCI Target Adapter Card

To accomplish real-time processing, all operations are

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The PCI bus is independent from the processor, whose
address, data, and control signal are generated separately.
Therefore, the PCI device design will not be affected by
the processor upgrade. PCI bus has the following
characteristics:
1 ) high speed, a 32 bit PCI bus supports 132 Mbits per
second peak transfer rate for both reading and
writing;
2) low-power consumption;
3) bursting mode can be performed on all read and write
transfers;
4) software transparent;
Based on its high transfer speed and good
performance, PCI adapters can access each other or system
memory at very high speed, thereby meet the requirements
for video operation and transmission.
The PCI interface function is fulfilled by the target
device PCI 9030 (Fig. 4). It works as a bridge, connects
the local bus devices of the PCI card to PCI bus, translates
the operation command, such as read and write register,
memory, YO, to local bus.
5. SYSTEM ARCHITECTURE AND WORKING
PRINCIF' LE
FPGA ePC19030
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sampling pulse, after clamping, amplifying, filtering and
AID transforming, the front end transform the image
information to digital signal, and then sends it to FPGA.
The image operation is implemented in FPGA. Under the
control of writing signal, the image data is delivered to the
memory through flip-latch. As soon as the memory is
filled with image data, the interrupt circuit sends interrupt
signal to PC through PCI port, applying for interrupting
operation. The PC interrupt operation program reads the
data to PC memory. In this way, each time the image
memory'is filled by the acquiring circuit, the interrupt
program reads the data out, and sends to PC memory.
Finally, the entire image is acquired. When the sampling
frequency is high enough, the system can implement
real-time acquiring, processing and display.
6.EXPERIMENTRESULTS
The following images (Fig. 6) are acquired via CCD in our
lab. The high quality of these images demonstrates that the
acquiring part of the system is cable of obtain high
resolution images. In the next step, we should focus our
efforts on implementing the whole system.
been involved in the research work.

8. REFERENCES

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[4] PLX Technology, Inc., PCI 9030 Dafabook VI.l, PLX

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[5] Luo Huiming, The Basis of Television Technologv,

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[6] John M. Yarbrough, Digifal Logic Applicafions and

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[8] Kenneth R. Castleman, Digiral Image Processing,

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[lo] Gu Haitao, “Research On Digital X-ray Image

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