Heterogeneous Computing To Enable The Highest Level of Safety in Automotive Systems - v1.2

Heterogeneous computing
to enable highest level of safety

Ramanujan Venkatadri
Automotive Innovation Center, Infineon Technologies
1
Table of contents
1 Challenges to address next generation automotive systems 3
2 Exponential increase in workload specific compute 5
3 How to secure the future connected vehicle? 7
4 How to achieve higher levels of autonomy? 9
5 How to address the new EE architecture challenges 11
6 Introduction to next generation AURIX TC4xx microcontrollers 13
7 Example application use case 29
8 Summary 31
08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 2

Table of contents
8 Summary 31

Challenges with developing autonomous, electric and connected
Vehicle
Connected, Autonomous
Electric Mobility
E/E architecture
evolution
High availability beyond

critical operations
Connectivity to “world"
needs high security
Higher workload
Evolving technologies specific compute
(ex: Battery, Sensing,
and AI)
Table of contents
8 Summary 31

Increase in demand for workload specific compute
1 2 3
Artificial Intelligence & sensor Faster security accelerators for Higher connectivity interfaces with
specific workload accelerators authenticity & Integrity low latency data processing
Machine learning Sensor processing Security Faster data processing

Table of contents
8 Summary 31

The connected mobility : How to secure the future vehicle?
Every connection in the car is a potential entry point for an attacker…
V2X-DSRC Radar
Keyless entry Tire pressure
monitoring system
Cellular
USB
Infotainment On-board
diagnosis
EV charging Wireless
charging
Bluetooth Wi-Fi

Table of contents
8 Summary 31

Autonomous vehicle : How to develop highly dependable systems?
High Availability | Ensure high availability beyond critical operations;

a safe and secure system, that operates in all conditions
Fail-Operational | Mitigate potentially hazardous

effects by ensuring critical operations in the event of a failure
Fail-Safe | in the event of a

failure, system enters safe state
Automation
Lower levels (ADAS, <L2) Higher levels (AD, ≥L2+) Higher levels (AD, ≥L3+)
System enters safe mode

Failure
System continues safety High availability in all conditions

critical tasks
System
Reliable, robust, safe, secure Fail safe + available Fail operational + highly available

Table of contents
8 Summary 31

E/E architecture : How to support next generation E/E architectures?
Future architecture: Domain, Zone,
Today’s architecture: Flat or combination
Gateway Central Computer
ECU with ECU with

Domain functionality Domain functionality Ethernet
Backbone
Func 1
Domain or Zone Controller
Ethernet and
Classical Bus
Func n
Sensors & Actuators
Sensors & Actuators

Table of contents
8 Summary 31

Infineon AURIX™ - the most dependable microcontroller platform
TriCore™ … integration of instructions from three worlds:
RISC, DSP and Real-time AURIX™
TC4xx.
AURIX™
TC3xx TC 1.8
Multicore
AURIX™ 500MHz
TC2xx TC1.6.2P +Hypervisor Support
Performance Increase
Multicore + 8-stages
AUDO 300MHz
MAX TC1.6.1P + Double precision floating point
Multicore +Improved Memory Hierarchy
AUDO 300MHz
Future TC1.6
+Multicore
AUDO 300MHz
+ Sync. inst
Next Gen. TC1.3.1
180MHz +Integer divide
+Code density for Byte&Half-Word AURIX™ and TriCore™ means
AUDO TC1.3
+Cache index › Protection of your software investment
150MHz
+FPU C convert inst. › Continuous performance increase
TC1.2 +FPU › Continues memory upgrade
40MHz
› High Scalability
RISC+DSP+Real-time
2001 2006 2009 2012 2015 2019 2023 SoP Timeline
14
Key improvements with AURIX™ TC4xx
15
AURIX™ TC4x defines the next controller standard for safe & secure
ECUs with strong networking capabilities
1 2 3 4
Higher Performance Safety and Security Freedom From Interference Rich connectivity
› New 500MHz TriCore™ 1.8 › AURIX™ meets ISO26262-2018 › Hardware isolation at core and › Up to 2x 5GBit Ethernet incl.
ASIL D safety standard peripheral level Bridge
› PPU: Private scalar core +
› › › Accelerated MACsec support
512bit wide vector unit with CSRM: high-performance TriCore™ 1.8 with up to eight
security module with private VMs per core and Hypervisor by HW accelerator in CSS and
up to 72 GOPS application SW driver
CPU, memories and crypto
› SPU3: High-performance accelerators › Ultra-fast context switching › 4x10/100MBit Ethernet
radar processing sub- supporting 10Base-T1S
system › CSS: Distributed crypto and › Enhanced memory protection standard
hash engines for secure for cores and virtual machines
› A/D Converter sub-system CAN/Ethernet communication › Up to 2x 8GBit/s PCIe 3.0 1x
lane
with integrated DSPs › Fine-granular access
› Security according to ISO 21434 protection to peripherals › Up to 20x CAN-FD
› Data Routing Engine for CAN – standard planned
Ethernet - Mem communication
› Isolated DMA protection

AURIX™ TC4x Architecture
Enhancements compared to AURIX™ TC3x
CSRM
Performance ASIL-D Radar Cluster
− 4x Performance New high performance Security Modules
Enhanced TriCore™ Radar Cluster
− 800MSamples/s with ASIL-B support
With up to 6CPUs @
500MHz − Radar DMA CSI-2 RIF
R
Flash A Flash B − CSI-2 Interface A
CSS
2MB 2MB
SPU M Dedicated communication security
3.0 satellites
Bigger Tightly Coupled Core + Checker Core
SRAM for increased TC 1.8P

local PF
PPU
performance CPU0
CSRM New Programmable HW Accelerator -
FPU Scalar Core
PSPR TC18 PPU
PCACHE Vector DSP
DSPR
DCACHE
Distr.
local SRAM
SIMD Vector DSP + Scalar Core for
Full AB-Swap Support STU (DMA) CSM
dLMU LMU
Modelling and Precise Control – ASIL D
System Resource Interconnect

without bridges
New high-speed comm Interfaces:
Debug and Trace
• PCIe 3.0
ETH MAC
Lockstep
PCIe 3.0
Debug-
eMMC
Bridge
Bridge
HSSL
Trace
Safe and the secure in field
DMA
DRE
xSPI
CSS
SFI
SFI
SBGT
• 100Mb- 5 Gbps Ethernet
xSPI New 10 Mbit Ethernet
External Memory Interface New communication routing
System Peripheral Bus CPB accelerator:
• DRE- Data Routing Engine
ADC ADC
Stdbv Ctrl
HRPWM
ASC LIN
CANFD
GPT12
eGTM
PSI5S
ERAY
SENT
Dedicated DSPs
TM-SAR
DS-ADC
GPIO
QSPI
GTM
MSC
PSI5
STM
SCU
I2C
CDSP
New eGTM timers and High Resolution
FC
Enhanced ADCs PWM with low latency interconnect
(LLI)
LLI

1
Workload specific compute – Machine Learning
18
Parallel Processing Unit (PPU): Scalable SIMD Vector DSP
Inter Processor Tools for high level application development

Communication
(IPC) Software PPU High/Mid/Entry C/C++ w/ vector
extensions
Framework Open CL
32b 128b - 512b Auto code
Scalar Vector DSP generation
TriCore including library
TriCore Compiler
TriCore
1.8 I$ D$ Vector Memory (32KB-128KB)
1.8
1.8
Cluster Streaming Transfer Cluster Shared Memory
Components Unit (STU) (CSM) – 64KB-256KB MLI xNN
library SDK
› Scalable PPU EV71FS in TC4x portfolio › Neural network based algorithms

› SIMD vector DSP co-processor › High speed control implementation
› Matrix operation acceleration & data processing

Inter processor communication between Tricore™ and PPU
TriCore™ 1 TriCore™ 2 PPU › PPU compute resource will be shared

Function a Function a
between multiple host CPUs
Function c › Outsourcing of functions into PPU
Function b Function c
Function c
enables speed up of applications tasks
Function c Interrupt
Function b
Function d
Function c › Middleware is integrated into basic
Switch to
previous
software using complex device driver
Function a
› Single level of interruption (priority
task
Function d scheme) is considered

Function b Function c Function c
Function a Function d
IPC enabling TriCore™ to PPU communication

Example: PPU middleware communication with AUTOSAR stack on
Tricore™
Example: AUTOSAR
Environment
TriCore™ TriCore™
› Three physically isolated
Hypervisor AUTOSAR stacks
SWC - EPS SWC - VD SWC – MC › Each communicates with PPU
RTE RTE RTE using dedicated complex
device driver (CDD)
BSW CDD BSW CDD BSW CDD
› CDD communicates with
SW mailbox SW mailbox SW mailbox
middleware on PPU
Shared memory
PPU middleware detects
Runtime requests and executes
FFT Kalman filter MLP
› Software on PPU does not
PPU differentiate its clients

2
Security: Hardware acceleration and secure

connection to the internet world
22
Security cluster of AURIX™ TC4x increases throughput by parallel
computation and supports upcoming new security standards
New AURIX™ TC4x security cluster Cyber security satellite (CSS) for parallel computation
› Parallelization of HW accelerators in service provider to application

area to avoid performance bottlenecks by
› Increasing throughput
TriCoreTM PFlash
› Minimizing latency
› 21 individual channels to be used by application (compared to one
SRI channel in TC3x)
TriCoreTM
› Providing freedom of interference for domain / zone controllers
CSS
LS
Bridge Bridge
Cyber security real-time module (CSRM) for performance increase
›
SRI interconnect
Upgrade to TriCore™ 1.8
Public
› providing ~5-15x more performance vs. TC3x HSM
TriCoreTM
LS
DMA DFlash 1 TRNG Key
Crypto › CSRM as trusted secure HW environment supporting new security
standards (e.g. ISO 21434)
Application area CSRM
› Private Program Flash within CSRM which supports individual security
SW updates independent of application core
› Enables realization of multiple security use cases for wide ranging
applications
Security use cases require significantly enhanced performance
Security use cases covered by AURIX™ TC4x Why is the new security cluster needed?
Enabled by SW on CSRM and HW on CSS/PKC/TRNG

Minimize latency & maximize throughput as an
› Secure boot › Flight Recorder / Secure Odometer
increasing number of security use cases are expected
› Debugger protection › Feature Activation for the future
› Immobilizer › Remote Diagnosis Car Access
› Tuning protection (OBD)
› Secure Update › Plug & Charge – OBC (ISO 15118)
› Secure (key-) storage › Device Attestation
› Supporting new Security standards
› Component protection Connection to external Service
Provider (e.g. ISO 21434)
› Key management
In-vehicle network (IVN) & V2x (e.g. vehicle to cloud) security

Enable SOTA use cases, which require secure and
› E/E COM (message) observation:
safe distribution of SW updates from cloud or within
› Intrusion Detection System (IDS)
IVN
› E/E COM (message) filtering:
› Intrusion Detection Prevention System (IDPS)
› Firewall: Feasible by HW filters in MAC and SW
› COM Message Security (e.g. CAN(FD)/Ethernet): Serve AEAD and AAD solutions, which are expected
› Authenticated Encryption with Associated Data (AEAD); Authentication to gain importance in the future: authentication of
with Associated Data (AAD) >50% and encryption of >15-20% of all IVN messages
› Combined modes are supported in CSS

Security : Significant performance improvement for AURIX™ TC4xx
Secure Boot*
AURIX™TC2x/TC3x AURIX™ TC4x 20x faster
69 MBytes/s Up to 1368 MB/s
Secure Boot1 8 MB ~ 120ms 24 MB ~ 18ms
1
Faster and less complex startup
CMAC AES-128
SecOC* 50x faster

AURIX™TC2x/TC3x AURIX™ TC4x
~30 µs 0.60µs
SecOC2
AURIXTM TC2x/TC3x performance at limit of current project’s need
AURIXTM TC4x minimize latency & maximize throughput for future apps
2 CMAC verify on 16 bytes

3
Freedom from interference : Safe hardware

isolation
26
Hardware Isolation to separate ASIL and non ASIL applications
Consolidation of features
Need for
Isolation › Reduce number of ECUs
› Enhance computing power
› Combine multiple applications with Introducing Virtual
different OS on one MCU Machines (VM)
Example: Zone › Isolation containers
controller Separation of applications › Isolates application
› Upto 6 per vehicle execution & control path
› Safety: cannot mix safe & unsafe SW
› Cross-domain › One ECU could need
functions in a › Security
upto 30
single ECU › Liability: keep SW from partners separate
› Need to be safe, secure
& easy to use
Flexibility
› Enable collaboration from multiple partners

› Separate startup/ shutdown of application
› Independent updates to fix/ upgrade: i.e. OTA
› Monetization: Activate or deactivate features

Virtual ECUs deployment using Hypervisor
ISOLATION from APU ISOLATION from APU
AURIX™ TC4xx TriCore
Application A Application B Third Advanced isolation features at
(Virtual (Virtual Party CPU level
Machine 1) Machine 2) App
... Access Protection Unit
(APU)
Provides isolation features at the
Hypervisor Inter virtual machine communication peripherals
SW (shared memory + interrupt)
Virtual Machines
AURIX™ Core 0 Core 1… Core X ...
TC4xx With complete AUTOSAR stack
& assignment of own peripherals
Sensors Comm I/F Sensors Comm I/F Comm I/F

Actuators Actuators
E/E Network
4
Rich connectivity and low latency data

routing
29
Feature set deep dive: Rich connectivity
TC4xx meets the latency and ethernet performance challenges
TC4xx DRE/CRE routing accelerators:

› Reduces SW processing load of data
Challenge: transmission
Latency when sharing real › Increase performance and throughput
time data i.e. wheel sensor › by reducing routing latency and jitter
between zone controllers › Use-cases covered:
– Packet forwarding CAN→CAN
– Packet formatting and encapsulation CAN→ETH
– Packet storage CAN→Memory
Reduces
Challenge:
TC4xx Ethernet MACs and Ethernet bridge: communication load
Ethernet bridge
› High-speed Ethernet with TSN support on CPUs and enables
performance & redundancy
› Combo MAC with 100Mbps and safety critical real
for safety critical application
10BaseT1s support time communication
in daisy chain & ring
› Ethernet bridge with filter and parser
topologies
capabilities

Comprehensive ethernet and CAN connectivity and feature set
to address wide variety of future IVN demands
2 x 5 Gbps MAC CSS - Security Accelerator
Supported speeds: TriCore™
Supports security algorithms for
CSS
› 100Mbps (MII,RMII, RGMII) LS
› MACsec
› 1Gbps(RGMII, SGMII) › IPsec
› 2.5Gbps (SGMII) › D/TLS
› 5Gbps (SGMII) › SecOC (PDU level)
4 x 10/100 Mbps MAC 10M/100M Bridge

Bridge Routing accelerator
20 x CAN-FD nodes and routing engine
Supported speeds:
› CAN-to-CAN frame routing across all 20
› 100Mbps (MII, RMII) CAN channels
› 10Mbps (3 Pin Transceiver) >1G >1G 10M 10M 10M 10M CAN CAN CAN CAN
› CAN-to-Memory frame routing
MAC MAC MAC MAC MAC MAC FD FD FD FD
Supported topologies: › CAN-to-Ethernet routing (IEEE:1722
› point-to-point (100M) support)
› Bus (10M) › Multi-cast up to 4 destinations
› Intrusion Detection support
› Quality of service: provides queues for frames › Virtualization support
› Classification: applies rules to inbound packets
Ethernet
› TSN: provides functions to achieve real time behavior
MAC
› Intrusion detection: supports detection of anomalies
Features
› Bridge: support fast forwarding of frames

Software Ecosystem
32
Getting started with new SDKs and re-using proven ecosystem
Last generation re-use plus Enabling development with new IP

support of new computing IP plus increased safety support
› TriCore™ compiler: › PPU libraries and auto code generation:
› TASKING, Hightec, WindRiver, › Synopsys, TASKING
GHS › AURIX TC4x hardware support package
Compiler Software
› PPU compiler: › MATLAB / Simulink
› Synopsys, TASKING, Hightec and development › Safety software package (in discussion)
› Debugger and test tools: debugger kits › Startup tests and failure checks recommended
› iSYSTEM, Lauterbach, PLS, in safety manual
Synopsys › Optional CDSP software toolchain
› Synopsys
Enablement of pre- Increased MCAL offering and

silicon development AUTOSAR providers incl. hypervisor
Virtual MCAL and › Proprietary MCAL with ISO26262:2018 compliance
› Provider: Synopsys
prototype AUTOSAR for IPs incl. new COM Ips (PCIe, DRE, 10BaseT1s)
› Modelling of key AURIX TC4x
HW features › Hypervisor implementation
› EB, ETAS, Opensynergy, SysGo, Greenhills
› Full debug and analysis support
› SW stack integration providers:
› Interfaces to Simulink, SABER, › Vector, Elektrobit, Siemens, ETAS
CANoe, etc.
› Security SW: Vector, ESCRYPT, ISS, EB
Table of contents
8 Summary 31

Example ADAS use case : Autonomous L1/L2 Sensor Fusion
Sensors
Actuate
Camera Radar
Actuation
Object Data Cmd
GPS
Sensor Fusion + Motion Planning +
Ultrasonic
Multiple Object Collision Vehicle Control
Tracking Avoidance
Other Vehicle Sensors

(ex: Position, Angle, Pressure)
Data rates from

1Gbps to 2.5Gbps Deterministic
Extended Kalman filtering or Grid processing for free space Model Predictive Secure
RNNs are used for tracking estimation (Thresholding) and Control for Vehicle Communication
and Joint probabilistic data Polynomial solver for Control
association for object trajectory validation
High speed association
CAN/Flexray
Ethernet, Data
or Low speed
routing Engine and
Tricore Ethernet
security accelerator Tricore™ or PPU PPU

Table of contents
8 Summary 31

AURIXTM TC4xx Heterogeneous SoC architecture
enabling highest level of safety for automotive applications
E/E architecture AURIXTM

evolution Microcontrollers
High availability
beyond critical CPU + accelerators
operations
Cyber Security Accelerator Security
Connectivity to “world" Faster data ASIL D:

needs high security Data Routing Engine processing
~8k DMIPS+
72GFlops
Sensor
Signal Processing Unit +
Performance
processing
ASIL-B:
Higher workload 1.2k DMIPS
Machine
specific compute Parallel Processing Unit learning
ASIL-D ASIL
TriCore™ CPU processing Performance

Summary : AURIX™ TC4xx enables heterogeneous computing with
industry leading functional safety concept
AURIX™ TC4xx offers tremendous computational power boost compared to

previous generation deploying new applications with complex computing needs
Optimized SoC with high speed connectivity, data routing engine, hypervisor
for isolation to enable next generation EE architectures
Scalable and flexible Parallel Processing Unit (PPU) enables affordable

artificial intelligence with its high performance SIMD architecture
Holistic functional safety concept with improved safety mechanisms, Security

cluster supporting security standards and with significantly enhanced performance
AURIX™ TC4xx offers a scalable platform from low end to high devices enabled
with rich software ecosystem to support the next generation of mobility

39

Heterogeneous Computing To Enable The Highest Level of Safety in Automotive Systems - v1.2

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Heterogeneous computing

to enable highest level of safety

1 Challenges to address next generation automotive systems 3

2 Exponential increase in workload specific compute 5

3 How to secure the future connected vehicle? 7

4 How to achieve higher levels of autonomy? 9

5 How to address the new EE architecture challenges 11

6 Introduction to next generation AURIX TC4xx microcontrollers 13

7 Example application use case 29

08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 2

1 Challenges to address next generation automotive systems 3

2 Exponential increase in workload specific compute 5

3 How to secure the future connected vehicle? 7

4 How to achieve higher levels of autonomy? 9

5 How to address the new EE architecture challenges 11

6 Introduction to next generation AURIX TC4xx microcontrollers 13

7 Example application use case 29

08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 3

High availability beyond

1 Challenges to address next generation automotive systems 3

2 Exponential increase in workload specific compute 5

3 How to secure the future connected vehicle? 7

4 How to achieve higher levels of autonomy? 9

5 How to address the new EE architecture challenges 11

6 Introduction to next generation AURIX TC4xx microcontrollers 13

7 Example application use case 29

08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 5

Machine learning Sensor processing Security Faster data processing

08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 6

1 Challenges to address next generation automotive systems 3

2 Exponential increase in workload specific compute 5

3 How to secure the future connected vehicle? 7

4 How to achieve higher levels of autonomy? 9

5 How to address the new EE architecture challenges 11

6 Introduction to next generation AURIX TC4xx microcontrollers 13

7 Example application use case 29

08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 7

Every connection in the car is a potential entry point for an attacker…

08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 8

1 Challenges to address next generation automotive systems 3

2 Exponential increase in workload specific compute 5

3 How to secure the future connected vehicle? 7

4 How to achieve higher levels of autonomy? 9

5 How to address the new EE architecture challenges 11

6 Introduction to next generation AURIX TC4xx microcontrollers 13

7 Example application use case 29

08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 9

High Availability | Ensure high availability beyond critical operations;

Fail-Operational | Mitigate potentially hazardous

Fail-Safe | in the event of a

System enters safe mode

System continues safety High availability in all conditions

08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 10

1 Challenges to address next generation automotive systems 3

2 Exponential increase in workload specific compute 5

3 How to secure the future connected vehicle? 7

4 How to achieve higher levels of autonomy? 9

5 How to address the new EE architecture challenges 11

6 Introduction to next generation AURIX TC4xx microcontrollers 13

7 Example application use case 29

08/23/2021 Copyright © Infineon Technologies AG 2021. All rights reserved. 11

Gateway Central Computer

ECU with ECU with