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R.M.D ENGINEERING COLLEGE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK
SUB CODE: EC8095 BRANCH: ECE

SUB NAME: VLSI DESIGN YEAR/SEM: III/VI

UNIT I

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INTRODUCTION TO MOS TRANSISTOR
PART A

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1. What is meant by body effect?

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2. What is the need for design rule?

3. What are the non-ideal I-V effects?

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4. Discuss any two layout design rules.

5. Compare CMOS and BiCMOS technology.

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6. Draw the DC Transfer characteristics of CMOS inverter.

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7. List the various issues in Technology CAD.

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8. Define the lambda layout rules.

9. Why tunnelling current is higher for NMOS transistors than PMOS transistor with silica gate?
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10. What is objective of layout rules?

11. Draw the IV Characteristics of MOS transistor.

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12. Brief the different operating regions of MOS system.

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13. Determine whether an NMOS transistor with a threshold voltage of 0.7V is operating in the
saturation region if VGS = 2V and VDS = 3V.

14. Write down the equation for describing the channel length modulation effect in NMOS transistors.

15. Draw the energy band diagrams of the components that make up the MOS system.

16. What is body effect coefficient?

17. Define drain punch through.

18. What are the advantages of twin tub process over n-well process?

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19. Define Channel length modulation.

20. Determine shift in threshold voltage for a substrate bias effect of Vsb = 2.5 V

From Vsb=0 volts (Assume Na=3 X 10^6/cm^3, tox=200A; eox=3.9x8.85x10^-14 F/cm.

21. Draw the transfer characteristics of an enhancement and depletion type NMOS transistor.

22. Write an expression to obtain threshold voltage of MOS transistor.

23. What are the modes of MOS transistor action?

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24. What is supermos transistor?

25. What is body effect?

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26. What are the effects due to increase in threshold voltage?

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27. Draw the small-signal equivalent model of a MOS transistor.

28. List different types of scaling.

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29. What do you mean by design margin?
30. Define transistor sizing problem.
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31. Define scaling. Mention the types of scaling.

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32. What is meant by design margin?

33. How do you define the term device modelling?
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34. Define the term scaling.

35. Draw the Schematic diagram of the tristate inverter?

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PART B

1. i) Derive drain current of MOS devices in different operating regions.(10)

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ii) Describe with neat diagram the well and channel formation in CMOS process. (6)
2. i) Describe on CMOS process enhancements.(8)
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ii) With the processing steps involved. Explain copper dual damascene interconnect.(8)
3. Discuss the CV Characteristics and DC transfer characteristics of the CMOS.(16)
4. Briefly discuss about the CMOS process enhancement and layout design rules.(16)
5. Explain the electrical properties of MOS transistor in detail.(16)
6. Derive an expression for Vin of a CMOS inverter to achieve the condition Vin = Vout,
What should be the relation for βn = βp.
7. Explain in detail about the ideal I-V characteristics and non ideal I-V characteristics
of a NMOS and PMOS devices.(16)

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8. i) Explain in detail about the body effect and its effect in NMOS and PMOS devices.(8)
ii) Derive the expression for DC transfer characteristics of CMOS inverter. (8)
9. i) Explain the different steps involved in n-well CMOS fabrication process with neat diagrams.
(10)
ii) Draw the CMOS inverter and discuss its DC characteristics. Write the conditions for
the different regions of operation. (6)
10. Explain the principle SOI technology with neat diagrams. Discuss its advantages and disadvantages.
11. Discuss in detail about a) Full-Custom Mask b) CMOS inverter Layout Design

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12. i)With a neat Diagram discuss in detail about DC transfer characteristics of CMOS.(8)
ii) Write a short note on a) Oxide related capacitance b) Junction Capacitance. (8)

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13. Explain the gate, source / drain formation and isolation steps of CMOS fabrication process with neat
diagrams.(16)

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14. Give a brief note on the different process techniques to enhance the performance of CMOS
transistors. (16)
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15. (i) Explain in detail with a neat diagram the fabrication process of the nMOS transistor. (8)
(ii) Discuss in detail with a neat layout, the design rules for a CMOS inverter. (8)
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16. (i) Discuss in detail with necessary equations the operation of MOSFET and its current- voltage
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characteristics. (11)
(ii) Explain briefly CMOS process enhancements. (5)
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17. Explain the various features of CMOS technology (16)

18. Explain the characteristics of bipolar transistors (16)
19. Explain with neat diagram the SOI process and mention its advantages. (16)
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20. i) How are the circuit elements implemented in IC’s? (8)

ii) Explain about CMOS interconnects with diagram. (8)
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21. Discuss the steps involved in IC fabrication process.(16)

22. i) Draw and explain the n-well process (10)
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ii) Explain the twin tub process with a neat diagram (6)
23. Discuss the origin of latch-up problems in CMOS circuits with necessary diagrams.
Explain the remedial measures (16)
24. i) Explain the working of an enhancement type NMOS transistor with a neat sketch.(8)
ii) Derive the MOS device equation various regions of operation. (8)
25. i) Draw and explain the small signal model of a MOS transistor(8)
ii) Explain the fabrication steps involved in SOI technology. (8)
26. Describe in detail about the different MOS models and explain about the small signal AV

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characteristics of MOS transistor.(16)

27. i) Explain in detail about the second order effect s in the MOS transistors.(6)
ii) Derive the basic design equation for a MOS transistor with the relationship between
threshold voltage and the body effect. (10)
28. i) Explain the working of a enhancement type NMOS transistor.(6)
ii) Draw small signal model of a MOS transistor, Derive expressions for output conductance and
transconductance in linear and saturation regions. (10)

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29. Draw the Schematic diagram of the tristate inverter?
30. i) derive the final expression and explain path logical effort, path electrical effort Path effort and

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path branching effort. (8)
31. Explain the following

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i) Device models and device characterizations. (8)
32. Derive an expression for the rise time, fall time and propagation delay of a CMOS inverter.(16)
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33. Explain detail about the scaling concept and reliability concept.

34. Describe in detail about the resistive and capacitive delay estimation of a CMOS Inverter circuit. (8)
35. Discuss the principle of constant field and lateral scaling. Write the effects of the above scaling
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methods on the device characteristics. (8)

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36. Explain in detail about

i. Channel length modulation. (6)
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ii. Constant field scaling. (5)

iii. Constant voltage scaling. (5)
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37. Discuss the principle of constant field scaling and also write its effect on device characteristics.(8)
38. Explain the different factor that affects the reliability of CMOS chip.(8)
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39. Explain the effect of temperature, supply voltage and process variation over behaviour of CMOS
systems. (16)
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40. i) What are the techniques used to size the transistor? Explain briefly.(8)
ii) Explain briefly the scaling and design margining of MOS transistor, (8)
UNIT II

COMBINATIONAL MOS LOGIC CIRCUITS

PART A

1. Give the expression for Elmore delay and state the various parameters associated with it.
2. Give the effect of supply voltage and temperature variations on the CMOS system performance.
3. What are the factors that cause static power dissipation in CMOS circuits?

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4. Write the expressions for the logical effort and parasitic delay of n input NOR gate.
5. Why does interconnect increase the circuit delay?
6. What is the influence of voltage scaling on power and delay?
7. Define rise time and fall time.
8. What are capacitances that contribute to the total load capacitance at output of a CMOS gate?
9. Write the importance of parasitic R, L and C calculation in the design of an IC
10. Write the expression for the estimation of capacitance and inductance
11. What is the effect of power dissipation in transistor design?

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12. What is diffusion capacitance?
13. What are the sources of dynamic power dissipation

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14. What is sheet resistance?
15. What is complementary Pass transistor logic? State its advantages over CVSL.
16. State any two criteria for low power logic design?
17. Implement a 2:1 Multiplexer using pass transistor. eri
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18. Design a 1-bit dynamic register using pass transistor.
19. List the various power losses in CMOS Circuits.Draw the circuit diagram of a CMOS bistable element
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and its time domain behaviour

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20. Write a note on CMOS transmission gate logic.

PART B
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1. Size the transistors of CMOS three input NAND gate for logic ratio of 3/1. (8)
2. Explain the following
1. Power dissipation in CMOS circuits. (8)
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2. The simulation of circuit interconnects.(8)

3. Explain the various ways to minimize the static and dynamic power dissipation.(16)
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4. Describe in detail about the transistor sizing for the performance in combinational networks. (8)
5. Explain the static and dynamic power dissipation in CMOS circuits with necessary diagrams and
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expressions.(8)
6. With necessary equations, explain in detail about :
i. Short current effect. (8)
ii. Narrow channel effect. (8)
7. Draw and explain switching characteristics of MOS transistor.(8)
8. Explain the estimation o total power dissipation of a CMOS circuit capacitance estimation with suitable
examples. (16)
9. Discuss in detail power dissipation and design margining in MOS circuits (16)

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10. Derive an expression for short circuit power dissipation of a CMOS inverter.(8)
11. Write short notes on capacitance estimation.(8)
12. Derive an expression for fall time of a CMOS inverter.(8)
13. Discuss in detail capacitances estimation of MOS transistor. (8)
14. Derive an expression for short circuit power dissipation of a CMOS inverter.(16)
15. Derive an expression for short circuit power dissipation of a CMOS inverter. (8)
16. i) Compare static and dynamic logic circuits with example.(8)
ii) Explain the dynamic and static power reduction in low power design of VLSI circuits.(8)

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17. i) Implement Y= (A+B)(C+D) using the standard CMOS logic. (8)
ii) Implement NAND gate using pseudo-nMOS logic. (8)

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18. Implement a 2-bit non-inverting dynamic shift register using pass transistor logic. (8)
19. Discuss the design techniques to reduce switching activity in a static and dynamic CMOS circuits (16)

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20. Design a transistor level schematic of the one bit full adder circuit and explain. (6)
21. Discuss in detail the characteristics of CMOS transmission gate.(10)
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22. Write the basic principles of low power logic design .(16)
23. Describe the basic principle of operation of dynamic CMOS, domino and NP domino
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24. logic with neat diagrams. (16)

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25. i) For a two input NAND gate derive an expression for the drain current. (8)
ii) Draw a CMOS NOR gate and its complementary operation with necessary equations. (4)
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26. Obtain a CMOS logic, design the Boolean function Z=A(D+E)+BC. (8)

UNIT III
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SEQUENTIAL CIRCUIT DESIGN

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PART A

1. Differentiate Latch and Flip-flop.

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2. What are synchronizers?

3. Enumerate the features of synchronizers.
4. State the reason for the speed advantage of CVSL family.
5. Mention the qualities of an ideal sequencing methods.
6. What are the advantages of using a Pseudo N-MOS Gate instead of a full CMOS Gate?
7. Compare CMOS Combinational logic gates with reference to the equivalent N-MOS
depletion load logic with reference to the area requirement.
8. Draw a pseudo NMOS inverter.

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9. What are the advantages of differential flip flops?

PART B
1. i) What are klass semi dynamic flip flop? Explain with their logic circuits.(8)
ii) Discuss on skew tolerant domino circuits. (8)
2. Explain the methodology of sequential circuits of Latches and Flip flops.(16)
3. Briefly discuss about the classification of circuit families and comparison of the circuit families.
(16)
4. i) Implement D flip flop using transmission gate. (8)

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5. Explain in detail about the pipeline concepts used in sequential circuits. (16)
6. i) Describe different methods of reducing static and dynamic power dissipation in

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CMOS circuits. (8)
ii) Explain domino and dual rail domino logic families with neat diagrams. (8)

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7. i) Draw and explain the operation of conventional CMOS, Pulsed and resettable latches.(8)
ii) Write a brief note on sequencing dynamic circuits. (8)
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8. i) Draw a circuit diagram of the CMOS SR Latch And Explain In Detail. (8)
ii) Along with the necessary input and output waveforms of the CMOS Negative
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Edge Triggered Master Slave D Flip Flop. (8)

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9. For a resistive load inverter circuit with VDD= 5V, Kn’= 20µ A /V2, VTO =0.8V ,
RL =200 kΩ and W/L=2.
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a. Calculate the critical voltages on the voltage transfer characteristics and

find the noise margins of the circuit. (6)
b. Explain the detail about pseudo-nMOS gates with neat circuit diagram. (10)
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10. Compare the sequencing in traditional domino and skew tolerant domino circuits
with neat diagrams .(18)
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11. Explain the problem of metastability with neat diagrams and expressions.(18)
UNIT IV
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DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

PART A

1. Distinguish between absolute skew & clock skew.

2. Single phase dynamic logic structures cannot be cascaded. Why?
3. Draw the logic diagram of simple 2 phase clock generator circuit.
4. Why is barrel shifter very useful in the designing of arithmetic circuits?
5. Define regularity. What is the regularity factor of a 4*4 barrel shifter?

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6. Draw the block of an adder element.

7. Implement the following Boolean expression using full static CMOS logic
a. Y = (A.B) + (D.B.C) + (D.A) + (A.C.B)
8. Write the principle of any one fast multiplier.
9. Why NOR structures are avoided in high speed circuits?
10. Realize 2 input XOR gate using CMOS devices.
11. Give the NAND-NAND implementation of Y=ABC +DEF.
12. Define clocked CMOS logic.

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13. Define domino logic.
14. What is a tally circuit?

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15. Implement XOR gate using CVSL logic.
16. What is clock Skew?
17. Realize OR/NOR logic functions using CVSL logic.
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18. What is the role of stick diagram and Layout in MOS circuit design process
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19. How does a demultiplexer differ from a decoder
20. What are the properties of static CMOS gate
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21. What is ratioed logic

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22. Draw a circuit diagram for a CMOS gate with 2 inputs A and B and an output Z,
a. where Z=1 if A=0 and B=1 and Z=0 otherwise
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23. Implement the function z = ab + cd using CMOS logic

24. What are data path circuits?
25. What is anti-fuse technique? Mention its significances.
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PART – B
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1. Describe precharge and evaluation operations associated with dynamic CMOS logic with neat
diagrams. (8)
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2. Explain the operation of a 3 input tally circuit designed with pass transistors. (8)

3. Compare the NMOS and CMOS implementation of 4*1 MUX with necessary diagrams.(8)

4. Draw the circuit diagram and stick diagram of a 4*4 barrel shifter and explain its operation. (16)

5. Discuss in detail about the circuit arrangement and stick diagram of a CMOS (Dynamic logic) 4*8*4
PLA. (16)

6. Explain the different XOR structures. (8)

7. Write a short note on dynamic CMOS design. (8)

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8. Draw the schematic and explain the operation of D-CMOS and C-CMOS two- input NAND gate and
NOR gate. (16)

9. Explain the structure of a booth multiplier and list its advantages. (8)

10. Give the general arrangement of a 4-bit arithmetic processor and design a 4-bit adder unit for ALU
sub system. (16)

11. Design a 3 bit barrel shifter. (8)

12. What is 4*4 carry save multiplier .Calculate the critical path delay. (8)

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13. Explain the following circuits.1.Data path circuits 2.Any one adder circuit. (16)

14. Implement 1. a parallel adder 2. a transmission gate adder circuit. (8)

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15. Design a 4 bit barrel shifter using multiplexer. (8)

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16. Explain the design of a bit serial adder. (8)

17. Design a positive edge triggered T register with CMOS gates. Explain the circuit operation with
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timing diagram. (16)

18. Design a pass-transistor network that implements the sum function for an adder. (8)
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19. Draw the stick diagram of 3 input tally circuit designed with pass transistor. (8)
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20. Give the NAND-NAND implementation of Y = ABC + DEF. (8)

UNIT V
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IMPLEMENTATION STRATEGIES AND TESTING

PART – A
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1. Differentiate between the standard cell based ASICs and full custom ASIC.
2. Differentiate the devices PAL, PLA and FPGA.
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3. What is the advantage of λ based design rule

4. Draw block diagram of the PLA.
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5. How the standard cell is classified?

6. What is the impact of Moore’s Law on the Semiconductor Industry?
7. Give the different types of ASIC Design Methodology.
8. Give some of the important CAD tools.
9. Differentiate between channeled & channel less gate array.
10. Differentiate between FPGA and CPLD
11. What are the different methods of programming of PALs?
12. What are the different levels of design abstraction at physical design?

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13. What are macros?

14. What is Programmable Interconnects?
15. Compare Antifuse, SRAM, EPROM and EEPROM technologies with respect to erasing mechanism.
16. What is meant by CBIC?
17. How granularity of logic block influences the performance of an FPGA?
18. What is the difference between EEPROM and UVPROM technology?
19. What is meant by PREP benchmarks
20. What are several factors to improve propagation delay of standard cell?

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PART – B

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1. a). Explain the ASIC design flow and development flow, Give design of standard cell three input
NAND gate and respective layout diagram.

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b) Write about design methodologies and design tools used for ASIC’s design rules.
(a) Explain the internal structure of CPLD. How the output is considered to be the registered output?
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(b). Draw FPGA architecture and explain all parts of FPGA
3. (a). What is the function of LUT in FPGA? Implement the logic function: F = X1X2 + X’2X3 in an
FPGA.(10)
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(b). Write short notes on CAD tools for ASIC construction, power dissipation in ASIC, Xilinx IO
block in programmable ASIC.
4. (a). What is an ASIC? Explain different types of ASIC’s.
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(b). Discuss the different types of programming technology used in FPGA design
5. (a). Explain the ASIC design flow with a neat diagram and write the difference between custom IC
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and standard IC?

b) Explain in detail about PLA and PAL devices.
6. Explain the performance & characteristics for the following design styles.
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a) Standard cells.
b) Cell based ASIC.
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7. a). What are the various methodologies of FPGA? Explain the same with neat diagram?
b). Discuss the different types of I/O cells used in programmable ASIC’s
8. a). Why SRAM based FPGAs are popular when compared to other types? Explain?
b). What is an Antifuse, with diagram explain metal-metal Antifuse.
9. a). Differentiate between the standard cell based ASIC’s and gate array based ASIC.
b). what is PLA. With a diagram explain a 4 × 3 PLA with six product terms with the help of
diagram; explain the working of PAL devices with characteristics.

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10. a). Explain in detail the internal organization of ROM.

b). Explain in detail about EPROM and EEPROM technology.
11. a). Explain in details how an EPROM can be used to realize a sequential circuit.
b). Why SRAM based FPGAs are popular when compared to other types? Explain?
12. a). Discuss the different types of programming technology used in FPGA design
b). Discuss about multistage cell.

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