DOCUMENTATION

8-BIT RISC MICROCONTROLLER

CONTENTS

1.OVERVIEW

1.1 Motive Behind The Project

1.2 Document Organisation

2.WORK DONE

2.1 Units Designed

2.2 Hardware Implementation

3.TERMS AND ABBREVATIONS

4.FUTURE SCOPE

5.REFERENCES
1.OVERVIEW

1.1 Motive Behind The Project

The project aims at making a RISC(reduced instruction

set computer) microcontroller in VHDL.It assures the single cycle execution
of the instructions (except a few which require 2 or 3 cycles) and the number
of total instructions are also reduced to a count of 92.

1.2 Document Organization

The document is organized in such a way that it

specifies all the units that are designed along with the name and meaning of
the signals of each unit individually.
2. WORK DONE

2.1 UNITS DESIGNED

a)DATAPATH
1.Instruction Register
2.General Purpose Register File
3.Arithmetic and Logic Unit
4.Data Ram
6.Portb
7.Portc
8.Portd

b)CONTROLLING

1.Control Unit
2. Databuses :
a)For taking output from the units
b)For giving inputs to the units
2.2 HARDWARE IMPLEMENTATION

DATAPATH DESIGN

1.Instruction Register (IR)

It is taking instruction as the input and giving output as the address of the
registers of GPR file. At the same time it latches the next instruction
depending upon the control signal(enable)from the control unit

2.General Purpose Register file (GPR)

There are 16 general purpose registers getting there address from the IR.
To load these registers we have the instruction LDI which will be decoded
into the
control unit.

3.Arithmetic & Logic Unit (ALU)

Gets control signals from the control unit to perform various arithmetic and
logic operations.Result of operation may be stored into one of the GPRs
through the databus.

4.Data Ram
It gets address from one of the GPRs and reads or write to a paricular
GPR.It is a 128*8 RAM.

5.Portb,Portc,Portd
All the ports have 8 pins with each pin programmable.
CONTROL UNIT DESIGN

1. Control Unit

The control unit is a synchronous mealy machine with 8

states.The control unit gives control signals to all the other units.

2. Databus input control and Databus output control

There are two databuses taken into the design .One on which
outputs from all the units are going and the other from which inputs are
going to particular units.The two buses are linked through some control
logic.
INSTRUCTION INPUT CONTROL
(1a) (1c) LOGIC

(11)

(2a) (10)
INSTRUCTION GPR FILE
REGISTER
(7) (8) PORT
(4a) B

D
D
A
A
T
T
A
A
(2b) B
B
ALU U
U
S
(9) S PORT
I
CONTRO (6) O N
C
U
L T
UNIT

(1b) STATUS REGISTER

PORT
D
CONTROL SIGNALS
(4b) DATA RAM
(3)

(5)
 BLOCK DIAGRAM OF 8 – BIT RISC MICROCONTROLLER

Description of connections:

(1a) Instruction Input (16 bit wide) is coming into the INSTRUCTION
REGISTER(IR).IR latches the next instruction only if it is a single cycle
instruction else it holds the previous instruction.

(1b)Instruction Input is also going into the control unit

(1c)Instruction Input is also going into the GPR File unit

(2a) INSTRUCTION REGISTER decodes address of registers of the GPR

file.The instruction itself contains the address of the GPR file registers
Example : Instuction LDI is “1110 kkkk dddd kkkk”

Here dddd specifies address of the registers of GPR register file

Instruction register decodes this address and points to that particular register.

(2b)INSTRUCTION REGISTER gives input to the control unit and control

unit is getting one more instruction input from (1b).Control Unit generates
control signals depending on both these inputs.
Eg: if we give ADD instruction as input,IR will decode the address for GPR
File while control unit will decode the instruction and assert the ADD=’1’
signal.

ADD :”0000 1111 dddd rrrr”

Bits “00001111” signify that this is the instruction to add the contents of
registers so control unit decodes this signal and makes add=’1’;
(3)GPR File to DATARAM : Contents of register 14 of GPRFile point to
address of the RAM .

(4a)Data from dataram to one of the GPRs .Here GPR address is decoded
into GPRFile unit itself

(4b)Data from one of the GPRs to dataram.

(5)Red line indicates that data output from units is going onto the databusout

(6)Blue line indicates that input to the units is coming from this databusin.

(7 & 8)Contents of registers (pointed by IR) are coming into ALU for some
operation.

(9)Flags output from ALU goes into the status register to get status of the
result.

(10)ALU result output is going to be stored into one of the GPRs.

(11)Databusout value goes into databusin depending on control

logic.Control logic gets control signals from the unit which either acts as o/p
unit or acts as input unit.
3. TERMS AND ABBREVATIONS

Table 3.1 ABBREVATIONS

Abbrevation Full Form

GPR File General Purpose Register File

ALU Arithmetic & Logic Unit

MBR Memory Buffer Register

MAR Memory Address Register

Table 3.2 SIGNALS USED IN THE DESIGN

S.No Signal Name Function

1. Instruction11 This is the instruction input to the TOP LEVEL
ENTITY.
2. clk Clock input to all the entities
3. Rst Reset input to the TOP LEVEL ENTITY
4. Pinb,pinc,pindInout ports of the TOP LEVEL ENTITY
5. Instruction Instruction input to instruction register mapped
with instruction11
6. insfminsreg Instruction output from instuction register to
control unit
7. enable Given by control unit to instruction register to
latch the next instruction or not.This signal is high
if instruction gets executed in 1 cycle else it is low
for 2,3 cycles instruction
8. Databusalu O/P from ALU also acts as an input to the GPR
file
9. Databusoutram O/P from data ram to one of the GPRs
10. Ld_mbr I/P to DATA RAM from control unit to load the
mbr register of the ram with the value of
databusramin
11 Wr_reg From CONTROL UNIT to GPR to load the result
of ALU (databusalu ) to one of the destination
GPRs
12 Inc_zp Signal from CONTROL UNIT to GPR to
increment the contents of Z – pointer to point to
the next memory location as that was pointed by
Z pointer
13 Dec_zp Signal from CONTROL UNIT to GPR to
decrement the contents of Z-pointer to point to the
previous memory location as that was pointed by
Z pointer
14 databusgprin Input from ALU (databusalu)to GPR
15 Ramout_togpr To load the contents of DATARAM to one of the
GPRs
16 dest Signal from CONTROL UNIT to GPR telling
destination register of the result computed by
ALU(databusalu)
17 rr Signal generated by GPR indicating address of the
source register
18 rd Signal generated by GPR indicating address of the
destination register
19 Reg_rr Signal from GPR to ALU indicating value loaded
into the ALU register
20 Reg_rd Signal from GPR to ALU indicating value loaded
 into the ALU register
21 Databusramin Input to DATARAM from one of the GPRs
22 addrbus Output from GPR to DATARAM to where
contents of GPR(14) is used to point to address of
the RAM
23 imm Value from GPR to ALU giving immediate value
of the data to be operated.

24 C2a Signal from CONTROL UNIT to ALU to load

particular value into ALU register ora
25 C2b Signal from CONTROL UNIT to ALU to load
particular value into ALU register orb
26 Asel Signal from CONTROL UNIT to ALU to load
particular value into ALU register orb
27 bsel Signal from CONTROL UNIT to ALU to load
particular value into ALU register orb
28 Bitsel Signal from CONTROL UNIT to ALU for
instructions
BLD,BST,SBRC,SBRS,CBI,SBI,SBIC,SBIS
29 Set Signal from CONTROL UNIT to ALU
30 C_flag Signal from CONTROL UNIT to ALU
31 T_flag Signal from CONTROL UNIT to ALU
32 Add Signal from CONTROL UNIT to ALU to perform
addition operation
33 Subcp Signal from CONTROL UNIT to ALU to perform
subtraction operation
34 Logic Signal from CONTROL UNIT to ALU to perform
logical operations
35 Direct Signal from CONTROL UNIT to ALU for direct
loading directly into ALU register
36 Right Signal from CONTROL UNIT to ALU to perform
right shifting operation
37 Bld Signal from CONTROL UNIT to ALU to load the
bit in ORA pointed by bitsel with T-flag
38 Cbi Signal from CONTROL UNIT to ALU to clear a
particular bit in one of the I/O registers
39 sbi Signal from CONTROL UNIT to ALU to set a
particular bit in one of the I/O registers
40 Pass_a Signal from CONTROL UNIT to ALU for
 skipping
41 Cpse Signal from CONTROL UNIT to ALU for
skipping
42 skiptest Signal from CONTROL UNIT to ALU to test if a
particular condition is satisfied to perform
skipping of the next instruction or not
43 Skip Signal from ALU to CONTROL UNIT if Skip
instructions like SBRC or SBRS are met
44 Ioaddress1 Signal from CONTROL UNIT to ALU address
for instructions like CBI,SBI,SBIC,SBIS
45 Logicsel Signal from CONTROL UNIT to ALU to
perform a particular logical operation
46 Dirsel Signal from CONTROL UNIT to ALU to put the
result of ALU directly into ALU register orb and
so on…
47 wcarry Signal from CONTROL UNIT to ALU
48 Rightsel Signal from CONTROL UNIT to ALU for right
shift operation
49 flagstat Signal from ALU to STATUS REGISTER to
load value of the flags into the status register

50 Rd_ram Signal from CONTROL UNIT to DATARAM to

read the contents of ram into one of the GPRs
51 Wr_ram Signal from CONTROL UNIT to DATARAM to
write the contents of one of the GPRs into ram
52 Ld_mar Signal from CONTROL UNIT to DATARAM to
load the mar register of RAM with the contents of
GPR(14).
53 Databusoutram Output from DATARAM to one of the GPRs

54 Databussr Signal from databuscntlin unit to statusreg toload

the value of databusin to databussr
55 srenable Signal from CONTROL UNIT to STATUSREG
to give signal srenable to load the contents the
contents of flag register from ALU to the
STATUS REGISTER
56 srsel Signal from CONTROL UNIT to STATUSREG
to select particular bit of the status register
57 databusoutfmsr Signal from STATUS REGISTER to
 eg databuscntlout unit i.e. to DATABUSOUT
signal
58 Srreg1 Signal from stat reg to control unit giving value of
the status register
59 Rd_sreg Signal from CONTROL UNIT to STATUSREG
to read the contents of status register
60 Wr_sreg Signal from CONTROL UNIT to STATUSREG
to write the contents into the status registers

61 Ins2 Signal mapped to insfmreg i.e. O/P from

instruction register
62 Bclr Signal from CONTROL UNIT to STATUSREG
to clear the flag pointed by srsel

63 bset Signal from CONTROL UNIT to STATUSREG

to set the flag pointed by srsel
64 Clr_I Signal from CONTROL UNIT to STATUSREG
to clear flag(7) i.e. interrupt flag when a particular
interrupt is being served.
65 Set_i Signal from CONTROL UNIT to STATUSREG
to set flag(7) i.e. interrupt flag when a interrupt
serving is over.
66 Rd_portb Signal from CONTROL UNIT to PORT to read
the contents of portb
67 Wr_portb Signal from CONTROL UNIT to PORT to write
the portb
68 Rd_portc Signal from CONTROL UNIT to PORT to read
the contents of portc
69 Wr_portc Signal from CONTROL UNIT to PORT to write
the portc
70 Rd_portd Signal from CONTROL UNIT to PORT to read
the contents of portd
71 Wr_portd Signal from CONTROL UNIT to PORT to write
the contents to portd
72 Rd_pinb Signal from CONTROL UNIT to PORT to read
pinb
73 Rd_pinc Signal from CONTROL UNIT to PORT to read
pinc
74 Rd_pind Signal from CONTROL UNIT to PORT to read
 pind
75 Rd_ddrb Signal from CONTROL UNIT to PORT to read
ddrb
76 Wr_ddrb Signal from CONTROL UNIT to PORT to write
ddrb
77 Rd_ddrc Signal from CONTROL UNIT to PORT to read
ddrc
78 Wr_ddrc Signal from CONTROL UNIT to PORT to write
ddrc
79 Rd_ddrd Signal from CONTROL UNIT to PORT to read
ddrd
80 Wr_ddrd Signal from CONTROL UNIT to PORT to write
ddrd
81 Rd_port Signal from CONTROL UNIT to PORT to read
the contents of port
82 Wr_port Signal from CONTROL UNIT to PORT to write
to the port
83 Rd_ddr Signal from CONTROL UNIT to PORT to read
the contents of ddr
84 Wr_ddr Signal from CONTROL UNIT to PORT to write
to the ddr
85 Rd_pin Signal from CONTROL UNIT to PORT to read
the contents of pin
86 Databusportin Signal from databuscntl unit to PORT
87 Databus- Value from PORT to databusout depending on
-outport some control signal
88 databusout Signal declared into the TOP LEVEL ENTITY
mapped to outputs from all the units
89 Rd_io Signal from CONTROL UNIT to IOADDRESS
space decoder to read the contents of I O registers
90 Wr_io Signal from CONTROL UNIT to IOADDRESS
space decoder to write into the IO registers
4. FUTURE SCOPE

In future following units can be added to the design

1.Program Counter

Program counter can be added into the design if there is ROM into the
design so that program counter will hold address of next instruction to be
fetched or address where the control has to jump (in case of a call or
interrupt)

2.ROM

ROM can be added to the design by reserving some particular pins for
external connection of the ROM

3.Timer

Timer can be connected to the design which will also act as an interrupt by
generating timer interrupt request.

4.External Interrupt

External Interrupt shares pin 7 of the port so can be added in the design.

5.Instructions like MUL,DIV can be added to the instruction set of the

design.
5. REFERENCES

1. PDF reference manual for 8-bit RISC microcontroller

2. M.A. Mazidi for 8051 microcontroller

3. D.L. Perry for VHDL