EXPERIMENT - 2

Full adder using Logic Gates

AIM :
Design a Full adder using gates and verify the truth table

COMPONENTS REQUIRED :

1. IC 74LS08
2. IC 74LS32
3. IC 74LS86
4. logic trainer kit
5. Connecting Wires

THEORY:

Binary Adder

The operation of adding two binary numbers is one of the fundamental

tasks performed by a digital computer. The four basic addition operations
are 0 + 0 = 0, 1 + 0 = 1, 0 + 1 = 1 and 1 + 1 = 10. In the first three operations,
each binary addition gives sum as one bit , i.e. , either 0 or 1.
But the fourth addition operation gives a sum that consists of two
binary digits. In such result of the addition, lower significant bit is called as
the sum bit, whereas the higher significant bit is called as the carry bit. The
logic circuits which are designed to perform the addition of two binary
numbers are called as binary adder circuits. In this article we are going to
look at the binary addition performed by various adder circuits.

S KARUNAKAR REDDY, Associate Professor, ACE Engineering College Page 1

Half Adder

A logic circuit block used for adding two one bit numbers or simply two
bits is called as a half adder circuit. This circuit has two inputs which accept
the two bits and two outputs, with one producing sum output and other
produce carry output.
As we discussed above that binary addition is commonly performed by
Ex-OR gate, but for the first three rules , it performs the binary addition
and when the two inputs are logic 1, it does not develop any carry.
To accomplish the binary addition with Ex-OR gate, there is need of
additional circuitry to perform the carry operation. Hence, a half adder is
formed by connecting AND gate to the input terminals of the Ex-OR gate so
as to produce the carry as shown in below figure.

S KARUNAKAR REDDY, Associate Professor, ACE Engineering College Page 2

 In the above half adder , inputs are labeled as A and B. The sum
output is labeled with the summation symbol Σ and the carry output or carry
out is labeled with Co. Half adder is mainly used for addition of augend and
addend of first order binary numbers.

SUM = (A XOR B) = (A ⊕ B)

CARRY-OUT = A AND B ) = A.B

Half adder has limited number of applications, and practically not used
in the application especially multi-digit addition. In such applications carry of
the previous digit addition must be added along with two bits; hence it is
three bits addition.

Full Adder

A binary full adder is a multiple output combinational logic network

that performs the arithmetic sum of three input bits. As we have seen that
the half adder cannot respond to the three inputs and hence the full adder
is used to add three digits at a time.
It consists of three inputs, in which two are input variables represent
the two significant bits to be added, labeled as A and B, whereas the third
input terminal is the carry from the previous lower significant position and
labeled as Cin. The two outputs are a sum and a carry outputs which are
labeled as Σ and Cout respectively.

S KARUNAKAR REDDY, Associate Professor, ACE Engineering College Page 3

 Full adder can be formed by combining two half adders and an OR gate
as shown in above where output and carry-in of the first adder becomes the
input to the second half adder that produce the total sum output. The total
carry out is produced by ORing the two half adder carry outs as shown in
figure. The full adder block diagram and truth table is shown below.

SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin

CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)

S KARUNAKAR REDDY, Associate Professor, ACE Engineering College Page 4

PROCEDURE:

1. Place the IC on the Digital IC Trainer kit bread board as shown in the
figure without damaging the legs of IC.

2. Connect Vcc and GND Connections of the IC from the Digital IC Trainer
kit

3. Give connections as per the Circuit Diagram on the Digital IC Trainer

kit with the inputs and outputs required

4. Verify the truth table for all combinations of inputs.

S KARUNAKAR REDDY, Associate Professor, ACE Engineering College Page 5

 B A
CIRCUIT DIAGRAM:

0
Half Adder

1
U2:A U1:A
74HC86
7408

3
CARRY SUM

Full Adder

A
U1:B
0 4 U1:A
6 1
5 3
B 2
74HC86
0 74HC86
SUM
C
0 U2:A
1
3
2
U3:B
7408 4
6 U3:A
U2:B 5 1 CARRY
4 3
6 7432 2
5
7432
7408
U2:C
9
8
10

7408

S KARUNAKAR REDDY, Associate Professor, ACE Engineering College Page 6

 A
U1:B
0 4 U1:A
6 1 SUM
5 3
B 2
74HC86
0 74HC86
C
0
U2:C
9 U3:A
8 1 CARRY
U2:A 10 3
1 2
3 7408
2 7432

7408

RESULT:

Realized Half Adder and Full Adder using logic Gates

S KARUNAKAR REDDY, Associate Professor, ACE Engineering College Page 7