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Embedded deterministic test for low-cost manufacturing

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 Special ITC Section
Embedded
Deterministic Test for
Low-Cost Manufacturing
Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jerzy Tyszer
and Nagesh Tamarapalli Poznan University of Technology
Mentor Graphics
Jun Qian
Cisco Systems
Editor’s note:
You have probably heard that BIST takes too long and its fault coverage is
low, and that deterministic test requires too many patterns. This article
shows how on-chip compression and decompression techniques can
provide high fault coverage with low test times.
—Rob Aitken, Artisan Components
DFT BASED ON SCAN AND ATPG is a reliable and
widely accepted methodology that provides very high
fault coverage. The automated process of scan insertion
and test generation guarantees high predictability and
quality of results. Conventional ATPG systems generate
test sets that guarantee almost complete coverage of sev-
eral types of fault models. Typically, when ATPG targets a
fault, it determines the content of only a few scan cells and
fills the remaining positions with random values. Such a
fully specified pattern is more likely to detect additional
faults and can be stored on a tester. As a result of random
fill, however, the test patterns are grossly overspecified.
For large circuits, a growing volume of test data signif-
icantly increases test cost because of longer test time and
elevated tester memory requirements. For a scan-based
test, test data volume can be approximately expressed as
Test data volume ≈ scan cells × scan patterns
Assuming balanced scan chains, the relationship
between test time and test data volume is then
Test time ≈ (scan cells × scan patterns)/(scan
chains × frequency)
58 0740-7475/03/$17.00 © 2003 IEEE Copublished by the IEEE CS and the IEEE CASS
Consider an example circuit consist-
ing of 10 million gates and 16 scan
chains. Typically, the number of scan
cells is proportional to the design size.
Thus, assuming one scan cell per 20
gates, the total test time to apply 10,000
scan patterns at a 20-MHz scan shift fre-
quency will be roughly 312 million test cycles or equiv-
alently 15.6 seconds. As designs grow larger,
maintaining high test coverage becomes increasingly
expensive because the test equipment must store a pro-
hibitively large volume of test data and the test appli-
cation time increases. Moreover, a very high and
continually increasing logic-to-pin ratio creates a test
data transfer bottleneck at the chip pins. Accordingly,
the overall efficiency of any test scheme strongly
depends on the method employed to reduce the
amount of test data.1-4
Several methods for compressing test data exploit the
fact that test cubes frequently feature many unspecified
positions.5-7 Unfortunately, these techniques can incur
significant area overhead and cause inefficient tester
use. The so-called Illinois scan scheme, which divides
the scan chains into partitions and shifts in the same test
vector to each scan chain through a single scan input,
can reduce test application time and test data volume.8
This scheme’s performance strongly relies on the scan
chain configuration and therefore is not easily scalable.
Another scheme, using an on-product multiple-input
signature register (OPMISR), accomplishes a test data
reduction along with a twofold scan test time reduction.9
IEEE Design & Test of Computers
This scheme replaces the
test responses in conven-

Phase shifter
tional scan data with far
Scan
more compact signatures chain
and uses the tester’s repeat

Ring generator
capability to shift the same
values into the scan Design
core
chains for several consec-

Phase shifter
utive cycles to achieve
additional test data com-
pression. SmartBIST, a fur-
ther refinement of the
OPMISR architecture, uses Decompressor Compactor
tester channels to deliver
stimuli, and signatures are
observed only at the end
Compressed Compacted
of an unload cycle.10 The ATE
stimuli responses
test patterns, however, are
delivered in a compressed
form, and an on-chip Figure 1. Embedded deterministic test (EDT) architecture.
decoder expands them
into the actual data
loaded into scan chains. on the solid foundation of scan and ATPG and, at the
Since manufacturing test cost strongly depends on same time, fulfills all the requirements just outlined. (We
test data volume and test time, one of the key require- presented an earlier version of this article at the 2002
ments of a next-generation DFT methodology is to dra- IEEE International Test Conference.11)
matically reduce both factors. This new technology
should provide a way to achieve high quality testing EDT architecture
that generates and applies patterns cost effectively for Our EDT scheme consists of logic embedded on a
any fault model used today, as well as for any new fault chip and a new deterministic test pattern generation
models, and for defect-based testing. technique. As Figure 1 shows, the EDT logic, inserted
The staggering complexity of designs makes it cru- along the scan path outside the design core, consists of
cial to test an embedded complex block with many two main blocks: an on-chip decompressor and an on-
internal scan chains by accessing it through a simple, chip selective compactor.
narrow interface. A DFT solution should have minimal The design core requires no additional inserted logic
impact on present scan design flows and design styles. such as test points or X-bounding logic. Therefore, the
It should not require modification of the current scan EDT logic affects only scan channel inputs and outputs
and ATPG knowledge base and skill set or replacement and not functional paths. The EDT scheme’s primary
of existing test equipment. In other words, the user objective is to drastically reduce tester memory require-
should not have to make major changes as a precondi- ments, not to eliminate them altogether. Minimizing
tion for obtaining the test data volume and test time memory use reduces test time and increases tester
reduction benefits. Finally, the new methodology must throughput while maintaining test quality.
take long-term scalability into account. Thus, it must The ratio of internal scan chains to tester scan chan-
include compression technology that can deliver nels usually sets the maximum compression level. The
increasingly higher levels of compression and fit the design in Figure 1 has two scan channels and many
compressed test data into the current tester memory for short internal scan chains. From the tester’s viewpoint,
at least one decade, with no upgrades. however, the design appears to have two short scan
Here, we present an embedded deterministic test chains. In every clock cycle, the tester applies 2 bits to
(EDT) scheme that offers a high-quality test, ease of use, the decompressor inputs (1 bit on each input channel),
and broad applicability, with no design impact. It builds while the decompressor outputs load all internal scan

September–October 2003
59
 Special ITC Section

2,400 internal scan chains

11,292 76 with a maximum length of
scan cells scan cells
76 scan cells. In total, EDT
required 2,238 test patterns
to achieve the same fault

Decompressor

16 1,600
16
channels patterns,
channels
16 scan
chains
(a) (b)
Figure 2. Design example: ATPG (a) versus EDT (b).
chains. Compared with ATPG, this EDT design has the
same number of scan channels interfacing with the
tester but far more scan chains. Because the scan chains
are balanced, they are also much shorter.
EDT pattern generation is truly deterministic. For a
given testable fault, as with conventional ATPG, the EDT
scheme generates a pattern to satisfy the ATPG con-
straints and to avoid bus contention. The patterns gen-
erated and stored on the tester are the stimuli applied
to the decompressor and the responses observed on the
compactor outputs. The application of one pattern
involves sending a compressed stimulus from the ATE
to the decompressor. The continuous-flow decompres-
sor receives the data on its inputs every clock cycle, and
it produces the necessary values in the scan chains to
guarantee fault detection. The random fill is a decom-
pression side effect that occurs after the compressed
pattern goes through the decompressor.
As in conventional testing, the tester directly controls
and observes the functional I/O pins. In fact, to the tester
an EDT pattern looks exactly the same as an ATPG pat-
tern except that it is much shorter. The responses cap-
tured in the scan cells are compacted by the selective
compactor, shifted out, and compared with their golden
references on the tester. To ensure that there is no alias-
ing and that unknown states do not mask the fault
effects, the decompressor controls the compactor so
that only selected scan chains can stream their contents
to the compactor if necessary.
Figure 2 shows a real design that further illustrates EDT
compression. For ATPG (Figure 2a), we configured the
design into 16 scan chains with a maximum length of
11,292 scan cells. The test required 1,600 patterns. For
EDT (Figure 2b), we configured the same design into
Compactor
2,238 coverage as that of ATPG.
patterns,
The scan chain length
2,400
scan decreased almost 150
chains times. The effective reduc-
tion of scan test data vol-
ume and scan test time
was 101 times. The actual
compression is lower than
the target compression
because the maximum
number of specified bits is,
in some cases, greater than a decompressor’s encoding
capacity, and thus more test patterns are required.
Moreover, handling a large number of X sources affects
compression.
It is worth comparing how tester memory is used in
the two cases. One ATPG scan pattern occupies 11,292
locations of tester memory, whereas one EDT pattern
occupies 76 locations of the same memory. The mem-
ory required for one ATPG scan pattern can store 148
EDT patterns. Moreover, in the time required to apply
one ATPG pattern, almost 148 EDT patterns can be
applied. However, because EDT requires more patterns
than ATPG does to achieve the same fault coverage, the
total time to apply all EDT vectors is effectively 101 times
less than that of ATPG.
Decompressor structure
The decompressor plays a crucial role in determin-
ing the effectiveness of EDT test data compression, so it
must satisfy several requirements:
■ very low linear dependency in its outputs,
■ very high operation speed,
■ very low silicon area, and
■ high design modularity.
The EDT on-chip decompressor deploys a new and
original architecture called a ring generator, a distinct
form of linear finite-state machine. To perform on-chip
decompression, the ring generator operates in con-
junction with a segmented linear phase shifter. The
phase shifter is necessary to drive a large number of
scan chains and to reduce linear dependencies
between sequences entering the scan chains. In addi-

60 IEEE Design & Test of Computers

 15 14 + 13 12 11 10 + 9
16 17 + 18 19 + 20 21 + 22
Figure 3. Ring generator implementing polynomial x32 + x18 + x14 + x9 + 1.
tion, the phase shifter’s design guarantees balanced use
of all memory elements in the ring generator.
Ring generator. Figure 3 shows an example 32-bit ring
generator. We developed it by applying transformations
to the external-feedback LFSR featuring feedback poly-
nomial x32 + x18 + x14 + x9 + 1.12 The structure has three
main benefits over conventional linear-feedback shift
registers or cellular automata. First, the propagation
delay introduced by the feedback logic is significantly
less. In the worst case, in fact, only one two-input XOR
gate lies between any pair of memory elements.
Second, the maximum internal fan-out is limited to only
two devices fed by any stem in the ring generator.
Finally, the structure can drastically reduce the total
length of feedback lines.
The circuit in Figure 3, for instance, features only very
short connections that cause no frequency degradation.
Generally, a ring generator has fewer logic levels than a
corresponding external-feedback LFSR and a smaller
fan-out than the original internal-feedback LFSR. Hence,
it can operate at higher speeds than conventional solu-
tions, and it meets layout and timing requirements.
Injectors. The compressed test data go into the decom-
pressor through input channels connected to ring gen-
erator taps by additional XOR gates, called injectors,
placed between the memory elements. Each input
channel usually splits into several internal injectors pro-
viding the same test data to multiple memory elements
at the same time. For instance, four external channels
feed the ring generator in Figure 3, each having two
injectors. Their locations ensure that test data quickly
reaches all the ring generator memory elements.
Phase shifter. The linear phase shifter, added to the out-
puts of the ring generator memory elements in the form of
a segmented XOR network, allows the ring generator to
September–October 2003
8 7 6 + 5 4 3 2 + 1 0
+ 23 24 + 25 + 26 27 28 29 + 30 31
mutually displace the produced sequences in various
scan paths. The EDT phase shifter consists of XOR gates
with a few inputs (called XOR taps) to reduce propaga-
tion delays. We obtained all results presented in this arti-
cle assuming that the number of XOR taps equals three.
Decompression
The decompressor operates as follows. At the begin-
ning of every pattern, the ATE shifts the first group of
data, called initial variables, into the ring generator. Data
shifted out of the decompressor into the scan chains dur-
ing those clock cycles does not become part of the
decompressed test pattern. Subsequently, the ATE scans
the next group of variables for decompression. Loading
the scan chains occurs in parallel with continuous injec-
tions of new variables into the ring generator. The total
number of shift cycles equals the number of initial
cycles, in addition to the length of the longest scan
chain. Comprehensive experiments indicate that we can
maximize the probability of successful compression if
we choose the number of initial variables to equal 0.75D,
where D is the decompressor size (the number of mem-
ory elements comprising the ring generator).
Compression of test stimuli
The concept of continuous-flow decompression rests
on the fact that deterministic test vectors typically have
only 1% to 5% of their bits specified. In fact, the average
number of specified bits is often well below 1%. The
remaining bits are randomly filled with 0s and 1s. We
define test vectors with partially specified bit positions as
test cubes. Compressing test cubes significantly reduces
the volume of test data stored on the tester. The fewer the
specified bits, the better our ability to encode the infor-
mation into a compressed form. We exploit this ability by
having a few inputs drive the circuit, whereas the circuit’s
memory elements are configured into a relatively large
number of short scan chains. Consequently, a tester that
61
 Special ITC Section
while (not all faults targeted)
select fault and generate test cube
try to compress cube
if (compression failed)
declare fault as EDT aborted
continue with new fault
loop // dynamic compaction loop
select fault and generate incremental test cube
if (dynamic compaction failed)
if (attempts < limit) continue with new fault
else exit loop
try to compress cube incrementally
if (compression failed)
if (attempts < limit) continue with new fault
else exit loop
end loop // one compressed pattern generated
decompress compressed pattern
perform fault simulation // group of 32 or 64 patterns
end while
Figure 4. Compressed-pattern generation.
has a few scan channels and a small memory for storing
test data can still drive a fairly large circuit.
Linear-equation solver
We compress test cubes by treating the external test
data as Boolean variables. We conceptually fill all scan
cells with symbolic expressions that are linear functions
of input variables injected into the decompressor. Given
a feedback polynomial implemented by the ring gen-
erator, the associated phase shifter’s structure, the loca-
tion of injection sites, and the number of shift cycles, we
can obtain a set of linear equations corresponding to
scan cells with specified values. Subsequently, we deter-
mine a compressed pattern by solving the system of
equations in a manner similar to published techniques.5-
7,10
Therefore, here we will refer to the software com-
pressor as the solver.
To achieve a high degree of compression, the ATPG
algorithm works as follows. When the algorithm gen-
erates a test cube (without random fill), it invokes the
solver to generate the compressed pattern. If the com-
pressed pattern is scanned in through the decompres-
sor, all the bits specified by the ATPG algorithm should
match. Other unspecified bits are set to pseudo-
random values (based on the decompressor architec-
ture). When dynamic compaction is enabled, the
solver works iteratively with ATPG to maximize com-
pression. In this scenario, as long as the solver can
compress a test cube, the ATPG algorithm attempts to
pack more specified bits into that test by targeting sub-
sequent faults. Figure 4 shows the ATPG flow and its
interactions with the solver. As the figure shows, the
62
solver operates incrementally; that is, the algorithm
invokes it several times for a gradually increasing sys-
tem of linear equations.
An incremental solver offers two advantages. First, it
appends newly specified bits to previously processed
equations so that computations are not repeated for pre-
viously specified bits. This ensures that the solver’s com-
putational complexity remains significantly less than
that of ATPG. Second, it ensures that if dynamic com-
paction fails in the nth iteration, the specified bits in the
test cube up to iteration n – 1 will be satisfied when the
pattern is decompressed.
If the solver cannot compress a test generated for the
first fault, that fault is not retargeted. The solver can fail
to compress the test cube because the number of spec-
ified bits is large or because there is linear dependency
between the positions with specified values. However,
if the test cube for any subsequent fault in the dynamic
compaction flow cannot be compressed, that fault will
become a target again because its test cube might be
compressible with tests for other faults or when it is tar-
geted separately.
Selective compaction of test responses
Undoubtedly, MISRs are the most popular test
response compaction devices used in parallel scan
chain environments. However, they do not handle
unknown states, and they provide only limited support
for fault diagnosis, even if they are reset for every test
pattern. Therefore, we designed the EDT compaction
scheme in a distinct manner that does not compromise
test coverage. In particular, EDT handles X (unknown)
states propagating to scan cells, eliminates aliasing
effects completely, and supports diagnosis.
The scheme comprises multiple linear spatial com-
pactors driven by outputs of selected scan chains. The
spatial compactors reduce the outputs of multiple scan
chains into significantly fewer test data outputs, equal
to the number of scan channel inputs. As Figure 1
shows, the scan chains are partitioned into multiple
groups, and each group connects to a separate spatial
compactor feeding an output scan channel. Although
spatial compactors are essentially XOR trees, they are
not necessarily combinational circuits. If propagation
delay through the XOR tree becomes unacceptable with
respect to the shift frequency, pipelining the XOR tree
as in Figure 5 will allow faster operation.
Scan chain masking. A prominent feature of EDT
response compaction is its ability to selectively mask
IEEE Design & Test of Computers
scan chains to protect captured fault
effects. To mask test data stored in a scan Scan chain
chain before it is unloaded through the
spatial compactor, we add logic between Scan chain
the scan chain’s output and the com-
pactor. This logic can force one or more
scan chain outputs to 0 before they enter
Scan chain
the compactor. Consequently, faults can
be detected even when they are captured Scan chain
in positions (scan cells) for which at least
one corresponding counterpart exists in
another scan chain that captures an
unknown state (X). Indeed, the fault
Pattern mask
effect will remain visible because it is
added modulo 2 with the logic value of 0
instead of X. Figure 5. Test response compaction.
Aliasing. A similar technique handles
faults that would escape detection because of the phe-
nomenon known as aliasing. Aliasing occurs when fault
effects appear only on corresponding positions in an
even number of scan chains and are therefore added
modulo 2 in the spatial compactor at the same time.
Our technique completely eliminates aliasing effects by
masking test data in certain scan chains so that an odd
number of fault effects enter the compactor.
Selection logic. To facilitate masking of test data
captured in scan chains, we add gating circuitry to
every spatial compactor. This circuitry consists of
logic gates and decoders with select registers. These
components facilitate selective scan chain control in
which the required scan chain subset (connected to a
given spatial compactor) propagates its values to the
compactor’s output, while the remaining scan chains
are blocked.
As Figure 5 shows, the compaction process begins
by loading the pattern mask into the select register that
drives the selection logic. The pattern mask is part of the
corresponding test pattern and is loaded concurrently
with the internal scan chains. Pattern mask content is
compressed in the same manner that test cubes are
compressed. Thus, the spatial compactor control sig-
nals are treated as an integral part of the test data and
are loaded through the decompressor, as Figure 1
shows. The pattern mask data can also come directly
from the ATE during scan chain loading via the decom-
pressor. The scan chain masks decoded from the pat-
tern mask are static for each pattern and are applied
throughout the unloading of captured values.
September–October 2003
Decoder
Select register
Design flow
A factor allowing easy adoption of EDT technology
is its simple design flow, which closely adheres to the
conventional ATPG flow. At the start of EDT design, we
apply standard DFT rule checks to analyze the circuit’s
testability. We then generate the EDT logic (mainly the
decompressor and the compactor) for a netlist with
preinserted scan chains. At this stage, we can perform
preliminary test pattern generation to determine the test
coverage and scan volume compression. The EDT tech-
nology makes it possible to target any fault model han-
dled by conventional ATPG tools, such as stuck-at,
transition, path delay, or multiple-detect. For these fault
models, the technology generates a compressed test
pattern set that provides test coverage similar to that of
any deterministic method.
EDT logic synthesis
We can either place the EDT logic as a wrapper sur-
rounding the original design or instantiate it within the
design. In either case, it does not affect the functional
paths. In addition to the main components, the EDT
logic can include circuitry that facilitates the bypass
mode of operation. This bypass circuitry allows the user
to concatenate the internal scan chains into fewer and
longer scan chains directly accessible from the ATE. In
addition to diagnosis, the bypass mode supports con-
ventional ATPG and system debugging.
The inserted EDT logic requires some control pins to
drive the controller, as well as scan channel pins to
serve as the design’s new scan I/Os. The EDT control sig-
nals and the scan channel signals can share the pins
63
 Special ITC Section

shifter pseudoexhaustively.
Scan Scan
channel channel Shared Functional Functional
We also thoroughly test all
inputs outputs pins outputs inputs the compactor’s masking
modes, including the selec-
Output
Output tion logic and the spatial
sharing
sharing
compactors. We test the
EDT optional bypass logic, if
Scan chain in synthesized, in the EDT
Decompressor mode with a sequential
pattern, as we simulate the
Compactor Core
Scan chain out bypass mode of operation
for several clock cycles.
Bypass These additional test pat-
terns guarantee more than
99% stuck-at coverage for
all the EDT logic. Finally,
before test pattern sign-off,
Figure 6. EDT logic for a given core. we can verify the generat-
ed patterns with a timing-
based simulator.
with the functional logic so that the design requires no
additional pins for EDT. Figure 6 shows a complete Experimental results
block diagram of the EDT logic along with the original We tested the EDT scheme on many industrial
core. The output-sharing logic consists of multiplexers designs. Here we present results for nine representative
that facilitate pin sharing. designs, ranging in size from 543,000 gates to 10.9 mil-
The EDT logic’s architecture depends primarily on the lion gates. For all the designs, we performed conven-
number of internal scan chains and the number of exter- tional ATPG as well as EDT by fixing the number of scan
nal scan channels in the given design. Only logic that lies channels and using internal scan chains. All the designs
at the interface of the EDT hardware and the scan chains have up to several thousand sources of observable
depends on the clocking of the first and last scan cells in unknown states. They are also random-pattern resistant.
every scan chain. The EDT logic is therefore pattern inde- Hence, none of them, without substantial modification,
pendent and in most cases need not be regenerated if a would work with logic BIST or any other scheme that
design changes. Once the EDT components are instanti- uses a MISR for response compaction. The circuits rep-
ated, we can insert the boundary scan logic and I/O pads. resent different design styles and scan methodologies.
On the other hand, if a netlist contains preinserted I/O The experiments used every available software pattern
pad cells, we place the EDT logic between the I/O pad compression technique for both ATPG and EDT, includ-
cells and the original core. Subsequently, we synthesize ing dynamic and static compaction. Thus, we com-
the EDT logic at the gate level along with the boundary pared EDT with the best conventional ATPG
scan logic and I/O pad cells. technology. We also included the patterns that tested
the EDT logic in the EDT pattern set.
Pattern generation and EDT logic test Table 1 summarizes the results of the experiments. For
The next step is the generation of the final set of EDT each circuit, the table presents the following information:
test patterns. The final test pattern set also contains a few
scan patterns (typically around 20 for a 10-time compres- ■ number of gates;
sion) that test the EDT logic and the scan chains’ integrity. ■ number of scan cells;
In addition to guaranteeing very high test coverage of the ■ ATPG test coverage (percentage of testable faults
EDT logic, these patterns help in debugging simulation detected by a conventional ATPG tool);
mismatches. The tester thoroughly exercises and observes ■ test coverage after generating compressed scan pat-
the ring generator as it shifts all the patterns through the terns using the EDT scheme;
decompressor into the scan chains. We test the phase ■ effective compression (the ratio of scan data volume

64 IEEE Design & Test of Computers

 Table 1. Experimental results for nine circuit designs.

Parameter C1 C2 C3 C4 C5 C6 C7 C8 C9
Gates (millions) 0.543 0.576 1.2 1.2 1.5 2.1 2.6 3.8 10.9
Scan cells (thousands) 45 41 70 62 86 181 129 216 297
ATPG test coverage (%) 98.89 98.78 97.04 99.89 99.07 98.92 92.00 95.53 94.39
EDT coverage (%) 98.70 98.65 96.90 99.79 99.01 98.78 91.85 95.49 94.34
Compression factor 51 53 83 50 60 120 21 26 31
Channels/chains 16/1,600 16/1,600 16/1,600 16/1,600 8/1,600 12/2,400 2/157 2/146 1/104
Maximum specified bits 505 463 816 676 466 940 1,430 3,174 2,462
X state sources 139 61 376 259 1,943 556 14,483 2,611 33,432
Decompressor size (bits) 64 64 64 64 40 48 20 20 20

between the EDT and ATPG pattern sets, which also
represents the ratio of the number of scan cycles
between the two pattern sets and, therefore, the
reduction in test application time);
■ number of scan channels and number of internal
scan chains,
■ maximum number of specified bits;
■ number of sources of unknown states; and
■ on-chip decompressor size.
gates, conventional ATPG required 14.2 million test
cycles to obtain 99.2% stuck-at test coverage. For the
same circuit, EDT required 3.5 million test cycles to
obtain 99.2% test coverage for stuck-at faults and 93.6%
for transition faults and generated 1,500 path delay pat-
terns for testing critical paths. In other words, EDT
enabled the use of two additional fault models and still
provided a compression rate four times that of ATPG tar-
geted for stuck-at faults only.

In all cases, EDT achieved virtually the same test cov-

erage as that of ATPG. Several factors can contribute to
the minor differences in coverage: random-fill differ-
ences, reduction in fortuitous fault detection due to scan
chain masking in designs with many X state sources, or
faults whose test cubes cannot be compressed (this usu-
ally occurs only at very high compression levels). As
mentioned earlier, effective compression can deviate
from the target for high levels of compression. This typi-
cally occurs in designs with many observable X sources,
which can impact effective compression, even though
the EDT compaction technique can tolerate unknown
states. In designs with relatively few X sources, much
higher compression levels are possible. Another factor
affecting compression is obviously the number of bits
specified in the test cubes. A large number of ATPG con-
straints usually results in more specified bits and there-
fore lower compression levels.
As the table shows, EDT achieves remarkable com-
pression with test logic that requires only about 20 gates
per internal scan chain (including the bypass logic).
We performed further experiments to demonstrate
EDT’s effectiveness in addressing at-speed defects. The
EDT technology can handle embedded phase-locked
loops (PLLs) by using its legal clock sequences to gen-
erate at-speed patterns. For a circuit with 1.5 million
THE EDT SCHEME significantly reduces manufacturing
cost by dramatically reducing scan test data volume and
scan test time. It consistently achieves compression in
excess of one order of magnitude. EDT is widely applic-
able and easy to deploy because it is based on standard
scan-ATPG methodology and uses a simple flow. It is
nonintrusive because it does not require any modifica-
tions to the core logic, such as the insertion of test points
or X-bounding logic. It guarantees high test quality
because it works with all the traditional fault models.
The EDT scheme also fits into the core-based design
paradigm, in which only a few external pins can drive
a large number of internal scan chains in the cores. As
design size doubles every 18 months, the compression
ratio can be scaled accordingly; thus, all the scan data
will fit on existing testers for at least a decade.
Consequently, EDT is a suitable next-generation DFT
technology for low-cost, high-quality manufacturing test
targeting deep-submicron devices. ■
Acknowledgments
We thank Geir Eide, Andre Hertwig, Grzegorz
Mrugalski, Rob Thompson, and Kun-Han Tsai for their
valuable contributions, numerous discussions, and
constructive comments.

September–October 2003
65
 Special ITC Section
References
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The biography of Janusz Rajski appears on p. 25
of this issue.
66
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Jerzy Tyszer is a professor at the
Institute of Electronics and Telecom-
munications of the Poznan University
of Technology, Poznan, Poland. His
research interests include design
automation and testing of VLSI systems, DFT, BIST,
digital switching, and computer simulation of discrete-
event systems. Tyszer has a PhD in electrical engi-
neering from the Poznan University of Technology.
Mark Kassab is the engineering
manager for ATPG and EDT at Mentor
Graphics. His research interests
include test cost reduction, test quali-
ty improvement, and high-perfor-
mance test generation. Kassab has a PhD in electrical
engineering from McGill University, Montreal.
Nilanjan Mukherjee manages the
Test Synthesis Group at Mentor
Graphics. His research interests
include next-generation DFT tech-
niques for subnanometer designs, test
cost management, test logic synthesis, memory BIST
and repair, and fault diagnosis. Mukherjee has a PhD
from McGill University, Montreal.
Nagesh Tamarapalli is a technical
marketing engineer for DFT products
at Mentor Graphics. His research inter-
ests include all aspects of DFT, BIST,
and ATPG, including defect-based
testing and diagnosis. Tamarapalli has a PhD in elec-
trical engineering from McGill University, Montreal.
Jun Qian manages the ASIC Design
Implementation Group in Cisco’s Inter-
net Switching Business Unit. His tech-
nical interests include DFT, timing,
simulation, and other ASIC design
technologies. Qian has an MSEE from the University
of Iowa.
Direct questions and comments about this article to
Janusz Rajski, Mentor Graphics, 8005 SW Boeckman
Road, Wilsonville, OR 97070; janusz_rajski@mentor.com.
IEEE Design & Test of Computers