Middle Power Class-D Speaker Amplifiers

Analog Input / BTL Output

Class-D Speaker Amplifier
No.10075EBT05
BD5426EFS

●Description
BD5426EFS is a 10W + 10W stereo class-D power amplifier IC, developed for space-saving and low heat-generation
applications such as low-profile TV sets. The IC employs state-of-the-art Bipolar, CMOS, and DMOS (BCD) process
technology that eliminates turn-on resistance in the output power stage and internal loss due to line resistances up to an
ultimate level. With this technology, the IC has achieved high efficiency of 87% (9W + 9W output with 8Ω load). The IC, in
addition, employs a compact back-surface heat radiation type power package to achieve low power consumption and low
heat generation and eliminates necessity of installing an external radiator, up to a total output of 20W. This product satisfies
both needs for drastic downsizing, low-profile structures and powerful, high-quality playback of the sound system.

●Features
1) A high efficiency of 87% (9W + 9W output with 8Ω load), which is the highest grade in the industry and low heat-generation.
2) An output of 10W + 10W (13V, with 8Ω load) is allowed without an external heat radiator.
3) Driving a lowest rating load of 6Ω is allowed.
4) Pop noise upon turning power on/off and power interruption has been reduced.
5) High-quality audio muting is implemented by soft-switching technology.
6) An output power limiter function limits excessive output to speakers.
7) High-reliability design provided with built-in protection circuits against high temperatures, against VCC shorting and
GND shorting, against reduced-voltage, and against applying DC voltage to speaker.
8) A master/slave function allowing synchronization of multiple devices reduces beat noises.
9) Adjustment of internal PWM sampling clock frequencies (250kHz to 400kHz) allows easy protective measures
against unwanted radio emission to AM radio band.
10) A compact back-surface heat radiation type power package is employed.
HTSSOP-A44(5mm × 7.5mm × 1.0mm, pitch 0.8mm )

●Absolute maximum ratings

A circuit must be designed and evaluated not to exceed absolute maximum rating in any cases and even momentarily, to prevent
reduction in functional performances and thermal destruction of a semiconductor product and secure useful life and reliability.
The following values assume Ta =25℃. For latest values, refer to delivery specifications.
Parameter Symbol Ratings Unit Conditions
Pin 7, 8, 15, 16, 29, 30, 37, 38, 40
Supply voltage VCC +20 V
(Note 1, 2)
2.0 W (Note 3)
Power dissipation Pd
4.5 W (Note 4)

Input voltage for signal pin VIN -0.2 ~ +7.2 V Pin 1, 44 (Note 1)

Input voltage for control pin VCONT -0.2 ~ Vcc+0.2 V Pin 20, 24 (Note 1)

Input voltage for clock pin VOSC -0.2 ~ +7.2 V Pin 23 (Note 1)

Operating temperature range Topr -40 ~ +85 ℃

Storage temperature range Tstg -55 ~ +150 ℃

Maximum junction temperature Tjmax +150 ℃

(Note 1) A voltage that can be applied with reference to GND (pins 11, 12, 33, 34, and 43)
(Note 2) Pd and Tjmax=150℃ must not be exceeded.
(Note 3) 70mm × 70mm × 1.6mmFR4 One-sided glass epoxy board (Back copper foil 0%) installed.
If used under Ta=25℃ or higher, reduce 16mW for increase of every 1℃. The board is provided with thermal via.
(Note 4) 70mm × 70mm × 1.6mmFR4 Both-sided glass epoxy board (Back copper foil 100%) installed.
If used under Ta=25℃ or higher, reduce 36mW for increase of every 1℃. The board is provided with thermal via.

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BD5426EFS Technical Note

●Operating conditions
The following values assume Ta =25℃. Check for latest values in delivery specifications.
Parameter Symbol Ratings Unit Conditions

Supply voltage VCC +10 ~ +16.5 V Pin 7, 8, 15, 16, 29, 30, 37, 38, 40

Load resistance RL 6 ~ 16 Ω (Note 5)

(Note 5) Pd should not be exceeded.

●Electrical characteristics
Except otherwise specified Ta = 25℃, VCC = 12V, fIN = 1kHz, Rg = 0Ω, RL = 8Ω,MUTEX="H", MS="L"
For latest values, refer to delivery specifications.
Parameter Symbol Limits Unit Conditions

Whole circuit

Circuit current 1 (Sampling mode) ICC1 25 mA With no signal

Circuit current 2 (Muting mode) ICC2 10 mA MUTEX = “L”

Control circuit

“H” level input voltage VIH 2.3 ~ 12 V SDX, MUTEX, MS

“L” level input voltage VIL 0 ~ 0.8 V SDX, MUTEX, MS

Audio circuit

Voltage gain GV 28 dB PO = 1W

Maximum output power 1 (Note 6) PO1 9 W THD+N = 10%

Maximum output power 2 (Note 6) PO2 10 W Vcc = 13V, THD+N = 10%

Total harmonic distortion (Note 6) THD 0.1 % PO = 1W, BW=20Hz ~ 20kHz

Crosstalk CT 85 dB PO = 1W, Rg = 0Ω, BW = IHF-A

Output noise voltage
VNO 80 µVrms Rg = 0Ω, BW = IHF-A
(Sampling mode)
Residual noise voltage
VNOM 1 µVrms Rg = 0Ω, BW = IHF-A, MUTEX = “L”
(Muting mode)
Internal sampling clock frequency FOSC 250 kHz MS = “L” (In master operation)
(Note 6) The rated values of items above indicate average performances of the device, which largely depend on circuit layouts, components,
and power supplies. The reference values are those applicable to the device and components directly installed on a board specified by us.

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BD5426EFS Technical Note

●Electrical characteristic curves (Reference data)

(1)Under Stereo Operation (RL=8Ω)

100 100
Vcc=12V
Vcc=12V RL=8Ω
RL=8Ω Po=1W
10 BW=20～20kHz 10
BW=20～20kHz
THD+N (%)

THD+N (%)
6kHz
1 1

0.1 0.1
1kHz 100Hz

0.01
0.01
10 100 1000 10000 100000
0.001 0.01 0.1 1 10 100
OUTPUT POWER (W) FREQUENCY (Hz)

Fig. 1 THD+N － Output power Fig. 2 THD+N － Frequency

35 0
Vcc=12V
30
-20 RL=8Ω
Po=1W
VOLTAGE GAIN (dB)

25
CROSSTALK (dB)

Vcc=12V BW=20～20kHz
RL=8Ω -40
20
Po=1W
15 L=33µH
-60
C=0.47µF
10 Cｇ=0.1µF
-80
5

0 -100
10 100 1000 10000 100000 10 100 1000 10000 100000
FREQUENCY (Hz) FREQUENCY (Hz)

Fig. 3 Voltage gain - Frequency Fig. 4 Crosstalk - Frequency

0 20
Vcc=12V RL=8Ω
fin=1kHz THD=10%
OUTPUT POWER (W)

-20 RL=8Ω
CROSSTALK (dB)

fin=1kHz 15
BW=20～20kHz
-40
10
-60
5
-80

-100 0
0.001 0.01 0.1 1 10 100 8 10 12 14 16 18
OUTPUT POWER (W) VCC (V)

Fig. 5 Crosstalk - Output power Fig. 6 Output power - Power supply voltage

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BD5426EFS Technical Note

●Electrical characteristic curves (Reference data) – Continued

100 100
90 90
80 80

EFFICIENCY (%)
EFFICIENCY (%)

70 70
60 60
50 50
40 40
Vcc=12V
30 Vcc=10V 30 RL=8Ω
20 RL=8Ω 20 fin=1kHz
10 fin=1kHz
10
0 0
0 5 10 15 20 0 5 10 15 20
OUTPUT POWER (W/ch) OUTPUT POWER (W/ch)

Fig. 7 Efficiency - Output power Fig. 8 Efficiency - Output power

100 3
90 Vcc=16.5V
80
EFFICIENCY (%)

70 Vcc=12V
2
60 Vcc=10V
ICC (A)

50
40
30 Vcc=16.5V 1
20 RL=8Ω RL=8Ω
fin=1kHz fin=1kHz
10
0 0
0 5 10 15 20 0 5 10 15 20 25 30 35 40
OUTPUT POWER (W/ch) TOTAL OUTPUT POWER (W)

Fig. 9 Efficiency - Output power Fig. 10 Current consumption - Output power

100 0
90 RL=8Ω Vcc=12V
無信号時signal
Without -20
80 RL=8Ω
NOISE FFT (dBV)

70 -40 無信号時
Without signal
60 BW=20～20kHz
ICC (mA)

-60
50
40 -80
30 Sampling -100
20
Mute -120
10
0 -140
8 10 12 14 16 18 10 100 1000 10000 100000
VCC (V) FREQUENCY (Hz)

Fig. 11 Current consumption - Power supply voltage Fig. 12 FFT of Output Noise Voltage

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BD5426EFS Technical Note

●Electrical characteristic curves (Reference data) – Continued

MUTEX
Pin 20 Vcc=12V MUTEX 10V/div Vcc=12V
10V/div Pin 20
RL =8 Ω RL =8 Ω
Po=500mW Po=500mW
TM fin=500Hz TM 5V/div fin=500Hz
Pin 26 5V/div Pin 26

Speaker 2V/div 2V/div

Speaker
Output Output
10msec/div 10msec/div

Fig. 13 Wave form when Releasing Soft-mute Fig. 14 Wave form when Activating Soft-mute

VCCA VCCA
VHOLD 5V/div VHOLD 5V/div
Vcc=12V Vcc=12V
Pin 27 Pin 27
RL =8 Ω RL =8 Ω
Po=500m W Po=500m W
TM 5V/div TM
fin=3kHz 5V/div fin=3kHz
Pin 26 Pin 26

2V/div 2V/div
Speaker
Output Speaker
Output
20msec/div 2msec/div

Fig. 15 Wave form on Instantaneous Power Interruption Fig. 16 Wave form on Instantaneous Power Interruption
(20msec / div) (2msec / div)

5V/div Vcc=12V
Soft Clip
RL =8 Ω
Po=5W
THD+n=10%
fin=1kHz
Speaker
Output R2=91k Ω
R3=22k Ω
Soft Clip

200μsec/div

Fig. 17 Wave form on Output Power Limiter function

(Po = 5W)

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BD5426EFS Technical Note

●Electrical characteristic curves (Reference data) – Continued

(2)Under Stereo Operation(RL=6Ω)

25
RL=6Ω
fin=1kHz THD=10%
OUTPUT POWER (W)

20

15

10

0
8 10 12 14 16 18
VCC (V)

Fig. 18 Output power - Power supply voltage

100 100
90 90
80 80
EFFICIENCY (%)
EFFICIENCY (%)

70 70
60 60
50 50
40 40
Vcc=12V
30 Vcc=10V 30 RL=6Ω
20 RL=6Ω 20 fin=1kHz
10 fin=1kHz 10
0 0
0 5 10 15 20 25 0 5 10 15 20 25
OUTPUT POWER (W/ch) OUTPUT POWER (W/ch)

Fig. 19 Efficiency - Output power Fig. 20 Efficiency - Output power

100 4
90 Vcc=16.5V
80
3
EFFICIENCY (%)

70 Vcc=12V
60
ICC (A)

Vcc=10V
50 2
40
30 Vcc=16.5V
1
20 RL=6Ω RL=6Ω
fin=1kHz fin=1kHz
10
0 0
0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 45 50
OUTPUT POWER (W/ch) TOTAL OUTPUT POWER (W)

Fig. 21 Efficiency - Output power Fig. 22 Current consumption - Output power

Dotted lines of the graphs indicate continuous output power to be obtained on musical signal source or by installing
additional heat sinks.

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 IN1 1 44 IN2
1.0 MAX

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0.95 ± 0.2
0.85 ± 0.05
BD5426EFS

PLM T1 2 43 GNDA
GNDA
●Pin Assignment

0.08 ± 0.05 0.75 ± 0.1

PLM T2 3 Power FIL A 42 FIL A

0.85
PLM T3 4 L imit PW M 1 PW M 2 FIL P 41 FIL P

44

1
V CCA
PLM T4 5 40 V CCA

BSP1P 6 39 BSP2P

© 2010 ROHM Co., Ltd. All rights reserved.

●Outer Dimensions and Inscriptions

0.8
V CCP1P 7 38 V CCP2P

V CCP1P 8 37 V CCP2P

1PIN MARK
OU T1P 9 36 OUT2P

1P
2P

OU T1P 10 35 OUT2P

DRIV ER
DRIV ER

(6.0)
18.5 ± 0.1
GND P1 11 34 GNDP2

7/16
(MAX 18.85 include BURR)
GND P1 12 33 GNDP2
Top View

BD5426EFS
OU T1N 13 32 OUT2N
1N
2N

OU T1N 14 31 OUT2N
DRIV ER
DRIV ER

Fig. 23 Pin Assignment Diagram

TYPE
V CCP1N 15 30 V CCP2N

22
23
V CCP1N 16 29 V CCP2N

Lot No.
(5.0)
BSP1N 17 28 BSP2N

W A RNING Protections & L ogic Power- off

W ARNING 18 Detector 27 V HOL D

Fig. 24 Outer Dimensions and Inscriptions of HTSSOP-A44 Package

ERROR Soft M ute
ERROR 19 Under V oltage Protection 26 TM
High Temperature Protection Ramp
M U TEX 20 M ute Generator 25 ROSC

(Unit: mm)
Control
N.C. 21 N.C. Output Short Protection 24 M S
Clock
Output DC V oltage Protection Control
N.C. 22 N.C. 23 OSC

2010.05 - Rev.B
Technical Note
BD5426EFS Technical Note

●Explanation of Pin Functions (Provided pin voltages are typical values.)

No. Symbol Pin voltage Pin description Internal equalizing circuit

40

ch1 Analog signal input pin

1 IN1 ch2 Analog signal input pin 20k
3.5V 1/44
44 IN2
Input audio signal via a capacitor.

43

40

Voltage-to-current conversion pin for

output power limiter function
2 PLMT1 3.5V 2
Connect a register.

43

40

Current-to-voltage conversion pin for

output power limiter function
3 PLMT2 - 3
Connect a register.

43

40

Current-to-voltage conversion pin for

output power limiter function 4
4 PLMT3 -
Connect a register.

43

40

Bias pin for output power limiter function

5 PLMT4 3.5V 5
Connect a register and a capacitor.

43

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BD5426EFS Technical Note

●Explanation of Pin Functions - Continued

No. Symbol Pin voltage Pin description Internal equalizing circuit

ch1 positive bootstrap pin

6 BSP1P - 7 ,8
Connect a capacitor.

6
ch1 positive power system power supply
7, 8 VCCP1P Vcc
pin
9 10

ch1 positive PWM signal output pin

9, 10 OUT1P Vcc ~ 0V
Connect with output LPF.

11 12
11, 12 GNDP1 0V ch1 power system GND pin
1 5 ,1 6

ch1 negative PWM signal output pin 17

13, 14 OUT1N Vcc ~ 0V
Connect with output LPF.

1 3 ,1 4

ch1 negative power system power supply

15, 16 VCCP1N Vcc
pin

17 BSP1N - ch1 negative bootstrap pin 1 1 ,1 2

Connect a capacitor.

40

Warning output pin

Pin to notify operation warning. 2k

H: 5V
18 WARNING H: Under warning 18
L: 0V
L: Normal operation

Connect a resister.

43

40

Error output pin

A pin for notifying operation errors.

H: 5V
19 ERROR H: Error 19
L: 0V 2k
L: Normal operation

Connect a resister.

43

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BD5426EFS Technical Note

●Explanation of Pin Functions - Continued

No. Symbol Pin voltage Pin description Internal equalizing circuit

40

Audio mute control pin

120k
20 MUTEX - H: Mute off 20
L: Mute on

80k
43

N.C. pin
21, 22 N.C. - Nothing is connected with IC internal
circuit.

40

Sampling clock signal input/output pin

23 OSC - 23
When using two or more sampling clocks,
connect via a capacitor.

43

40
Master/Slave switching pin
120k
Switching of master/slave functions on a
24 MS - 24
sampling clock signal.
H: Slave operation
80k

L: Master operation
43

40

Internal PWM sampling clock frequency

setting pin
25 ROSC 5.6V
Usually the pin is used open. 25
To adjust an internal sampling clock
frequency, connect a resister.
32k

43

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BD5426EFS Technical Note

●Explanation of Pin Functions - Continued

No. Symbol Pin voltage Pin description Internal equalizing circuit

40

Audio muting constant setting pin

26 TM 0 ~ 5V 26
Connect a capacitor.

43

40

Instantaneous power interruption detecting

180k
voltage setting pin
27 VHOLD 0.68×Vcc 27
Connect a capacitor.
To adjust a detecting voltage, connect a

390k
resister.

43

ch2 negative bootstrap pin

28 BSP2N -
Connect a capacitor. 29,3 0

28
ch2 negative power system power supply
29, 30 VCCP2N Vcc
pin
31,3 2

ch2 negative PWM signal output pin

31, 32 OUT2N Vcc ~ 0V
Connect an output LPF.

33,3 4
33, 34 GNDP2 0V ch2 power system GND pin
37,3 8

ch2 positive PWM signal output pin 39

35, 36 OUT2P Vcc ~ 0V
Connect an output LPF.

35,3 6

ch2 positive power system power supply

37, 38 VCCP2P Vcc
pin

ch2 positive bootstrap pin 33,3 4

39 BSP2P -
Connect a capacitor.

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BD5426EFS Technical Note

●Explanation of Pin Functions - Continued

No. Symbol Pin voltage Pin description Internal equalizing circuit

40 VCCA Vcc Analog system power pin

40

Vcc+35 PWM system bias pin 41

41 FILP
12 Connect a capacitor.

43

40

Analog signal system bias pin

42 FILA 3.5V 42
Connect a capacitor.

43

43 GNDA 0V Analog system power supply pin

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www.rohm.com
BD5426EFS

C1 C44
2.2µF 2.2 µ F
INPU T INPUT
c h-1 1 44 ch-2
R2
・Vcc=10V ~ 16.5V

22k Ω
2 43
GNDA

GNDA
GNDA
3 Power FIL A 42

C42

R3
C43

C41

10 µ F
L imit

10 µ F

22k Ω
4 PW M 1 PW M 2 FIL P 41

1µF
C40
V CCA

R4
0.1 µ F

0.1 µ F
C5
22k Ω
5 40

© 2010 ROHM Co., Ltd. All rights reserved.

GND A
V CCA

6 39
V CCP V CCP

C6
C39
7 38

0.68 µ F

0.68 µ F
8 37
L9 L35

C7
C37
C38

22 µ H 22 µ H
10 µ F

9 36

0.1 µ F
0.1 µ F

C8 10 µ F
1P
2P
●Application Circuit Diagram (under stereo operation)

10 35

DRIV ER
DRIV ER

C9
C35

11 34

0.15 µ F
0.15 µ F

SP ch1 SP ch2

13/16
6Ω 12 33 6Ω

C10
GNDP GNDP
C32

L31

C13
C31

13 32 22 µ H

0.15 µ F

0.68 µ F
0.68 µ F

0.15 µ F

1N
2N
L13 14 31

DRIV ER
DRIV ER
22 µ H

C15
C29

15 30
0.1 µ F

0.1 µ F
16 29

C17
C28
0.68 µ F

0.68 µ F
17 28

W A RNING Protections & Logic Power- off

18 27

Fig. 25 Circuit Diagram of Stereo Operation with 6Ω Load

W ARNING OU TPUT Detector C27
R18
GNDD

100k Ω ERROR 3.3 µ F

ERROR OUTPU T 19 Under V oltage Protection Soft M ute 26
R19 C26
100k Ω High Temperature Protection Ramp 0.1 µ F
M UT E 20 M ute Generator 25 O PEN
Control SL A VE
N.C. 21 N.C. Output Short Protection 24
Clock
Output DC V oltage Protection Control M A STER
N.C. 22 N.C. 23 CLK I /O
C23
0.1 µ F

2010.05 - Rev.B
Technical Note
BD5426EFS Technical Note

Table 1 BOM List of Stereo Operation with 6Ω Load

Configuration
Rated Temperature
No. Item Part Number Vendor Value Tolerance Quantity Reference
voltage characteristics
mm inch

1 IC BD5426EFS ROHM HTSSOP-A44 - - - - 1 IC1

2 C GRM219B31E684KA88D MURATA 2012 0805 0.68µF 25V ±10% ±10% 4 C6, C17, C28, C39

3 C GRM188R11H104KA93 MURATA 1608 0603 0.1µF 50V ±10% ±10% 5 C7, C15, C29, C37, C40

4 C GRM31MB11H154KA01B MURATA 3216 1206 0.15µF 50V ±10% ±10% 4 C9, C13, C31, C35

5 C 25ST225M3216 Rubycon 3225 1210 2.2µF 25V ±20% ±5% 2 C1, C44

6 C 50ST684M3225 Rubycon 3225 1210 0.68µF 50V ±20% ±5% 2 C10, C32

7 C GRM21BB31E335KA75 MURATA 2012 0805 3.3µF 25V ±10% ±10% 1 C27

8 C GRM188B11E104KA MURATA 1608 0603 0.1µF 25V ±10% ±10% 3 C5, C23, C26

9 C GRM21BB11C105KA MURATA 2012 0805 1µF 16V ±10% ±10% 1 C41

10 C GRM21BB31C106KE15 MURATA 2012 0805 10µF 16V ±10% ±10% 1 C42

11 C 25SVPD10M SANYO 6666 2626 10µF 25V ±20% ±25% 3 C8, C38, C43

12 R MCR01MZPF2202 ROHM 1005 0402 22kΩ 50V ±1% ±200ppm/℃ 3 R2, R3, R4

13 R MCR01MZPF1003 ROHM 1005 0402 100kΩ 50V ±1% ±200ppm/℃ 2 R18, R19

Configuration
DC Rated
No. Item Part Number Vendor Value Tolerance Quantity Reference
Resistance DC Current
mm

14 L 7G09B-220M SAGAMI 10×9×10 22µH×2 ±20% 44mΩmax. 4.1A max. 2 L9, L13, L31, L35

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BD5426EFS Technical Note

●Notes on Usage
1. About absolute maximum ratings
If an applied voltage or an operating temperature exceeds an absolute maximum rating, it may cause destruction of a
device. A result of destruction, whether it is short mode or open mode, is not predictable. Therefore, provide a physical
safety measure such as fuse, against a special mode that may violate conditions of absolute maximum ratings.

2. About power supply line

As return of current regenerated by back EMF of output coil happens, take steps such as putting capacitor between
power supply and GND as a electric pathway for the regenerated current. Be sure that there is no problem with each
property such as emptied capacity at lower temperature regarding electrolytic capacitor to decide capacity value. If the
connected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage
on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute
maximum ratings. It is recommended to implement a physical safety measure such as the insertion of a voltage clamp
diode between the power supply and GND pins.

3. Potential of GND (11, 12, 33, 34, and 43 pins)

Potential of the GND terminal must be the lowest under any operating conditions.

4. About thermal design

Perform thermal design with sufficient margins, in consideration of maximum power dissipation Pd under actual operating
conditions. This product has an exposed frame on the back of the package, and it is assumed that the frame is used with
measures to improve efficiency of heat dissipation. In addition to front surface of board, provide a heat dissipation pattern
as widely as possible on the back also.
A class-D power amplifier has heat dissipation efficiency far higher than that of conventional analog power amplifier and
generates less heat. However, extra attention must be paid in thermal design so that a power dissipation Pdiss should not
exceed the maximum power dissipation Pd.

Maximum power dissipation Pd 

Tjmax - Ta
W  Tjmax: Maximum temperature junction = 150[℃]
θ ja Ta: Operating ambient temperature [℃]
θja: Package thermal resistance [℃/W]
1 
Power dissipation P diss  P O


η
- 1



W  Po: Output power [W]
  η: Efficiency

5. About operations in strong electric field

Note that the device may malfunction in a strong electric field.

6. Thermal shutdown (TSD) circuit

This product is provided with a built-in thermal shutdown circuit. When the thermal shutdown circuit operates, the output
transistors are placed under open status. The thermal shutdown circuit is primarily intended to shut down the IC avoiding
thermal runaway under abnormal conditions with a chip temperature exceeding Tjmax = 150℃, and is not intended to
protect and secure an electrical appliance. Accordingly, do not use this circuit function to protect a customer's electrical
appliance.

7. About shorting between pins and installation failure

Be careful about direction and displacement of an LSI when installing it onto the board. Faulty installation may destroy
the LSI when the device is energized. In addition, a foreign matter getting inbetween LSI pins, pins and power supply,
and pins and GND may cause shorting and destruction of the LSI.

8. About power supply startup and shutdown

When starting up a power supply, be sure to place the MUTEX pin (pin 20) at “L” level. When shutting down a power
supply also, be sure to place the pin at “L” level. Those processes reduce pop noises generated upon turning on and off
the power supply. In addition, all power supply pins must be started up and shut down at the same time.

9. About WARNING output pin (pin 18) and ERROR output pin (pin 19)
A WARNING flag is output from the WARNING output pin upon operation of the high-temperature protection function and
under-voltage protection function. And an ERROR flag is output from the ERROR output pin upon operation of VCC/GND
shorting protection function and speaker DC voltage applying protection function. These flags are the function which the
condition of this product is shown in. The use which aimed at the protection except for this product is prohibition.

10. About N.C. pins (pins 21 and 22)

The N.C. (Non connection) pins are not connected with an internal circuit. Leave the pins open or connect them to GND.

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BD5426EFS Technical Note

●Ordering part number

B D 5 4 2 6 E F S - E 2

Part No. Part No. Package Packaging and forming specification

EFS:HTSSOP-44 E2: Embossed tape and reel

HTSSOP-A44
<Tape and Reel information>
18.5±0.1
(MAX 18.85 include BURR) Tape Embossed carrier tape (with dry pack)
+6°
(6.0) 4° −4°
44 23 Quantity 1500pcs
0.5±0.15

E2
1.0±0.2
9.5±0.2
7.5±0.1

Direction
(5.0)

The direction is the 1pin of product is at the upper left when you hold
of feed ( reel on the left hand and you pull out the tape on the right hand )
1 22
0.85 1PIN MARK
+0.05
0.17 -0.03
S
1.0MAX

0.08 S
0.8 +0.05
0.85±0.05
0.08±0.05

0.37 -0.04 0.08 M

1pin Direction of feed

(Unit : mm) Reel ∗ Order quantity needs to be multiple of the minimum quantity.

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 Notice

Notes
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Examples of application circuits, circuit constants and any other information contained herein
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R1010A