Cascaded H-Bridge Multilevel Inverter With a Fault
Detection Scheme Based on the Statistic Moments
Indexes
V. Fernão Pires Tito G. Amaral
ESTSetúbal, Polytechnic ESTSetúbal, Polytechnic
Institute of Setúbal Institute of Setúbal
INESC-ID Lisboa Setúbal, Portugal
Setúbal, Portugal
Abstract—Multilevel inverters allow to generate AC voltages
with low total harmonic distortion (THD) but requires an
increased number of power switches. One of the disadvantages of
that is the increased probability of a fault in one of the power
switches. Thus in order to improve the reliability of the converter
a fast and robust fault detection scheme must be used. In this
context this paper presents a new fault detection scheme based on
the AC voltages of the inverter. The proposed scheme uses fault
factors that are based on the statistic moment method. This
method was used for the identification of image patterns. Due to
this the proposed scheme allows for a robust detection to load or
voltage variations. To test the method was used a cascaded H-
bridge inverter with five levels. Several tests were performed
through numerical results. The use of a laboratory prototype was
also used to confirm the proposed scheme.
Keywords—Cascaded H-bridge converter; multilevel inverter;
fault detection; fault diagnosis; open switch fault, statistic
moments.
I. INTRODUCTION
For many of the high industrial applications such as, AC
drives, renewable sources, HVDC and FACTS, it is used a
multilevel inverter. These converters are an important part of
those systems. Thus a failure in those converters will normally
lead to a stop in the process. Due to the importance of many of
those systems, it is normally required inverters with a high
reliability. One of the parts to ensure that reliability is the
existence of a fast and efficient fault detection scheme.
Multilevel inverters present several advantages over the
classical two level voltage source inverter, such as, AC
voltages with low THD, less electromagnetic interference and
less switching loss. Many research have been made and
several topologies have been proposed [1-5]. Among them,
one of the most studied is the cascaded H-bridge multilevel
inverter. In fact, the use of this topology has been proposed for
several applications [6-9]. However, one of the problems
associated to these power electronic converters is their
reliability in applications with high availability requirements.
In this context, the use of fault diagnosis is fundamental.
Due to the importance of high reliability, several
approaches have been proposed for the fault diagnosis of
978-1-XXXX-XXXX-X/16/$31.00 ©2016 IEEE
D. Foito A. J. Pires
ESTSetúbal, Polytechnic ESTSetúbal, Polytechnic
Institute of Setúbal Institute of Setúbal
Setúbal, Portugal CTS/UNINOVA
Setúbal, Portugal
cascaded H-bridge multilevel inverters. The methods normally
were developed to identify open switches fault. In fact, these
faults are one of the main industry concerns [10]. Some of the
methods are based on the signals frequency analysis [11,12].
Other methods use the analysis in the time domain [13-15]. In
this context, algorithms based on the Park Vector were also
used [16,17]. In [18] was proposed an algorithm based on the
analysis of the mass center of the AC voltages histogram.
Expert systems were also proposed for the identification of the
open switch faults in these converters. In fact, in [19] was used
a principal component analysis and the multiclass relevance
vector machine.
In this paper it is presented a new approach for open
switch fault detection in cascaded H-bridge multilevel
inverters. This approach is based on the analysis of the AC
voltages. It uses indexes that allow to discriminate different
voltages patterns. Thus, it will be based on the statistic
moment algorithm that normally is used in pattern recognition
problems [20]. This approach results in a simple algorithm
that easily can be implemented and allows for a fast
diagnostic.
Following this, section II introduces the proposed fault
diagnosis approach and the power converter topology under
study. Section III presents some simulation results where is
possible to verify the effectiveness of the proposed system. To
confirm these results, in section IV, experimental results, from
a laboratory prototype, are presented. Finally, section V
reports the general conclusions of the work.
II. PROPOSED FAULT DIAGNOSIS SYSTEM
The topology of the cascaded H-bridge multilevel inverter
consists in the serial connection of the classical single-phase
two level voltage source inverter. The number of voltage
levels of the AC voltages depends on the number of the
inverters connected in serial. Fig. 1 shows the three-phase
inverter topology with five levels. It consists in two single-
phase H-bridge inverters connected in serial per phase. Several
modulation strategies can be used in this kind of topology. In
this work was adopted the carrier phase disposition PWM
(PDPWM) modulation technique.
193
 n The gravity center of the image is represented by the
coordinates ( t , V ). These coordinates are determined through
T11 T13 T21 T23 T31 T32 the use of the regular moments of zero order, m00 and first
orders, m10 and m01, by equation (3).
VDC VDC VDC
 m10
T12 T14 T22 T24 T33 T34
t =m
 00
 (3)
T15 T17 T25 T27 T35 T37  m
 V = 01
 m00
VDC VDC VDC

T16 T18 T26 T28 T36 T38 For this problem it is used the feature associated to the
eccentricity of the image. Thus, this feature will be determined
VA VC
through the use of six regular moments and given by:
VB

R R R 2
 2 2 
e=
1  m20 − m02 − m10 + m01 
m00  m00 m00 
L L L  (4)
 m m 
+ 4  m11 − 10 01 
Fig. 1. Three-phase cascaded H-bridge multilevel inverter.  m00 

There are several types of faults in these topologies.

However, this work will focus in the open switch fault that is This feature can be obtained more effectively using only
one of the most frequent as said before. In this approach the three and four central moments. Thus, the relation between the
AC voltage signals will be used. Associated to each open regular and the central moments can be obtained by:
switch fault there is a specific pattern of these voltages. Thus
it is proposed indexes based on the pattern analysis of the
voltages. One of the methods that was used in patterns  µ 00 = m00
problems is the statistic moment based method [20-22]. This 
 µ 10 = µ 01= 0
approach uses indexes that were based on the moment-based
features. The moments used to construct the moment invariants  m m
 µ 11= m11 − 10 01
are defined in the continuous but for practical implementation  m00
they are computed in the discrete form.  2
 m10 (5)
In this work it is used an index fault based on the statistic  µ 20 = m20 −
moments method. Thus, the proposed method is based on a m00

sliding window that has stored one cycle of the AC voltage  m 2
signals (Van, Vbn, Vcn). Since that window has the  µ 02 = m02 − 01
information of an image, each acquired signal (sample) is  m00
stored as a coordinate of an image given by voltage and time 
(t,V). According to this, the regular moment mpq with the 
order (p+q) is given by:
According to equation (4), the eccentricity can be
M determined through the use of the following equation [19]:
mpq = ∑( ti ) (Vi )
p q
(1)
i=1
e=
(µ 20 − µ02 )2 + 4 µ 11
(6)
where p and q are both natural numbers and the sum is made µ 00
over all the M samples of the window.
where µ20, µ02 and µ11 are the central moments of second order
The central moments, µpq, are invariant to translation and it and µ00 is the central moments of zero order.
can be determined tacking into consideration the origin of the
image and its gravity center (2). Through this last equation is possible to analyze the pattern
of the obtained voltages. However, in order to define a fault
factor that allow to determine each of the open switch fault,
  
p

M q
− −
µ pq = ∑ ti − t  Vi − V  (2) the following equation is defined:
i=1
   

194
 V4
ff i =k i (7)
ei

Where i = A, B, C and k is a gain.

This fault factor will allow to obtain discrete and fixed
values according to the condition of the switches. As will be
seen in the next section, the fault factor allows to obtain
different values (two positives, two negatives and a zero). In
case of no fault condition this fault factor gives the zero value.

III. SIMULATION RESULTS

The verification of the proposed approach was firstly made
through simulation results obtained by the program
Matlab/Simulink. The multilevel inverter presented in Fig. 1
was used, with a DC source voltage of 400 V, a RL load and
with a PWM with a switching frequency of 3 kHz. It was also Fig. 3. Simulation result for phase A for transistor fault condition T11.
used a carrier phase disposition PWM (PDPWM) modulation
technique. The sampling frequency was three times the
switching frequency.
Figures 2 to 4 present simulation results for the power
converter in normal condition and with open switch fault
(Transistor T11 and T17). From these figures it is possible to
verify that there is a specific pattern associated to each open
switch fault. In the first fault the maximum positive level (800
V) does not appear anymore. Thus, the number of levels is
reduced from five to four originating in this way an
asymmetric waveform. In the second fault it is the minimum
level (-800 V) that does not appear anymore. However, it is
possible to verify that the patterns are different (not
symmetrical between those two faults). In case of a fault in the
transistor T15 the minimum level also does not appear but the
pattern is equal from the one obtained with a fault in the
transistor T11 (although symmetrical). Since the method uses
the pattern to identify the faults, multilevel inverters with
different value of the DC voltage sources does not affect the Fig. 4. Simulation result for phase A for transistor fault condition T17.
identification of a fault since under the point of view of the
patterns they are equal. The different patterns that appear as a consequence of an
open transistor fault will be reflected in the fault factor. Table
I shows the values of the fault factors that are obtained for the
different open switch faults for the two H-bridge inverters of
phase A. As can be seen by this table the different values of
the fault factor clearly allow to discriminate which transistor is
in open fault.

TABLE I. FAULT FACTOR

Condition ffA
All transistors in healthy condition 0
Fault – transistor T11 or T14 -4,6
Fault – transistor T12 or T13 +4,6
Fault – transistor T15 or T18 -10,2
Fault – transistor T16 or T17 +10,2

Fig. 2. Simulation result for phase A in normal condition.

195
 Simulation tests in which the converter is firstly in normal
condition followed by an open switch fault were also done. In 10 FFa

Fig. 5 it is presented the time behavior of the faulty diagnosis 8 FFb

for one of these tests. In this case, at 0,12 s there is an open 6

FFc

transistor fault in T11. From this result is possible to confirm 4

that the index fault ffA changes from zero to -4,6 after the fault.

FFa, FFb, FFc

2
The other indexes remain at zero since there is not an open 0
switch fault associated to the inverters of the other phases. In -2
Fig. 6 is presented another simulation test, but in this case for
-4
a different open transistor fault. At 0,12 s there is a fault in the
-6
transistor T27. As expected the index fault ffB changes from
-8
zero to +10,2. A test with multiple faults was also performed.
This test starts with the converter in healthy mode, followed -10

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22
by T15 open switch fault at 0,09 s and a second open switch Time [s]
fault at 0,16 s for transistor T37. Since the faults are in the
transistors of phases A and C only the indexes related with Fig. 7. Behaviour of the fault indexes before and after T15 and T37 open
these phases change their values from zero to +4,6 and -10,2 transistor fault.
respectively. These results show that for faults in different
transistors, different values are obtained for the fault indexes.
Thus, it is possible to conclude that through the analyses of the IV. EXPERIMENTAL RESULTS
obtained values of these indexes it will be possible to To confirm the simulation results it was implemented a
discriminate the transistor under fault. laboratory prototype of this multilevel inverter. The tests with
this prototype were made for a DC voltage of 50 V and a RL
load. It was used a PDPWM modulation technique with a
switching frequency of 3 kHz. To simulate the open switch
10 FFa fault, the signal gate of the transistor, which is considered
8 FFb under fault, was permanently with zero volts (transistor
6
FFc
permanently in turn off mode).
4
Several tests were done where the inverter starts in normal
FFa, FFb , FFc

2
mode and after a while appears a transistor in fault mode. The
0
voltage waveform of one of the inverter phases with all the
-2 transistors in healthy condition presents the typical shape with
-4 five voltage levels as can be seen in Fig. 8. This shape changes
-6 when there is an open switch fault. In fact, as seen in Fig. 9 the
-8 number of voltage levels is reduced to 4 when there is an open
-10 switch fault in transistor T12. Comparing this result with the
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 one presented in the simulation results for the transistor T11
Time [s] (Fig. 3) is possible to verify that this pattern is symmetrical.
The same happens for an open switch fault T18, but in this
Fig. 5. Behaviour of the fault indexes before and after T11 open transistor case the pattern is different from the one obtained in the
fault. previous test. From these experimental results it is also
possible to confirm that the obtained voltage patterns allow to
discriminate between the different faulty transistors, as well as
10
FFa they are similar with the ones obtained by simulation.
8 FFb
6 FFc

4
FFa, FFb, FFc

-2

-4

-6

-8

-10

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22
Time [s]

Fig. 6. Behaviour of the fault indexes before and after T17 open transistor
fault.
Fig. 8. Experimental result for phase A in normal condition.

196
 10

FF
0

-2

-4

-6

-8

-10

Fig. 9. Experimental result for phase A for transistor fault condition T12. 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time [s]

Fig. 12. Behaviour of the fault index obtained from the experimental results
before and after T12 open transistor fault.

10

FF
0

-2

-4
Fig. 10. Experimental result for phase A for transistor fault condition T18.
-6

Fig. 11 shows an experimental result of phase A fault -8

index where the inverter is in normal mode and at 0,27 s -10

appears a transistor in faulty mode. In this case, the transistor 0.05 0.1 0.15 0.2 0.25
Time [s]
0.3 0.35 0.4 0.45 0.5

in faulty mode is T18. As expected, since the pattern of the

voltage changes after the transistor fault, the value of the fault
factor of phase A also changes. This value changes from 0 to -
10 confirming the previous assumptions. Another
experimental text in which there was used a different open
transistor fault was carried out. Fig. 12 shows the behaviour of
the phase A fault index before and after a fault in transistor
T12. From this figure it is possible to verify that initially the
fault index is zero, and after 0,26 s the fault index (ffA)
changes gradually to -10.
10
8
6
Fig. 13. Behaviour of the fault index obtained from the experimental results
before and after T17 open transistor fault.
A third experimental test in transient mode is presented in
Fig. 13. In this test at 0,25 s there is a T17 open transistor
fault. As expected the fault factor ffA changes its value after
the transistor fault from zero to 10. Through this result is
possible to confirm that this experimental result is similar with
the one obtained by simulation (Fig. 6). All these experimental
results also allowed to confirm that the method is independent
of the inverter parameter since for the simulation tests it was
used DC sources with 400 V and in these ones it was used DC
sources with 50 V.

2
V. CONCLUSIONS
In this work it was presented a new approach for the
FF

-2 detection of an open transistor fault in cascaded H-bridge

-4 multilevel inverter. The proposed method uses indexes that are
-6
based on the analyses of the AC voltages pattern. This method
-8
was based in an algorithm that normally is used in pattern
-10
recognition problems. So, the fault factors were derived from
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
the statistic moment based method. The obtained values by
Time [s] those fault factors are related with the specific location of the
faulty switch. On other hand, they are independent of the load.
Fig. 11. Behaviour of the fault index obtained from the experimental results
before and after T18 open transistor fault. In order to verify the effectiveness of this approach several
tests were performed with a five-level cascaded H-bridge
inverter. For the simulation tests it was used the package

197
 Matlab/Simulink. A laboratory prototype was also used, in
order to confirm the simulation results. Through the obtained
results it was possible to verify the effectiveness of the
proposed fault detection scheme.
ACKNOWLEDGMENT
This work was supported by national funds through FCT –
Fundação para a Ciência e a Tecnologia, under projects
UID/CEC/50021/2013 and UID/EEA/00066/2013.
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