R.M.K.

ENGINEERING COLLEGE
R.S.M.Nagar, Kavaraipettai, Gummidipoondi Taluk, Thiruvallur District, Tamil Nadu 601 206.
(AN AUTONOMOUS INSTITUTION)
( Affiliated to Anna University, Chennai / Approved by AICTE ,New Delhi / Accredited by NAAC with A+ Grade /
ISO 9001:2015 Certified Institution / All the eligible UG Programs are Accredited by NBA, New Delhi)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SUBJECT CODE/ NAME

20EC0241/ Principles of Electronics Engineering Lab

REGISTER NUMBER : 111720202044

NAME OF THE CANDIDATE : M.S.SANGAVI

 R.M.K. ENGINEERING COLLEGE
R.S.M.Nagar, Kavaraipettai, Gummidipoondi Taluk, Thiruvallur District, Tamil Nadu 601 206.
(AN AUTONOMOUS INSTITUTION)
( Affiliated to Anna University, Chennai / Approved by AICTE ,New Delhi / Accredited by NAAC with A+ Grade /
ISO 9001:2015 Certified Institution / All the eligible UG Programs are Accredited by NBA, New Delhi)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

RECORD NOTE BOOK

Register Number 111720202044

Certify that this is the bonafide record of work done by Selvan/Selvi …

M.S.SANGAVI…………..…….. of II Semester of Computer Science & Business Systems

Branch during the year 2020 – 2021 in the Principles of Electronics Engineering +

Laboratory.

Staff-in-charge Head of the Department

Submitted for the practical examination on ……02/08/2021…………………

 INTERNAL EXAMINER EXTERNAL EXAMINER

R.M.K. ENGINEERING COLLEGE

R.S.M.Nagar, Kavaraipettai, Gummidipoondi Taluk, Thiruvallur District, Tamil Nadu 601 206.
(AN AUTONOMOUS INSTITUTION)

TABLE OF CONTENTS
Date of
S.no Date Name of the Experiment Marks Sign
submission
Semiconductor Diodes and Applications

16.04.2021 Characteristics of PN junction diode 23.04.2021

1

23.04.2021 Zener diode characteristics & Regulator using 30.04.2021

2
Zener diode
30.04.2021 Full wave Rectifier 07.05.2021
3

4 07.05.2021 Common Emitter Input Output characteristics 14.05.2021

14.05.2021 Common Base Input Output characteristics 21.05.2021

5

21.05.2021 Simplification, realization of Boolean 28.05.2021

6 expressions using logic gates/Universal gates.

28.05.2021 04.06.2021
Realization of Half/Full adders using logic
7
gates.
04.06.2021 11.06.2021
Realization of Half/Full Subtractors using logic
8
gates.
11.06.2021 Construction of simple Decoder circuits using 18.06.2021
9 logic gates.

18.06.2021 Construction of simple Multiplexer circuits 25.06.2021

10 using logic gates.

11 25.06.2021 Realization of Synchronous Up/Down counter 30.06.2021

CONTENT BEYOND SYLLABUS

12 25.06.2021 Shift Registers 30.06.2021

EXPT.NO:1 DATE:16.04.2021

CHARACTERISTICS OF PN JUNCTION DIODE

AIM:

To Plot the Volt Ampere Characteristics of PN Junction Diode under Forward and Reverse Bias Conditions
and also to find the Cut-in voltage, Static Resistance, Dynamic Resistance for forward Bias & Reverse
Bias.

APPARATUS:

S Name Range/V Quan

. alue tity

N
o
.

1 DC Regulated Power Supply 0 – 30 1

volts
2 Diode 1N 1
4001
3 Resistor 1K 1
4 0– E
100mA, a
0– c
500A h
1
D.C Ammeters

5 D.C Volt meters 0 E

– a
2 c
V, h
0 1
–
2
0
V
6 Bread Board and connecting wires - 1

S
e
t
PROCEDURE:
FORWARD BIAS CHARACTERISTICS:

1. Connect the Circuit as per the Circuit Diagram on the bread board.
2. Switch on the Regulated Power Supply and slowly increase the source voltage. Increase
the Diode Current in steps of 2mA and note down the corresponding voltage across the
PN junction Diode under forward Bias condition as per table given below.
3. Take the readings until a Diode Current of 30mA.
4. Plot the graph VF versus IF on the graph Sheet in the 1st quadrant as in Fig.
5. From the graph find out the Static & Dynamic forward Bias resistance of the diode
6. Observe and note down the cut in Voltage of the diode.

REVERSE BIAS CHARACTERISTICS:

1. Connect the Circuit as per the Circuit Diagram on the bread board.
2. Switch on the Regulated Power Supply and slowly increase the source voltage. Increase
the Diode voltage in steps of 2.0 volts and note down the corresponding Current against
the Voltage under Reverse Bias condition as per table given below.
3. Take readings until a Diode Voltage reaches 30.0V.
4. Plot the graph VR versus IR on the graph Sheet in the 3rd quadrant as in Fig.
5. From the graph find out the Dynamic Reverse Bias resistance of the diode.
6. Observe and note down the break down Voltage of the diode.

OUTPUT – FORWARD BIAS

OUTPUT – REVERSE BIAS
RESULT :
The V-I Characteristics of the PN Junction Diode are plotted for the both Forward and Reverse
Bias conditions and Calculated the Cut in Voltage, Dynamic Forward and Reverse Bias resistance.

EXPT. No: 2 DATE: 23.04.2021

CHARACTERISTICS OF ZENER DIODE , LINE & LOAD REGULATION

AIM:

To Obtain the Forward Bias and Reverse Bias characteristics of a Zener diode & also find out the
Zener Break down Voltage from the Characteristics. And obtain the Load regulation characteristics.
APPARATUS:

S. No. Name Range/Value Quantity

1 DC Regulated Power Supply 0 – 30 volts 1

2 Diode ECZ 5.1 1

3 Resistor 1K, 560 Each 1

4 D.C Ammeters 0–200Ma 1

Each 1
5 D.C Volt meters 0–2V, 0–20V
6 Decade Resistance Box - 1

1 Set
7 Bread Board and connecting wires -
PROCEDURE:

FORWARD BIAS CHARACTERISTICS:

1. Connect the Circuit as per the Circuit Diagram.

2. Switch on the Regulated Power Supply and slowly increase the source voltage. Increase
the Diode Current in steps of 2mA and note down the corresponding voltage across the
Zener Diode under forward Bias condition as per table given below.
3. Take the readings until a Diode Current of 20mA.
4. Plot the graph VF versus IF on the graph Sheet in the 1st quadrant as in Fig.
5. From the graph find out the Static & Dynamic forward Bias resistance of the diode
REVERSE BIAS CHARACTERISTICS:

1. Connect the Circuit as per the Circuit Diagram.

2. Switch on the Regulated Power Supply and slowly increase the source voltage. Increase
the Diode Current in steps of 2mA and note down the corresponding voltage across the
Zener Diode under Reverse Bias condition as per table given below.
3. Take the readings until a Diode Current of 20mA.
4. Plot the graph VR versus IR on the graph Sheet in the 3rd quadrant as in Fig.
5. From the graph find out the Dynamic Reverse Bias resistance of the diode.
6. Observe and note down the break down Voltage of the diode.

LOAD REGULATION CHARACTERISTICS:

1. Connect the Circuit as per the Circuit Diagram.

2. By changing the load Resistance, kept constant I/P Voltage at 5V, 10 V,
15 V as per table given below. Take the readings of O/P Voltmeter
(Vo=Vz).
3. Now by changing the I/P Voltage, kept constant load Resistance at 1K,
2K, 3K as per table given below. Take the readings of O/P Voltmeter
(Vo=Vz).

LINE REGULATION CHARACTERISTICS:

1. Connect the Circuit as per the Circuit Diagram.

2. Keeping load current constant, the input voltage is varied and corresponding
observations are made’
3. Plot the graph.

ZENER BREAKDOWN VOLTAGE:

Draw a tangent on the reverse Bias Characteristic of the Zener Diode

starting from the Knee and touching most of the points of the curve. The point
where the tangent intersects the X-axis is the Zener Breakdown Voltage.
OUTPUT -LINE REGULATOR
OUTPUT – LOAD REGULATION
OUTPUT – ZENER CHARACTERISTICS
RESULT:

The Characteristics of Zener Diode, line and load regulation are verified.

EXPT. NO: 3 Date:30.04.2021

FULL-WAVE RECTIFIERS

AIM:
 To Rectify the AC signal and then to find out Ripple factor and percentage of Regulation
in Full-wave rectifier center tapped circuit with and without Capacitor filter. APPARATUS:
S. No. Name Range/Value Quantity

1 Transformer 230V / 9-0-9V 1

2 Diode 1N4001 2

1000F/16V,
3 Capacitors 1
470f/25V
4 Decade Resistance Box - 1

5 Multimeter - 1

6 Bread Board and connecting wires - 1

7 Dual Trace CRO 20MHz 1

PROCEDURE:
WITHOUT FILTER:

1. Connect the circuit as per the circuit diagram.

2. Connect the primary of the transformer to main supply i.e. 230V, 50Hz
3. Connect the decade resistance box and set the RL value to 100Ω
4. Connect the Multimeter at output terminals and vary the load resistance (DRB) from
100Ω to 1KΩ and note down the Vac and Vdc as per given tabular form
5. Disconnect load resistance ( DRB) and note down no load voltage Vdc (V no load)
6. Connect load resistance at 1KΩ and connect Channel – II of CRO at output terminals and
CH – I of CRO at Secondary Input terminals observe and note down the Input and Output
Wave form on Graph Sheet.
7. Calculate ripple factor and percentage of regulation

WITH CAPACITOR FILTER:

1. Connecting the circuit as per the circuit Diagram and repeat the above procedure
from steps 2 to 8.

WITHOUT FILTER - OUTPUT

INPUT WAVEFORM
 OUTPUT :

TABULATION
TIME PERIOD AMPLITUDE
INPUT 2*0.1 = 0.2 1*1.3=1.3
OUTPUT 2*0.1 = 0.2 1*1.3=1.3

CALCULATIONS
WITH FILTER – CIRCUIT DIAGRAM
OUTPUT WAVEFORM

RESULT:
Thus the Full wave rectifier with and without filter is constructed and waveforms are drawn and ripple
factor is calculated.

EXPT. NO: 4 DATE:07.05.2021

COMMON EMITTER TRANSISTOR CHARACTERISTICS

AIM:

To plot the Input and Output characteristics of a transistor connected in Common Emitter Configuration
and to find the h – parameters from the characteristics.

APPARATUS:
S. No. Name Range/Value Quantity

1 Dual Regulated D.C Power supply 0–30 Volts 1

2 Transistor BC107 1

3 Resistors 120K 1

4 DC Ammeters (0-500A), (0-200mA) Each 1 No

5 DC Voltmeters (0-2V), (0-20V) Each 1 No

6 Bread Board and connecting wires - 1 Set

PROCEDURE:
TO FIND THE INPUT CHARACTERISTICS:

1. Connect the circuit as in the circuit diagram.

2. Keep VBB and VCC in zero volts before giving the supply
3. Set VCE = 1 volt by varying VCC and vary the VBB smoothly with fine control such
that base current IB varies and note down the corresponding voltage V BE for each
step in the tabular form.
4. Repeat the experiment for VCE =2 volts and 3 volts.
5. Draw a graph between VBE Vs IB against VCE = Constant.

TO FIND THE OUTPUT CHARACTERISTICS:

1. Start VEE and VCC from zero Volts.

2. Set the IB = 20µA by using VBB such that, VCE changes in steps of 0.2 volts from
zero upto 10 volts, note down the corresponding collector current I C for each step
in the tabular form.
3. Repeat the experiment for IE = 40µA and IE = 60µA, tabulate the readings.
4. Draw a graph between VCE Vs IC against IB = Constant.

OUTPUT – INPUT CHARACTERISTICS

OUTPUT CHARACTERISTICS
RESULT:
The input and output characteristics are drawn on the graphs.

EXPT. NO: 5 DATE:14.05.2021

 COMMON BASE TRANSISTOR CHARACTERISTICS
AIM:

To plot the Input and Output characteristics of a transistor connected in Common Base Configuration and
to find the h – parameters from the characteristics.

APPARATUS:
S. No. Name Range/Value Quantity

1 Dual Regulated D.C Power supply 0–30 Volts 1

2 Transistor BC107 1

3 Resistors 1K 1

4 DC Ammeters (0-200mA) 2

5 DC Voltmeters (0-2V), (0-20V) Each 1 No

6 Bread Board and connecting wires - 1 Set

PROCEDURE:

TO FIND THE INPUT CHARACTERISTICS:

1. Connect the circuit as in the circuit diagram.

2. Keep VEE and VCC in zero volts before giving the supply
3. Set VCB = 1 volt by varying VCC. and vary the VEE smoothly with fine control such that emitter
current IE varies note down the corresponding voltage VEB for each step in the tabular form.
4. Repeat the experiment for VCB =2 volts and 3 volts. Draw a graph between V EB Vs IE against
VCB = Constant

TO FIND THE OUTPUT CHARACTERISTICS:

1. Start VEE and VCC from zero Volts.

2. Set the IE = 1mA by using VEE such that, VCB changes in steps of 1.0 volts from zero upto 20
volts, note down the corresponding collector current IC for each step in the tabular form.
3. Repeat the experiment for different values of IE, tabulate the readings.
4. Draw a graph between VCB Vs IC against IE = Constant.

INPUT CHARACTERISTICS :
CIRCUIT DIAGRAM

TABULATION
BJT – CB CHARACTERISTICS CIRCUIT DIAGRAM
RESULT

Thus the CB characteristics of transistor is verified and the graphs are drawn.

EXPT.NO:6 DATE:21.05.2021
 SIMPLIFICATION AND REALIZATION OF
BOOLEAN EXPRESSIONS USING LOGIC GATES AIM:
To simplify and realize the Boolean expressions and implement the same using
logic gates.
APPARATUS:
1. IC 7408 2.
IC 7404 3. IC
7402 4. IC
7400 5. IC
7432 6. IC
7486

PROCEDURE:

1. Simplify the expression/ minterms/ maxterms using k-map.

2. Draw the logic circuit and give the connections accordingly.
3. Verify the output.

CIRCUIT DIAGRAM
Y=AB +C
Y=AB+B’C
RESULT:

Thus the Boolean expressions are implemented using logic gates and outputs are verified.

EXPT.NO:7 DATE:28.05.2021

REALIZATION OF HALF/FULL ADDERS USING LOGIC GATES.

AIM

To implement half and full adder using logic gates and to verify its truth table.

COMPONENTS REQUIRED

1. IC 7408 2.
IC 7402 3. IC
7432
4. IC 7486

PROCEDURE:

1. Simplify the expression/ minterms/ maxterms using k-map.

2. Draw the logic circuit and give the connections accordingly.
3. Verify the output.

TRUTH TABLE:
HALF ADDER

EXPRESSION:
Sum = A XOR B
Carry = A AND B

LOGIC DIAGRAM:
FULL ADDER TRUTH TABLE

EXPRESSION

SUM = (A XOR B) XOR Cin = (A B) Cin

CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A B)
LOGIC DIAGRAM
RESULT

Thus half adder and full adder are implemented using logic gates and truth tables are verified.

EXPT.NO:8 DATE: 04.06.2021

 REALIZATION OF HALF/FULL SUBTRACTORS USING LOGIC GATES

AIM

To implement half and full subtractor using logic gates and to verify its truth table.

COMPONENTS REQUIRED

1. IC 7408
2. IC 7402
3. IC 7432
4. IC 7486
5. IC7404
PROCEDURE:

1. Simplify the expression/ minterms/ maxterms using k-map.

2. Draw the logic circuit and give the connections accordingly.
3. Verify the output.

HALF SUBTRACTOR
TRUTH TABLE

EXPRESSION
LOGIC DIAGRAM
FULL SUBTRACTOR TRUTH TABLE

EXPRESSION

LOGIC DIAGRAM
CONNECTION

RESULT:
Thus half and full subtractor circuits are implemented and truth tables are verified.

EXPT.NO : 9 DATE:11.06.2021
 CONSTRUCTION OF SIMPLE DECODER CIRCUITS USING LOGIC GATES

AIM:
To design and implement 4x2 encoder and 2x4 decoder and verify its truth table.
APPARATUS REQUIRED

1. OR gate (IC 7432)

2. NOT gate (IC 7404)
3. AND gate (IC 7408)

PROCEDURE

1. Simplify the expression/ minterms/ maxterms using k-map.

2. Draw the logic circuit and give the connections accordingly.
3. Verify the output.
DECODER
A Decoder is a digital circuit that identifies each code present at the input. A Decoder does the reverse
operation of an encoder. It has ‘n’ input lines and ‘2 n’output lines. It is used to memory system of
computer.

D0 = x′.y′

D1 = x′.y

D2 = x.y’

D3 = x.y
TRUTH TABLE
LOGIC DIAGRAM

CONNECTION
RESULT:

Thus decoder circuit is implemented using logic gates and truth table is verified.

EXPT.NO : 10 DATE:18.06.2021
 CONSTRUCTION OF SIMPLE MULTIPLEXER CIRCUITS USING LOGIC GATES

AIM:

To design and construct 4 x 1 multiplexer and 1 x 4 demultiplexer and verify its truth table.

APPARATUS REQUIRED:

Three input AND gate (IC 7411)

OR gate (IC7432) NOT

gate (IC7404)

THEORY:

The function performed by a multiplexer is to select 1 out of N input data sources and to transmit the
selected data to a single information channel. The selection of the desired data-input is controlled by
the SELECT inputs. In the 4 X 1 multiplexer, it has 4-line inputs designated by D0, D1, D2 and D3 and
one output and two SELECT lines A& B. A demultiplexer performs the reverse operation of a
multiplexer. It accepts a single input and distributes it over several outputs. The SELECT input code
determines to which output the data input will be transmitted. TRUTH TABLE

LOGIC DIAGRAM

CONNECTION
RESULT

Thus multiplexer circuit is implemented and verified.

EXPT.NO : 11 DATE:25.06.2021

REALIZATION OF SYNCHRONOUS COUNTER

AIM:
 To construct a 4 bit synchronous counter and verify its truth table.

APPARATUS REQUIRED:

1. JK Flip Flop(IC 7473)

2. AND gate (IC 7408)
3. OR gate (IC 7432)
4. NOT gate (IC 7404)

THEORY:

A counter that advanced upward through H8 sequence (0,1,2,3,0,1, . . . .) is called up counter. A

counter that denotes downward through its sequence (3,2,1,0,3,2,1, . . . ) is called down counter. A
up / down counter is a counter used to perform both up counting and down counting operation using
up / down control signal.

PROCEDURE:

1. Connecting are given as per logic circuit.

2. Supply and ground connections are given to all IC’s according to pin diagram
3. Using up / down signal and circuit, truth table was verified.
LOGIC DIAGRAM
CONNECTIONS
RESULT

Thus 4- bit synchronous counter is designed and verified.

 CONTENT BEYOND SYLLABUS

EXPT.NO : 12 DATE:25.06.2021

REALIZATION OF SHIFT REGISTERS

AIM
To analyse the circuit and truth table of 4-bit SIPO (serial input parallel output) shift register by
using IC 7474 (D flip flop).

THEORY

In Serial In Parallel Out (SIPO) shift registers, the data is stored into the register serially while it is
retrieved from it in parallel-fashion. Figure 1 shows an n-bit synchronous SIPO shift register sensitive
to positive edge of the clock pulse. Here the data word which is to be stored (Data in) is fed serially at
the input of the first flip-flop (D1 of FF1). It is also seen that the inputs of all other flip-flops (except
the first flip-flop FF1) are driven by the outputs of the preceding ones like the input of FF2 is driven
by the output of FF1. In this kind of shift register, the data stored within the register is obtained as a
parallel-output data word (Data out) at the individual output pins of the flip-flops (Q1 to Qn).
In general, the register contents are cleared by applying high on the clear pins of all the flip-flops at
the initial stage. After this, the first bit, B1 of the input data word is fed at the D1 pin of FF1.This bit
(B1) will enter into FF1, get stored and thereby appears at its output Q1 on the appearance of first
leading edge of the clock. Further at the second clock pulse, the bit B1 right-shifts and gets stored
into FF2 while appearing at its output pin Q2 while a new bit, B2 enters into FF1. Similarly at each
clock pulse the data within the register moves towards right by a single bit while a new bit of the
input word enters into the register. Meanwhile one can extract the bits stored within the register in
parallelfashion at the individual flip-flop outputs.

In the right-shift SIPO shift-register, data bits shift from left to right for each clock pulse. However if
the data bits are made to shift from right to left in the same design, one gets a left-shift SIPO
shiftregister as shown by figure 3. Nevertheless the basic working principle remains the same except
the fact that now Bn down to B1 is stored in Qn down to Q1 i.e. Q1 = B1, Q2 = B2 … Qn = Bn at the
nth clock pulse.

PROCEDURE

Step-1) Connect the supply(+5V) to the circuit.

Step-2) Keep the Reset and Preset as active-high signals .

Step-3) Apply the data at data input .

Step-4) Press clock pulse and observe this data at LED Q3.

Step-5) Then press "ADD" button to add data in the given truth table.

Step-6) Apply the next data at data input.

Step-7) Press clock pulse and observe that the data at LED Q3will shift to LED Q2 and the new data
applied will appear at Q3.

Step-8) Repeat steps 3 to 5 till all the 4 bits appear at the output of shift register.

Step-9) Press the "Print" button after completing your simulation to get your results.PROCEDURE

CONNECTION

RESULT

Thus SIPO shift register is implemented and verified

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