Professional Documents
Culture Documents
(Field Programmable Gate Array) : Subin Mathew Raset 29/09/09
(Field Programmable Gate Array) : Subin Mathew Raset 29/09/09
(FIELD PROGRAMMABLE
GATE ARRAY)
Subin Mathew
RASET
29/09/09
HISTORY
Programmable Read Only Memory (PROM)
address line as input
data line as output
Problem:
don’t require all the logic combination in
input.
Programmable Logic Array (PLA)
Programmable AND plane followed by
programmable or wired OR plane.
Sum of product form
Two level programming adds delay (problem)
NEXT
PAL ( Programmable array logic)
Programmable AND plane and fixed OR plane.
All these PLA and PAL are Simple programmable
logic devices.
Logic plane structure grows rapidly with number
of inputs( problem)
NEXT
To mitigate the problem
Complex programmable logic devices (CPLD)
programmably interconnect multiple SPLDs.
Extending to higher density difficult (problem)
Less flexibility (problem)
COMPARISON
FPGA
A field programmable gate array (FPGA) is a
Programmable Logic Device(PLD) with higher
densities and capable of implementing different
functions in a short period of time.
Topics covered:
• FPGA Overview
• Logic Block
• FPGA Routing Techniques
• FPGA Structural Classification
• Programming Methodology
• FPGA Design Flow
FPGA OVERVIEW
2D array of logic blocks and flipflops with
electrically programmable interconnections.
Compact design
User can configure
Intersections between the logic blocks and
The function of each block
Why do we need FPGAs?
WORLD OF INTEGRATED
CIRCUITS
PLD FPGA
WHICH WAY TO GO?
ASICs FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes Reprogrammable
OTHER FPGA ADVANTAGES
Manufacturing cycle for ASIC is very costly,
lengthy and engages lots of manpower
Mistakes not detected at design time have large
impact on development time and cost
FPGAs are perfect for rapid prototyping of digital
circuits
Easy upgrades like in case of software
Unique applications
reconfigurable computing
LOGIC BLOCKS
Purpose: implement combinational and
sequential logic functions.
Logic blocks can be implemented by:
• Transistor pairs
• Basic small gates such as twoinput NAND’s or
exclusiveOR’ s.
• Multiplexers
• Look up tables( LUT)
• Wide fanin ANDOR structure.
LOGIC BLOCK ARCHITECTURE
Granularity: is the number of boolean function
a logic block can implement, the number of
gates, transistors, total normalized area,
number of inputs and outputs.
According to granularity Two types of Blocks
Fine Grain Logic Blocks
Coarse Grain Logic Blocks
FINE GRAIN
1. The Cross Point
FPGA
Transistors are
interconnected.
Logic block is
implemented using
transistor pair tiles.
2. Plessey FPGA :
• 2input NAND gate forms basic building block
FINE GRAIN
Advantage:
Blocks are fully utilized.
Disadvantage:
Require large numbers of wire segments and
programmable switches. So it is costly in delay
and area size.
COARSE GRAIN LOGIC BLOCKS
Many types exists according to implementations
Multiplexer Based and LookupTable Based are
most common
1. The Xilinx Logic Block:
A SRAM function as a LUT.
Address line of SRAM as input
Output of SRAM gives the logic output
kinput logic function =2^k * 1 size SRAM
Advantage:
High functionality
k inputs logic block can be implemented in no.
of ways
Disadvantage:
Large no of memory cells required if i/p is large
2. Altera logic block:
Wide fanin
Up to 100 i/p AND gate fed into OR gate with 38
i/ps
Advantage:
Few logic block can implement the entire
functionality
Less area required
Disadvantage:
If i/ps are less, usage density of block will be low
Pull up devices consume static power
EFFECTS OF GRANULARITY ON FPGA
DENSITY AND PERFORMANCE
Tradeoff
Granularity increase > Blocks less
More Functional Blocks> more area
Area is normally measured by total number of bits
needed to implement the design. So look the
example
EXAMPLE
FPGA ROUTING TECHNIQUES
Comprises of programmable switches and wires
Provides connection between I/O blocks, logic
blocks etc.
Routing decides logic block density and area
consumed
Different routing techniques are:
Xilinx Routing architecture
Actel routing methodology
Altera routing methodology
Xilinx Routing architecture
connections are made through a connection block.
SRAM is used to implement LUT. So connection sites
are large
Pass transistors for connecting output pins
multiplexers for input pins.
wire segments used are:
general purpose segments
Direct interconnect
long line
clock lines
Xilinx routing architecture
Actel routing methodology
more wire segments in horizontal direction.
i/p & o/p vertical tracks can make connection with
every horizontal track.
Routing is flexible.
Drawback:
more switches are required => more capacitive load.
Altera routing methodology
It has two level hierarchy.
first level => 16 or 32 of the logic
blocks are grouped into a Logic Array Block(LAB)
connections are formed using EPROM
Second level=> LABs are interconnected using
Programmable Interconnect Array(PIA)
PROGRAMMING METHODOLOGY
Electrically programmable switches are used to
program FPGA
Properties of programmable switch determine on
resistance, parasitic capacitance, volatility,
reprogrammability, size etc.
Various programming techniques are:
SRAM programming technology
Floating Gate Programming
Antifuse programming methodology
SRAM programming technology
Use Static RAM cells to control pass gates or
multiplexers.
1= closed switch connection
0= open
For mux, SRAM determines the mux input selection
process.
Advantage
• Fast reprogrammability
• Requires large area
Floating gate programming
Tech used in EPROM and
EEPROM devices is used
Switch is disable by injecting
charge on the gate 2 using high
voltage between gate1 and drain.
The charge is removed by UV
light
Advantage:No external
permanent memory is needed to
program it at powerup
Disadvantage:
Extra processing steps
Static power loss due to pull
up resistor and high on
resistance
Antifuse programming methodology
2 terminal device with an un programmed
state present very high resistance.
By applying high voltage create a low
resistance link.
Advantage:
Small size
Low series resistance and low parasitic
capacitance
SUMMARY
WHY BETTER ?
FPGA programmed using electrically
programmable switches
Routing architectures are complex.
Logic is implemented using multiple levels of
lower fanin gates.
Shorter time to market
Ability to reprogram in the field to fix bugs
Lower nonrecurring engineering costs
FPGA DISADVANTAGE
FPGAs are generally slower than their
applicationspecific integrated circuit (ASIC)
Can't handle as complex a design, and draw
more power.
FPGA DESIGN AND
PROGRAMMING
To define the behavior of the FPGA the user provides
a hardware description language (HDL) or a
schematic design.
Then, using an electronic design automation tool, a
technologymapped net list is generated.
The netlist can then be fitted to the actual FPGA
architecture using a process called placeandroute.
The user will validate the map, place and route
results via timing analysis, simulation, and other
verification methodologies.
Once the design and validation process is complete,
the binary file generated used to configure the
FPGA.
APPLICATION
Reconfigurable computing.
Applications of FPGAs include DSP, software
defined radio.
The inherent parallelism of the logic resources
on the FPGA allows for considerable compute
throughput.
THANK YOU