MCT-222

Embedded Systems

Lecture 4: GPIO, Branches and

SysTick Timer

6-1
 LED interfaces
❑ The TM4C1294 can output (or sink? see datasheet) maximum of 12 mA current.

❑ Be careful in interfacing LEDs /switches/others peripherals, not to exceed the current

rating

❑ Large number of LEDs or LED needing higher large current (i.e. > 12 mA) may draw
excessive current and damage the microcontroller when directly connected to the PORT
pins

❑ Instead we insert buffers (e.g. ULN2003, 7407) to interface high current LED(s) (or
other peripheral)

6-2
 LED interfaces

Know voltage, current, power, Ohm’s Law.

6-3
Also read paragraphs related to Figure 4.16 of Textbook#1
 Switch Interface

Know voltage, current, power

6-4
Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Cuevas, Tiwari
Enabling internal pull-up/pull-down resistances

Set lower 8-bits of registers

• GPIO_PORTx_PDN_R
To enable internal pull-down resistance on PORTx

OR

• GPIO_PORTx_PUN_R
To enable internal pull-up resistance on PORTx

Example

Set Bit-4 of GPIO_PORTA_PDN_R

Set Bit-6 of GPIO_PORTA_PUR_R

Using internal resistances is a safe option

When interfacing switches 6-5
 Adding Delays While Reading in Switch

❑ Mechanical switches may oscillate between ON/OFF

due to friction, mass, spring

❑ Solution: Wait for some time e.g. 10 ms before

reading data from the PORT where switch is
connected.

❑ Homework: Modify switch input read program to

include 10 ms delays. See 4.24 of textbook#1.

6-6
Code bits: pre-requisite of conditional branches

❑ Recall suffix after arithmetic, logical and shift/rotate

instructions

❑ e.g.

❖ ANDS Perform bitwise AND and update code bits : N and Z

❖ LSRS Perform logical shift right and update code bits N,Z
and C
❖ ADDS Perform addition and update code bits: all N,Z,C and
V

6-7
Code bits: pre-requisite of conditional branches
Suffix Code bit Meaning
EQ Z=1 Equal
NE Z=0 Not equal
CS or HS C=1 Higher or same, unsigned ≥
CC or LO C=0 Lower, unsigned <
MI N=1 Negative
PL N=0 Positive or zero
VS V=1 Overflow
VC V=0 No overflow
HI C = 1 and Z = 0 Higher, unsigned >
LS C = 0 or Z = 1 Lower or same, unsigned ≤
GE N=V Greater than or equal, signed ≥
LT N≠V Less than, signed <
GT Z = 0 and N = V Greater than, signed >
LE Z = 1 and N ≠ V Less than or equal, signed ≤
AL Can have any value Always. This is the default when no suffix is
specified.

Condition code suffixes used to optionally execution instruction.

6-8
 Example: Conditional Branch Instruction

Label of some instruction

Branch (go to) Where we want to jump to

BEQ some_instr_label
If Z == 1, go to instruction
whose label is some_instr_label

Suffix: EQ checks if Z = 1

6-9
 Example: Conditional Branch Instruction

CMP R0,R1 ; Perform RO – R1 and update

and set code bits. Do not update R0 or R1

BEQ some_instr_label ; If Z == 1, go to instruction

whose label is some_instr_label

6-10
Conditional Branch Instructions
❑Unsigned conditional branch
❖follow SUBS CMN or CMP
BEQ target ; Branch if Equal(unsigned/signed)
BNE target ; Branch if not Equal (unsigned/signed)
BLO target ; Branch if unsigned less than
BLS target ; Branch if unsigned less than or equal to
BHS target ; Branch if unsigned greater than or equal to
BHI target ; Branch if unsigned greater than

CMP R0,R1

R0<R1
BLO
R0≥R1 target
Next instruction
6-11
Conditional Branch Instructions

❑Signed conditional branch

❖follow SUBS CMN or CMP
BLT target ; if signed less than
BGE target ; if signed greater than or equal to
BGT target ; if signed greater than
BLE target ; if signed less than or equal to

CMP R0,R1

R0<R1
BLT
R0≥R1 target
Next instruction
6-12
 Equality Test

Program 2.7.1. Conditional structures that test for equality.

6-13
Unsigned Conditional Structures

Program 2.7.2. Unsigned conditional structures.

6-14
Signed Conditional Structures

Program 2.7.4. Signed conditional structures.

6-15
If-then-else

Program 2.7.6

6-16
 While Loops

LDR R4, =G1 ; R4 -> G1 uint32_t G1,G2;

LDR R5, =G2 ; R5 -> G2 while(G2 > G1){
loop LDR R0, [R5] ; R0 = G2 Body();
LDR R1, [R4] ; R1 = G1 }
CMP R0, R1 ; is G2 <= G1?
BLS next ; if so, skip to next
BL Body ; body of the loop
B loop
next

6-17
For Loops

6-18
 For Loops

MOV R4, #0 ; R4 = 0 for(i=0; i<100; i++){

loop CMP R4, #100 ; index >= 100? Process();
BHS done ; if so, skip to done }
BL Process ; process function*
ADD R4, R4, #1 ; R4 = R4 + 1
B loop
done

Count up

MOV R4, #100 ; R4 = 100 for(i=100; i!=0; i--){

loop BL Process ; process function Process();
SUBS R4, R4, #1 ; R4 = R4 - 1 }
BNE loop
done

Count down

6-19
 SysTick Timer

❑Timer/Counter operation
❖24-bit counter decrements at bus clock
frequency
o With 80 MHz bus clock, decrements every 12.5 ns
❖Counting is from n → 0
o Setting n appropriately will make the counter a
modulo n+1 counter. That is:
➢next_value = (current_value-1) mod (n+1)
➢Sequence: n,n-1,n-2,n-3… 2,1,0,n,n-1…

6-20
 SysTick Timer

❑ Initialization (4 steps)
❖ Step1: Clear ENABLE to stop counter
❖ Step2: Specify the RELOAD value
❖ Step3: Clear counter by reading NVIC_ST_CURRENT_R
❖ Step4: Set NVIC_ST_CTRL_R
o CLK_SRC = 1 (bus clock)
o INTEN = 0 for no interrupts
o ENABLE = 1 to enable

6-21
 SysTick Timer
SysTick_Init
; disable SysTick during setup 24-bit Countdown Timer
LDR R1, =NVIC_ST_CTRL_R
MOV R0, #0 ; Clear Enable
STR R0, [R1]
; set reload to maximum reload value
LDR R1, =NVIC_ST_RELOAD_R
LDR R0, =0x00FFFFFF; ; Specify RELOAD value
STR R0, [R1] ; reload at maximum
; writing any value to CURRENT clears it
LDR R1, =NVIC_ST_CURRENT_R
MOV R0, #0
STR R0, [R1] ; clear counter
; enable SysTick with core clock
LDR R1, =NVIC_ST_CTRL_R
MOV R0, #0x0005 ; Enable but no interrupts (later)
STR R0, [R1] ; ENABLE and CLK_SRC bits set
BX LR
6-22
 SysTick Timer

❖ Once Timer has counted all the way from RELOAD value
to 0, it sets COUNT flag and start over to countdown
from RELOAD value. Timer keeps running…

❖ COUNT = 0 -> 1 when Timer values goes from 0x00000001

-> 0x00000000. Once set, COUNT stays 1, unless cleared
by some means(?).

❖ Any value written to NVIC_ST_CURRENT_R clears its

contents (i.e. NVIC_ST_CURRENT_R = 0x00000000) and
clears COUNT i.e COUNT = 0

❖ We can read current value of COUNT by reading

NVIC_ST_CTRL_R. After register is read, it clears
COUNT. 6-23
 SysTick Timer

;------------SysTick_Wait------------
; Time delay using busy wait.
; Input: R0 delay parameter in units of the core clock
; 80 MHz(12.5 nsec each tick)
; Output: none
; Modifies: R1
SysTick_Wait
SUB R0, R0, #1 ; delay-1
LDR R1, =NVIC_ST_RELOAD_R
STR R0, [R1] ; time to wait
LDR R1, =NVIC_ST_CURRENT_R
STR R0, [R1] ; any value written to CURRENT clears it
LDR R1, =NVIC_ST_CTRL_R
SysTick_Wait_loop
LDR R0, [R1] ; read status
ANDS R0, R0, #0x00010000 ; bit 16 is COUNT flag
BEQ SysTick_Wait_loop ; repeat until flag set
BX LR

6-24
 We have just developed a routine

SysTick_Wait

that uses introduces delay R0 times 12.5 ns

Register R0 has become an input to the routine!

6-25
 SysTick Timer
;------------SysTick_Wait10ms------------
; Call this routine to wait for R0*10 ms
; Time delay using busy wait. This assumes 80 MHz clock
; Input: R0 number of times to wait 10 ms before returning
; Output: none
; Modifies: R0
DELAY10MS EQU 800000 ; clock cycles in 10 ms
SysTick_Wait10ms
PUSH {R4, LR} ; save R4 and LR
MOVS R4, R0 ; R4 = R0 = remainingWaits
BEQ SysTick_Wait10ms_done ; R4 == 0, done
SysTick_Wait10ms_loop
LDR R0, =DELAY10MS ; R0 = DELAY10MS
BL SysTick_Wait ; wait 10 ms
SUBS R4, R4, #1 ; remainingWaits--
BHI SysTick_Wait10ms_loop ; if(R4>0), wait another 10 ms
SysTick_Wait10ms_done
POP {R4, PC}

6-26
 Thank You

Q&A

Slides credit: Jonathan Volvano (http://users.ece.utexas.edu/~valvano/)

6-27