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PIC16C71X: 8-Bit CMOS Microcontrollers With A/D Converter
PIC16C71X: 8-Bit CMOS Microcontrollers With A/D Converter
MCLR/VPP 4 17 OSC2/CLKOUT
- < 2 mA @ 5V, 4 MHz VSS 5 16 VDD
Features In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes Yes Yes Yes
Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP,
SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP
20-pin SSOP 20-pin SSOP 20-pin SSOP
Serial Port(s) SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART
(SPI/I2C, USART)
Parallel Slave Port — Yes — Yes
A/D Converter (8-bit) Channels 5 8 5 8
Interrupt Sources 11 12 11 12
I/O Pins 22 33 22 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
Program
Device Data Memory
Memory
PIC16C710 512 x 14 36 x 8
PIC16C71 1K x 14 36 x 8
PIC16C711 1K x 14 68 x 8
PIC16C715 2K x 14 128 x 8
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (sym-
metrical) instruction set that makes it possible to carry
out any operation on any register using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.
PIC16C710 512 x 14 36 x 8
PIC16C71 1K x 14 36 x 8
PIC16C711 1K x 14 68 x 8
PIC16C715 2K x 14 128 x 8
STATUS reg
8
3 MUX
Power-up
Timer
Instruction
Decode & Oscillator
Start-up Timer ALU
Control
Power-on 8
Timing Reset
Generation W reg
Watchdog
OSC1/CLKIN Timer
OSC2/CLKOUT
Brown-out
Reset(2)
Timer0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
User Memory
For those devices with less than 8K program memory,
Space
accessing a location above the physically implemented Interrupt Vector 0004h
address will cause a wraparound.
On-chip Program 0005h
The reset vector is at 0000h and the interrupt vector is Memory
at 0004h.
03FFh
FIGURE 4-1: PIC16C710 PROGRAM 0400h
MEMORY MAP AND STACK
PC<12:0> 1FFFh
CALL, RETURN
RETFIE, RETLW 13
FIGURE 4-3: PIC16C715 PROGRAM
MEMORY MAP AND STACK
Stack Level 1
PC<12:0>
CALL, RETURN
Stack Level 8 RETFIE, RETLW 13
Stack Level 1
Reset Vector 0000h
User Memory
Stack Level 8
Space
On-chip Program
Memory
07FFh
0800h
1FFFh
2Fh AFh
30h B0h
7Fh FFh
Bank 0 Bank 1
File File
File File Address Address
Address Address
00h INDF(1) INDF(1) 80h
00h INDF(1) INDF(1) 80h
01h TMR0 OPTION 81h
01h TMR0 OPTION 81h
02h PCL PCL 82h
02h PCL PCL 82h
03h STATUS STATUS 83h
03h STATUS STATUS 83h
04h FSR FSR 84h
04h FSR FSR 84h
05h PORTA TRISA 85h
05h PORTA TRISA 85h
06h PORTB TRISB 86h
06h PORTB TRISB 86h
07h 87h
07h PCON 87h
08h 88h
08h ADCON0 ADCON1 88h
09h 89h
09h ADRES ADRES 89h
0Ah PCLATH PCLATH 8Ah
0Ah PCLATH PCLATH 8Ah
0Bh INTCON INTCON 8Bh
0Bh INTCON INTCON 8Bh
0Ch PIR1 PIE1 8Ch
0Ch 8Ch
General 0Dh 8Dh
Purpose
General Register 0Eh PCON 8Eh
Purpose 0Fh 8Fh
Register Mapped 10h 90h
in Bank 0(2)
11h 91h
4Fh CFh 12h 92h
50h D0h 13h 93h
14h 94h
15h 95h
16h 96h
17h 97h
18h 98h
19h 99h
1Ah 9Ah
FFh 1Bh 9Bh
7Fh
1Ch 9Ch
Bank 0 Bank 1
1Dh 9Dh
1Eh ADRES 9Eh
Unimplemented data memory locations, read
as '0'.
1Fh ADCON0 ADCON1 9Fh
Note 1: Not a physical register. 20h A0h
2: These locations are unimplemented in Bank 1. General General
Any access to these locations will access the Purpose Purpose
corresponding Bank 0 register. Register Register
BFh
C0h
7Fh FFh
Bank 0 Bank 1
Bank 0
00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
02h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
04h(3) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — — PORTA Data Latch when written: PORTA pins when read ---x 0000 ---u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h — Unimplemented — —
08h ADCON0 ADCS1 ADCS0 (6) CHS1 CHS0 GO/DONE ADIF ADON 00-0 0000 00-0 0000
0Ah(2,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(3) INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Bank 1
80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
82h
(3) STATUS IRP(5) (5) RP0 TO PD Z DC C 0001 1xxx 000q quuu
83h RP1
(3) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
84h
85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111
86h TRISB PORTB Data Direction Control Register 1111 1111 1111 1111
(2,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Ah
(3) INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Bh
Bank 0
00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — — PORTA Data Latch when written: PORTA pins when read ---x 0000 ---u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
(1,2)
0Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Dh — Unimplemented — —
0Eh — Unimplemented — —
0Fh — Unimplemented — —
10h — Unimplemented — —
11h — Unimplemented — —
12h — Unimplemented — —
13h — Unimplemented — —
14h — Unimplemented — —
15h — Unimplemented — —
16h — Unimplemented — —
17h — Unimplemented — —
18h — Unimplemented — —
19h — Unimplemented — —
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Bank 1
80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(1) (4) (4)
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000
8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Dh — Unimplemented — —
8Eh PCON MPEEN — — — — PER POR BOR u--- -1qq u--- -1uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h — Unimplemented — —
93h — Unimplemented — —
94h — Unimplemented — —
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
Not
Data Used
Memory
05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111
9Fh ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
RD TRIS
Q D
RD Port EN
RB0/INT
RD Port EN RD Port EN Q1
Set RBIF Set RBIF
From other Q D Q D
RB7:RB4 pins From other
RB7:RB4 pins RD Port
EN EN
RD Port Q3
RB7:RB6 in serial programming mode RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS. Note 1: I/O pins have diode protection to VDD and VSS.
2: TRISB = ’1’ enables weak pull-up if 2: TRISB = ’1’ enables weak pull-up if
RBPU = ’0’ (OPTION<7>). RBPU = ’0’ (OPTION<7>).
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note:
PC PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB
Instruction followed by a read from PORTB.
fetched MOVWF PORTB MOVF PORTB,W
write to NOP NOP
PORTB Note that:
RB7:RB0 data setup time = (0.25TCY - TPD)
where TCY = instruction cycle
Port pin
sampled here TPD = propagation delay
TPD Therefore, at higher clock frequencies,
Instruction
executed NOP
a write followed by a read may be
MOVWF PORTB MOVF PORTB,W
write to problematic.
PORTB
Data bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0
clocks
RA4/T0CKI Programmable 0 PSout
pin Prescaler
T0SE (2 cycle delay)
3
Set interrupt
PS2, PS1, PS0 PSA flag bit T0IF
T0CS on overflow
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Executed
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3)
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC PC PC +1 PC +1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h)
Instruction Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h)
executed
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
External Clock Input or misses sampling
Prescaler output (2)
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
8
M 1
0
RA4/T0CKI U M
X SYNC
pin U 2 TMR0 reg
1 0
X Cycles
T0SE
T0CS
PSA Set flag bit T0IF
on Overflow
0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer
8 - to - 1MUX PS2:PS0
PSA
0 1
WDT Enable bit
MUX PSA
WDT
Time-out
CHS1:CHS0
11
RA3/AN3/VREF
VIN
(Input voltage) 10
RA2/AN2
01
A/D RA1/AN1
Converter
00
RA0/AN0
VDD
00 or
VREF 10 or
11
(Reference
voltage) 01
PCFG1:PCFG0
Rs = 10 kΩ 10.747 µs + 1.25 µs
VDD = 5V → Rss = 7 kΩ
Temp (application system max.) = 50°C
VHOLD = 0 @ t = 0
CHOLD
VA CPIN I leakage = DAC capacitance
5 pF VT = 0.6V ± 500 nA = 51.2 pF
VSS
(full scale)
255 LSb
256 LSb
0.5 LSb
1 LSb
2 LSb
3 LSb
4 LSb
Analog input voltage
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
A/D Clock
Yes Start of A/D SLEEP Yes Finish Conversion
Conversion Delayed Instruction? GO = 0
= RC? 1 Instruction Cycle ADIF = 1
No No
No No
Wait 2 TAD
0Bh,8Bh INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
08h ADCON0 ADCS1 ADCS0 — CHS1 CHS0 GO/DONE ADIF ADON 00-0 0000 00-0 0000
05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
1Fh ADCON ADCS ADCS CHS2 CHS1 CHS0 GO/ — ADON 0000 00-0 0000 00-0
0 1 0 DONE
9Fh ADCON — — — — — — PCFG1 PCFG0 ---- --00 ---- --00
1
05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
CP0 CP0 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
bit13 bit0 Address 2007h
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed.
CP1 CP0 CP1 CP0 CP1 CP0 MPEEN BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
bit13 bit0 Address 2007h
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
2.0 MHz Murata Erie CSA2.00MG ± 0.5% These values are for design guidance only. See
notes at bottom of page.
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
Crystals Used
8.0 MHz Murata Erie CSA8.00MT ± 0.5%
32 kHz Epson C-001R32.768K-A ± 20 PPM
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
200 kHz STD XTL 200.000KHz ± 20 PPM
All resonators used did not have built-in capacitors.
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Recommended values of C1 and C2 are identical to the ranges tested table.
2: Higher capacitance increases the stability of oscillator but also increases the start-up time.
3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal man-
ufacturer for appropriate values of external components.
4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level speci-
fication.
External
Reset
MCLR/VPP Pin
Program MPEEN
Memory
Parity(3)
WDT SLEEP
Module
WDT Time-out
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset(2) S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter R Q
OSC1/
CLKIN
Pin PWRT
On-chip(1)
RC OSC 10-bit Ripple-counter
Enable PWRT
See Table 8-6 for time-out situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: Brown-out Reset is implemented on the PIC16C710/711/715.
3: Parity Error Reset is implemented on the PIC16C715.
VDD
BVDD
Internal
72 ms
Reset
VDD
BVDD
Internal <72 ms
Reset 72 ms
VDD
BVDD
Internal
72 ms
Reset
On power-up the time-out sequence is as follows: First For the PIC16C715, bit2 is PER (Parity Error Reset). It
PWRT time-out is invoked after the POR time delay has is cleared on a Parity Error Reset and must be set by
expired. Then OST is activated. The total time-out will user software. It will also be set on a Power-on Reset.
vary based on oscillator configuration and the status of For the PIC16C715, bit7 is MPEEN (Memory Parity
the PWRT. For example, in RC mode with the PWRT Error Enable). This bit reflects the status of the MPEEN
disabled, there will be no time-out at all. Figure 8-11, bit in configuration word. It is unaffected by any reset of
Figure 8-12, and Figure 8-13 depict time-out interrupt.
sequences on power-up.
8.4.7 PARITY ERROR RESET (PER)
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then Applicable Devices 710 71 711 715
bringing MCLR high will begin execution immediately
(Figure 8-12). This is useful for testing purposes or to The PIC16C715 has on-chip parity bits that can be
synchronize more than one PIC16CXX device operat- used to verify the contents of program memory. Parity
ing in parallel. bits may be useful in applications in order to increase
Table 8-10 and Table 8-11 show the reset conditions for overall reliability of a system.
some special function registers, while Table 8-12 and There are two parity bits for each word of Program
Table 8-13 show the reset conditions for all the Memory. The parity bits are computed on alternating
registers. bits of the program word. One computation is per-
formed using even parity, the other using odd parity. As
8.4.6 POWER CONTROL/STATUS REGISTER a program executes, the parity is verified. The even par-
(PCON) ity bit is XOR’d with the even bits in the program mem-
ory word. The odd parity bit is negated and XOR’d with
Applicable Devices 710 71 711 715
the odd bits in the program memory word. When an
The Power Control/Status Register, PCON has up to error is detected, a reset is generated and the PER flag
two bits, depending upon the device. bit 2 in the PCON register is cleared (logic ‘0’). This indi-
cation can allow software to act on a failure. However,
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is there is no indication of the program memory location
unknown on a Power-on Reset. It must then be set by of the failure in Program Memory. This flag can only be
the user and checked on subsequent resets to see if bit set (logic ‘1’) by software.
BOR cleared, indicating a BOR occurred. The BOR bit
is a "Don’t Care" bit and is not necessarily predictable The parity array is user selectable during programming.
if the Brown-out Reset circuitry is disabled (by clearing Bit 7 of the configuration word located at address
bit BODEN in the Configuration Word). 2007h can be programmed (read as ‘0’) to disable par-
ity. If left unprogrammed (read as ‘1’), parity is enabled.
TO PD
1 1 Power-on Reset
0 x Illegal, TO is set on POR
x 0 Illegal, PD is set on POR
0 1 WDT Reset
0 0 WDT Wake-up
u u MCLR Reset during normal operation
1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 8-8: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C710/711
POR BOR TO PD
0 x 1 1 Power-on Reset
0 x 0 x Illegal, TO is set on POR
0 x x 0 Illegal, PD is set on POR
1 0 x x Brown-out Reset
1 1 0 1 WDT Reset
1 1 0 0 WDT Wake-up
1 1 u u MCLR Reset during normal operation
1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 8-9: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C715
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
D 10k MCLR
R
R1 40k
MCLR PIC16CXX
C PIC16CXX
VDD VDD
R1
Q1
MCLR
R2 40k
PIC16CXX
A global interrupt enable bit, GIE (INTCON<7>) 2. The program branches to the Interrupt
enables (if set) all un-masked interrupts or disables (if vector and executes the Interrupt Ser-
cleared) all interrupts. When bit GIE is enabled, and an vice Routine.
interrupt’s flag bit and mask bit are set, the interrupt will 3. The Interrupt Service Routine com-
vector immediately. Individual interrupts can be dis- pletes with the execution of the RET-
abled through their corresponding enable bits in vari- FIE instruction. This causes the GIE
ous registers. Individual interrupt bits are set bit to be set (enables interrupts), and
regardless of the status of the GIE bit. The GIE bit is the program returns to the instruction
cleared on reset. after the one which was meant to dis-
The “return from interrupt” instruction, RETFIE, exits able interrupts.
the interrupt routine as well as sets the GIE bit, which Perform the following to ensure that inter-
re-enables interrupts. rupts are globally disabled:
The RB0/INT pin interrupt, the RB port change inter- LOOP BCF INTCON, GIE ; Disable global
rupt and the TMR0 overflow interrupt flags are con- ; interrupt bit
tained in the INTCON register. BTFSC INTCON, GIE ; Global interrupt
; disabled?
The peripheral interrupt flags are contained in the spe- GOTO LOOP ; NO, try again
cial function registers PIR1 and PIR2. The correspond- : ; Yes, continue
ing interrupt enable bits are contained in special ; with program
function registers PIE1 and PIE2, and the peripheral ; flow
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
ADIF
ADIE
GIE
ADIF
ADIF
ADIE
GIE
External interrupt on RB0/INT pin is edge triggered: An overflow (FFh → 00h) in the TMR0 register will set
either rising if bit INTEDG (OPTION<6>) is set, or fall- flag bit T0IF (INTCON<2>). The interrupt can be
ing, if the INTEDG bit is clear. When a valid edge enabled/disabled by setting/clearing enable bit T0IE
appears on the RB0/INT pin, flag bit INTF (INTCON<5>). (Section 6.0)
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF 8.5.3 PORTB INTCON CHANGE
must be cleared in software in the interrupt service rou-
An input change on PORTB<7:4> sets flag bit RBIF
tine before re-enabling this interrupt. The INT interrupt
(INTCON<0>). The interrupt can be enabled/disabled
can wake-up the processor from SLEEP, if bit INTE was
by setting/clearing enable bit RBIE (INTCON<4>).
set prior to going into SLEEP. The status of global inter-
(Section 5.2)
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up. Note: For the PIC16C71
See Section 8.8 for details on SLEEP mode. if a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
CLKOUT 3
4
INT pin
1
1
INTF flag 5 Interrupt Latency 2
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC+1 PC+1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h)
The Watchdog Timer is as a free running on-chip RC The CLRWDT and SLEEP instructions clear the WDT and
oscillator which does not require any external compo- the postscaler, if assigned to the WDT, and prevent it
nents. This RC oscillator is separate from the RC oscil- from timing out and generating a device RESET condi-
lator of the OSC1/CLKIN pin. That means that the WDT tion.
will run, even if the clock on the OSC1/CLKIN and The TO bit in the STATUS register will be cleared upon
OSC2/CLKOUT pins of the device has been stopped, a Watchdog Timer time-out.
for example, by execution of a SLEEP instruction. Dur-
ing normal operation, a WDT time-out generates a 8.7.2 WDT PROGRAMMING CONSIDERATIONS
device RESET (Watchdog Timer Reset). If the device is
It should also be taken into account that under worst
in SLEEP mode, a WDT time-out causes the device to
case conditions (VDD = Min., Temperature = Max., and
wake-up and continue with normal operation (Watch-
max. WDT prescaler) it may take several seconds
dog Timer Wake-up). The WDT can be permanently
before a WDT time-out occurs.
disabled by clearing configuration bit WDTE
(Section 8.1). Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
8.7.1 WDT PERIOD the prescaler count will be cleared, but the
prescaler assignment is not changed.
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
0
M Postscaler
1 U
WDT Timer
X 8
8 - to - 1 MUX PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 6-6)
0 1
MUX PSA
WDT
Note: PSA and PS2:PS0 are bits in the OPTION register. Time-out
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 8-1, Figure 8-2 and Figure 8-3 for operation of these bits.
The following peripheral interrupts can wake the device To ensure that the WDT is cleared, a CLRWDT instruc-
from SLEEP: tion should be executed before a SLEEP instruction.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INT pin
INTF flag
(INTCON<1>) Interrupt Latency
(Note 2)
GIE bit Processor in
(INTCON<7>)
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction
fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
8.9 Program Verification/Code Protection The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low while raising the
If the code protection bit(s) have not been pro-
MCLR (VPP) pin from VIL to VIHH (see programming
grammed, the on-chip program memory can be read
specification). RB6 becomes the programming clock
out for verification purposes.
and RB7 becomes the programming data. Both RB6
Note: Microchip does not recommend code pro- and RB7 are Schmitt Trigger inputs in this mode.
tecting windowed devices. After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A 6-
8.10 ID Locations
bit command is then supplied to the device. Depending
Four memory locations (2000h - 2003h) are designated on the command, 14-bits of program data are then sup-
as ID locations where the user can store checksum or plied to or from the device, depending if the command
other code-identification numbers. These locations are was a load or a read. For complete details of serial pro-
not accessible during normal execution but are read- gramming, please refer to the PIC16C6X/7X Program-
able and writable during program/verify. It is recom- ming Specifications (Literature #DS30228).
mended that only the 4 least significant bits of the ID
location are used. FIGURE 8-23: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
8.11 In-Circuit Serial Programming CONNECTION
PIC16CXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is To Normal
simply done with two lines for clock and data, and three External Connections
other lines for power, ground, and the programming Connector PIC16CXX
voltage. This allows customers to manufacture boards Signals
with unprogrammed devices, and then program the +5V VDD
microcontroller just before shipping the product. This
0V VSS
also allows the most recent firmware or a custom firm-
VPP MCLR/VPP
ware to be programmed.
CLK RB6
VDD
To Normal
Connections
Description: The contents of the W register are Description: The contents of W register are
added to the eight bit literal 'k' and the AND’ed with the eight bit literal 'k'. The
result is placed in the W register. result is placed in the W register.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
literal 'k' data W literal "k" data W
Example CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter = 0x00
WDT prescaler= 0
TO = 1
PD = 1
Description: GOTO is an unconditional branch. The Description: The contents of register 'f' are incre-
eleven bit immediate value is loaded mented. If 'd' is 0 the result is placed
into PC bits <10:0>. The upper bits of in the W register. If 'd' is 1 the result is
PC are loaded from PCLATH<4:3>. placed back in register 'f'.
GOTO is a two cycle instruction.
Words: 1 Words: 1
Cycles: 2 Cycles: 1
MOVWF Move W to f
MOVF Move f
Syntax: [ label ] MOVWF f
Syntax: [ label ] MOVF f,d
Operands: 0 ≤ f ≤ 127
Operands: 0 ≤ f ≤ 127
d ∈ [0,1] Operation: (W) → (f)
Operation: (f) → (dest) Status Affected: None
Status Affected: Z Encoding: 00 0000 1fff ffff
Encoding: 00 1000 dfff ffff Description: Move data from W register to register
'f'.
Description: The contents of register f is moved to
a destination dependant upon the sta- Words: 1
tus of d. If d = 0, destination is W reg-
Cycles: 1
ister. If d = 1, the destination is file
register f itself. d = 1 is useful to test a Q Cycle Activity: Q1 Q2 Q3 Q4
file register since status flag Z is Decode Read Process Write
affected. register data register 'f'
'f'
Words: 1
Cycles: 1
Example MOVWF OPTION_REG
Q Cycle Activity: Q1 Q2 Q3 Q4
Before Instruction
Decode Read Process Write to OPTION = 0xFF
register data dest
W = 0x4F
'f'
After Instruction
OPTION = 0x4F
Example MOVF FSR, 0 W = 0x4F
After Instruction
W = value in FSR register
Z =1
Example RETFIE
After Interrupt
PC = TOS
GIE = 1
1st Cycle Decode Read NOP Write to 2nd Cycle NOP NOP NOP NOP
literal 'k' W, Pop
from the
Stack Example RETURN
2nd Cycle NOP NOP NOP NOP
After Interrupt
PC = TOS
Example CALL TABLE ;W contains table
;offset value
• ;W now has table value
•
•
TABLE ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RLF Rotate Left f through Carry RRF Rotate Right f through Carry
Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] d ∈ [0,1]
Operation: See description below Operation: See description below
Status Affected: C Status Affected: C
Encoding: 00 1101 dfff ffff Encoding: 00 1100 dfff ffff
Description: The contents of register 'f' are rotated Description: The contents of register 'f' are rotated
one bit to the left through the Carry one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is the W register. If 'd' is 1 the result is
stored back in register 'f'. placed back in register 'f'.
C Register f C Register f
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
register data dest register data dest
'f' 'f'
Before Instruction
W = 0xB5 Example XORWF REG 1
DS30272A-page 88
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KEELOQ
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VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
VDD BVDD
35
TABLE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 1 — — µs VDD = 5V, -40˚C to +125˚C
31 Twdt Watchdog Timer Time-out Period 7* 18 33* ms VDD = 5V, -40˚C to +125˚C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period
33 Tpwrt Power up Timer Period 28* 72 132* ms VDD = 5V, -40˚C to +125˚C
34 TIOZ I/O Hi-impedance from MCLR Low — — 1.1 µs
or Watchdog Timer Reset
35 TBOR Brown-out Reset pulse width 100 — — µs 3.8V ≤ VDD ≤ 4.2V
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
RA4/T0CKI
40 41
42
TMR0
A/D DATA 7 6 5 4 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
30
25
20
IPD(nA)
15
10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
85°C
70°C
1.000
IPD(µA)
0.100 25°C
0°C
-40°C
0.010
0.001
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
Fosc(MHz)
IPD(µA)
15
3.5
3.0
10 R = 10k
2.5
2.0
5
1.5
1.0
0 R = 100k
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5
VDD(Volts) 0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
25 2.2
R = 3.3k
2.0
IPD(µA)
20 1.8
70°C 1.6
Fosc(MHz)
15 R = 5k
1.4
85°C 1.2
10
1.0
R = 10k
5 0.8
0.6
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.4
R = 100k
VDD(Volts) 0.2
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
600
R = 5k
500
400
R = 10k
300
200
100 R = 100k
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
1200 30
1000
25
IPD(µA)
IPD(µA)
400 Device in 15
Brown-out
200 Reset 10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5
VDD(Volts)
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
The shaded region represents the built-in hysteresis of the VDD(Volts)
brown-out reset circuitry.
1400
1200 45
1000 40
IPD(µA)
Device NOT in 35
800 Brown-out Reset
30
600 Device in
25
IPD(µA)
Brown-out
400 Reset 20
200 15
4.3 10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5
VDD(Volts)
0
The shaded region represents the built-in hysteresis of the 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
brown-out reset circuitry. VDD(Volts)
2000
6.0V
1800 5.5V
5.0V
1600
4.5V
1400
4.0V
1200
IDD(µA)
3.5V
1000 3.0V
800
2.5V
600
400
200
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency(MHz)
Shaded area is
beyond recommended range
FIGURE 12-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C)
2000 6.0V
1800 5.5V
5.0V
1600
4.5V
1400
4.0V
1200
IDD(µA)
3.5V
1000 3.0V
800
2.5V
600
400
200
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency(MHz)
Shaded area is
beyond recommended range
1600
6.0V
1400 5.5V
5.0V
1200 4.5V
4.0V
1000
3.5V
IDD(µA)
3.0V
800
2.5V
600
400
200
0
0 200 400 600 800 1000 1200 1400 1600 1800
Shaded area is Frequency(kHz)
beyond recommended range
FIGURE 12-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO 85°C)
1600
6.0V
1400 5.5V
5.0V
1200 4.5V
4.0V
1000
3.5V
IDD(µA)
3.0V
800
2.5V
600
400
200
0
0 200 400 600 800 1000 1200 1400 1600 1800
Shaded area is Frequency(kHz)
beyond recommended range
1200
6.0V
5.5V
1000 5.0V
4.5V
4.0V
800
3.5V
3.0V
IDD(µA)
600
2.5V
400
200
0
0 100 200 300 400 500 600 700
Frequency(kHz)
FIGURE 12-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO 85°C)
1200
6.0V
5.5V
1000 5.0V
4.5V
4.0V
800
3.5V
3.0V
IDD(µA)
600
2.5V
400
200
0
0 100 200 300 400 500 600 700
Frequency(kHz)
gm(mA/V)
IDD(µA)
3.0V
300 2.0
0 0.0
20 pF 100 pF 300 pF 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Capacitance(pF) Shaded area is VDD(Volts)
beyond recommended range
TABLE 12-1: RC OSCILLATOR
FREQUENCIES FIGURE 12-20: TRANSCONDUCTANCE(gm)
OF LP OSCILLATOR vs. VDD
Average 110
Cext Rext
Fosc @ 5V, 25°C 100 Max -40°C
90
22 pF 5k 4.12 MHz ± 1.4% 80
10k 2.35 MHz ± 1.4% 70
gm(µA/V)
70
3.0
60
2.5
Startup Time(Seconds)
50
Startup Time(ms)
2.0
40
32 kHz, 33 pF/33 pF 200 kHz, 68 pF/68 pF
1.5 30
200 kHz, 47 pF/47 pF
20
1.0 1 MHz, 15 pF/15 pF
10 4 MHz, 15 pF/15 pF
0.5 200 kHz, 15 pF/15 pF
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0 VDD(Volts)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
1600 6.0V
120
1400 5.5V
100
5.0V
1200
80 4.5V
1000
IDD(µA)
4.0V
60
6.0V 3.5V
800
5.5V
IDD(µA)
40 5.0V 3.0V
4.5V 600
4.0V 2.5V
20 3.5V
3.0V 400
2.5V
0
0 50 100 150 200 200
Frequency(kHz)
0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Frequency(MHz)
FIGURE 12-26: MAXIMUM IDD vs. FIGURE 12-28: MAXIMUM IDD vs.
FREQUENCY FREQUENCY
(LP MODE, 85°C TO -40°C) (XT MODE, -40°C TO 85°C)
1800
6.0V
140 1600
5.5V
120 1400
5.0V
80 1000 4.0V
IDD(µA)
5.5V 3.0V
5.0V
40 4.5V 600 2.5V
4.0V
3.5V
20 3.0V
400
2.5V
0 200
0 50 100 150 200
Frequency(kHz) 0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Frequency(MHz)
4.0
IDD(mA)
3.0
3.0
2.0 6.0V
5.5V
5.0V 2.0 6.0V
1.0 4.5V 5.5V
4.0V 5.0V
1.0 4.5V
0.0 4.0V
1 2 4 6 8 10 12 14 16 18 20
0.0
Frequency(MHz) 1 2 4 6 8 10 12 14 16 18 20
Frequency(MHz)
TABLE 13-1:
PIC16C71X
Applicable Devices
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
710 71 711 715
OSC PIC16C715-04 PIC16C715-10 PIC16C715-20 PIC16LC715-04 PIC16C715/JW
VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 5.5V VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.0 mA typ. at 3.0V IDD: 5 mA max. at 5.5V
RC
IPD: 21 µA max. at 4V IPD: 1.5 µA typ. at 4V IPD: 1.5 µA typ. at 4V IPD: 0.9 µA typ. at 3V IPD: 21 µA max. at 4V
Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max.
VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 5.5V VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.0 mA typ. at 3.0V IDD: 5 mA max. at 5.5V
XT
IPD: 21 µA max. at 4V IPD: 1.5 µA typ. at 4V IPD: 1.5 µA typ. at 4V IPD: 0.9 µA typ. at 3V IPD: 21 µA max. at 4V
Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max.
VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V
HS Do not use in HS mode
IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 10 MHz max.
VDD: 4.0V to 5.5V VDD: 2.5V to 5.5V VDD: 2.5V to 5.5V
IDD: 52.5 µA typ. at 32 kHz, 4.0V IDD: 48 µA max. at 32 kHz, 3.0V IDD: 48 µA max. at 32 kHz, 3.0V
LP Do not use in LP mode Do not use in LP mode
IPD: 0.9 µA typ. at 4.0V IPD: 5.0 µA max. at 3.0V IPD: 5.0 µA max. at 3.0V
Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type
that ensures the specifications required.
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices 710 71 711 715
13.1 DC Characteristics: PIC16C715-04 (Commercial, Industrial, Extended)
PIC16C715-10 (Commercial, Industrial, Extended)
PIC16C715-20 (Commercial, Industrial, Extended))
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)
DC CHARACTERISTICS
-40˚C ≤ TA ≤ +85˚C (industrial)
-40˚C ≤ TA ≤ +125˚C (extended)
Param. Characteristic Sym Min Typ† Max Units Conditions
No.
D001 Supply Voltage VDD 4.0 - 5.5 V XT, RC and LP osc configuration
D001A 4.5 - 5.5 V HS osc configuration
D002* RAM Data Retention VDR - 1.5 - V Device in SLEEP mode
Voltage (Note 1)
D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details
ensure internal Power-
on Reset signal
D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details
internal Power-on Reset
signal
D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled
D010 Supply Current (Note 2) IDD - 2.7 5 mA XT, RC osc configuration (PIC16C715-04)
FOSC = 4 MHz, VDD = 5.5V (Note 4)
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout 32
OSC
Timeout
Internal
RESET
Parity
Error
Reset
36
Watchdog
Timer
RESET 34
31
34
I/O Pins
VDD BVDD
35
TABLE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 5V, -40˚C to +125˚C
31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40˚C to +125˚C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period
33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C
34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 µs
or Watchdog Timer Reset
35 TBOR Brown-out Reset pulse width 100 — — µs VDD ≤ BVDD (D005)
36 TPER Parity Error Reset — TBD — µs
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
RA4/T0CKI
40 41
42
TMR0
A/D DATA 7 6 5 4 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
30
25
20
IPD(nA)
15
10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
85°C
70°C
1.000
IPD(µA)
0.100 25°C
0°C
-40°C
0.010
Fosc(MHz)
IPD(µA)
15
3.5
3.0
10 R = 10k
2.5
2.0
5
1.5
1.0
0 R = 100k
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5
VDD(Volts) 0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Shaded area is beyond recommended range.
VDD(Volts)
FIGURE 14-4: MAXIMUM IPD vs. VDD (WDT Shaded area is beyond recommended range.
ENABLED, RC MODE)
FIGURE 14-6: TYPICAL RC OSCILLATOR
35 FREQUENCY vs. VDD
-40°C
Cext = 100 pF, T = 25°C
30 2.4
0°C
2.2
25 R = 3.3k
2.0
1.8
IPD(µA)
20
1.6
Fosc(MHz)
70°C R = 5k
15 1.4
1.2
85°C
10 1.0
R = 10k
0.8
5
0.6
0 0.4
R = 100k
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.2
VDD(Volts) 0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Shaded area is beyond recommended range.
VDD(Volts)
Shaded area is beyond recommended range.
600
R = 5k
500
400
R = 10k
300
200
100 R = 100k
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
1200 30
1000
25
IPD(µA)
IPD(µA)
Device in 15
400
Brown-out
200 Reset 10
0 5
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
This shaded region represents the built-in hysteresis of VDD(Volts)
the brown-out reset circuitry.
Shaded area is beyond recommended range.
Shaded area is beyond recommended range.
Device NOT in
Brown-out Reset 25
IPD(µA)
800
20
600 Device in
Brown-out 15
400 Reset
10
200 5
4.3
0 0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts) VDD(Volts)
This shaded region represents the built-in hysteresis of Shaded area is beyond recommended range.
the brown-out reset circuitry.
2000
1800 5.5V
5.0V
1600
4.5V
1400
4.0V
1200
IDD(µA)
3.5V
1000 3.0V
800
2.5V
600
400
200
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency(MHz)
Shaded area is
beyond recommended range
FIGURE 14-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C)
2000
1800 5.5V
5.0V
1600
4.5V
1400
4.0V
1200
IDD(µA)
3.5V
1000 3.0V
800
2.5V
600
400
200
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency(MHz)
Shaded area is
beyond recommended range
1600
1400 5.5V
5.0V
1200 4.5V
4.0V
1000
3.5V
IDD(µA)
3.0V
800
2.5V
600
400
200
0
0 200 400 600 800 1000 1200 1400 1600 1800
Shaded area is Frequency(kHz)
beyond recommended range
FIGURE 14-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO 85°C)
1600
1400 5.5V
5.0V
1200 4.5V
4.0V
1000
3.5V
IDD(µA)
3.0V
800
2.5V
600
400
200
0
0 200 400 600 800 1000 1200 1400 1600 1800
Shaded area is Frequency(kHz)
beyond recommended range
1200
5.5V
1000 5.0V
4.5V
4.0V
800
3.5V
3.0V
IDD(µA)
600
2.5V
400
200
0
0 100 200 300 400 500 600 700
Frequency(kHz)
FIGURE 14-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO 85°C)
1200
5.5V
1000 5.0V
4.5V
4.0V
800
3.5V
3.0V
IDD(µA)
600
2.5V
400
200
0
0 100 200 300 400 500 600 700
Frequency(kHz)
gm(mA/V)
IDD(µA)
3.0V
300 2.0
0 0.0
20 pF 100 pF 300 pF 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Capacitance(pF) VDD(Volts)
70
3.0
60
2.5
Startup Time(Seconds)
50
Startup Time(ms)
2.0
40
32 kHz, 33 pF/33 pF 200 kHz, 68 pF/68 pF
1.5 30
200 kHz, 47 pF/47 pF
20
1.0 1 MHz, 15 pF/15 pF
10 4 MHz, 15 pF/15 pF
0.5 200 kHz, 15 pF/15 pF
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0 VDD(Volts)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Shaded area is beyond recommended range.
VDD(Volts)
Shaded area is beyond recommended range. TABLE 14-2: CAPACITOR SELECTION
FOR CRYSTAL
FIGURE 14-23: TYPICAL XTAL STARTUP OSCILLATORS
TIME vs. VDD (HS MODE,
25°C) Crystal Cap. Range Cap. Range
Osc Type
Freq C1 C2
7 LP 32 kHz 33 pF 33 pF
6 200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
Startup Time(ms)
20 MHz, 33 pF/33 pF
5 1 MHz 15 pF 15 pF
4 4 MHz 15 pF 15 pF
8 MHz, 33 pF/33 pF HS 4 MHz 15 pF 15 pF
3 8 MHz 15-33 pF 15-33 pF
20 MHz, 15 pF/15 pF
8 MHz, 15 pF/15 pF 20 MHz 15-33 pF 15-33 pF
2
1 Crystals
4.0 4.5 5.0 5.5 6.0 Used
VDD(Volts)
32 kHz Epson C-001R32.768K-A ± 20 PPM
Shaded area is beyond recommended range. 200 kHz STD XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
1600
120
1400 5.5V
100
5.0V
1200
80 4.5V
1000
IDD(µA)
4.0V
60
800 3.5V
5.5V
IDD(µA)
40 5.0V 3.0V
4.5V 600
4.0V 2.5V
20 3.5V
3.0V 400
2.5V
0
0 50 100 150 200 200
Frequency(kHz)
0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Frequency(MHz)
FIGURE 14-26: MAXIMUM IDD vs. FIGURE 14-28: MAXIMUM IDD vs.
FREQUENCY FREQUENCY
(LP MODE, 85°C TO -40°C) (XT MODE, -40°C TO 85°C)
1800
140 1600
5.5V
120 1400
5.0V
80 1000 4.0V
IDD(µA)
60 800 3.5V
IDD(µA)
5.5V 3.0V
5.0V
40 4.5V 600 2.5V
4.0V
3.5V
20 3.0V
400
2.5V
0 200
0 50 100 150 200
Frequency(kHz) 0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Frequency(MHz)
4.0
IDD(mA)
3.0
3.0
2.0
5.5V
5.0V 2.0
1.0 4.5V 5.5V
4.0V 5.0V
1.0 4.5V
0.0 4.0V
1 2 4 6 8 10 12 14 16 18 20
0.0
Frequency(MHz) 1 2 4 6 8 10 12 14 16 18 20
Frequency(MHz)
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKOUT
15 pF for OSC2 output
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
11
10
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O Pins
TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 200 — — ns VDD = 5V, -40˚C to +85˚C
31 Twdt Watchdog Timer Time-out Period 7* 18 33* ms VDD = 5V, -40˚C to +85˚C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
33 Tpwrt Power-up Timer Period 28* 72 132* ms VDD = 5V, -40˚C to +85˚C
34 TIOZ I/O High Impedance from MCLR — — 100 ns
Low
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
RA4/T0CKI
40 41
42
TMR0
Note: Refer to Figure 15-1 for load conditions.
A/D DATA 7 6 5 4 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
The graphs and tables provided in this section are for R = 4.7k
4.5
design guidance and are not tested or guaranteed. In
some graphs or tables the data presented are out-
side specified operating range (e.g. outside speci- 4.0
fied VDD range). This is for information only and
devices are guaranteed to operate properly only 3.5
within the specified range.
3.0
Note: The data presented in this section is a sta-
tistical summary of data collected on units R = 10k
from different lots over a period of time and 2.5
matrix samples. 'Typical' represents the
Fosc (MHz)
mean of the distribution while 'max' or 'min' 2.0
represents (mean + 3σ) and (mean - 3σ)
respectively where σ is standard deviation. 1.5
Cext = 20 pF, T = 25°C
FIGURE 16-1: TYPICAL RC OSCILLATOR
1.0
FREQUENCY VS.
TEMPERATURE R = 100k
0.5
Fosc
Fosc (25°C)
Frequency Normalized to 25°C 0.0
1.050 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
1.025 Rext = 10k
Cext = 100 pF
1.000 FIGURE 16-3: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
0.975 VDD = 5.5V
2.0
0.950
R = 3.3k
0.925 VDD = 3.5V 1.8
0.900 1.6
0.875
1.4
0.850 R = 4.7k
0 10 20 30 40 50 60 70 1.2
T(°C)
1.0
Fosc (MHz)
0.8
R = 10k
0.6
0.2 R = 100k
0.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
14
FIGURE 16-5: TYPICAL IPD VS. VDD
WATCHDOG TIMER
DISABLED 25°C
12
0.6
10
0.5
IPD (µA)
0.4
6
IPD (µA)
0.3
4
0.2 2
0
0.1 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
0.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 16-7: MAXIMUM IPD VS. VDD FIGURE 16-8: MAXIMUM IPD VS. VDD
WATCHDOG DISABLED WATCHDOG ENABLED
45
25
-55°C
40 -40°C
125°C
35
20
30 125°C
25
15
IPD (µA)
20
IPD (µA)
0°C
15
70°C
Data based on matrix samples. See first page of this section for details.
10
85°C
10
85°C
70°C 5
5
0
0°C 3.0 3.5
4.0 4.5 5.0 5.5 6.0
-40°C VDD (Volts)
0 -55°C IPD, with Watchdog Timer enabled, has two components:
3.0 3.5 4.0 4.5 5.0 5.5 6.0 The leakage current which increases with higher tempera-
VDD (Volts) ture and the operating current of the Watchdog Timer logic
which increases with lower temperature. At -40°C, the latter
dominates explaining the apparently anomalous behavior.
FIGURE 16-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS VS. VDD
2.00
1.80
Max (-40˚C to 85˚C)
1.60
25˚C, TYP
1.40
VTH (Volts)
1.20
Min (-40˚C to 85˚C)
1.00
0.80
0.60
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
3.00
VIH, VIL (Volts)
2.50
2.00
0.00
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
Data based on matrix samples. See first page of this section for details.
FIGURE 16-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES)
VS. VDD
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
IDD (µA)
100
Data based on matrix samples. See first page of this section for details.
10
1
10,000 100,000 1,000,000 10,000,000 100,000,000
Frequency (Hz)
FIGURE 16-13: MAXIMUM, IDD VS. FREQ (EXT CLOCK, -40° TO +85°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
IDD (µA)
100
10
10,000 100,000 1,000,000 10,000,000 100,000,000
Frequency (Hz)
FIGURE 16-14: MAXIMUM IDD VS. FREQ WITH A/D OFF (EXT CLOCK, -55° TO +125°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
IDD (µA)
100
Data based on matrix samples. See first page of this section for details.
10
10,000 100,000 1,000,000 10,000,000 100,000,000
Frequency (Hz)
FIGURE 16-15: WDT TIMER TIME-OUT FIGURE 16-16: TRANSCONDUCTANCE (gm)
PERIOD VS. VDD OF HS OSCILLATOR VS. VDD
9000
50
8000
45
7000
40 Max, -40°C
6000
35
gm (µA/V)
Max, 70°C
30 4000
Typ, 25°C
25 3000
20 Min, 85°C
Typ, 25°C 2000
Min, 0°C
15 1000
10 0
Min, -40°C 2 3 4 5 6 7
VDD (Volts)
5
2 3 4 5 6 7
VDD (Volts)
225
200 -5
Max, -40°C Min, 85°C
175
150
-10
Typ, 25°C
IOH (mA)
gm (µA/V)
125
Typ, 25°C
100 Min, 85°C -15
75
Data based on matrix samples. See first page of this section for details.
50 Max, -40°C
-20
25
0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 -25
VDD (Volts) 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts)
FIGURE 16-18: TRANSCONDUCTANCE (gm) FIGURE 16-20: IOH VS. VOH, VDD = 5V
OF XT OSCILLATOR VS. VDD
0
2500
-5
Max, -40°C
-10
2000
-15
IOH (mA)
-25
Typ @ 25°C
-30
1000
-35
-40
Min, 85°C Max @ -40°C
500
-45
-50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0 VOH (Volts)
2 3 4 5 6 7
VDD (Volts)
Max @ -40°C
30 80
Max @ -40°C
70
25
60
Typ @ 25°C Typ @ 25°C
20
IOL (mA)
IOL (mA)
50
Min @ +85°C
15 Min @ +85°C 40
10 30
20
5
Data based on matrix samples. See first page of this section for details.
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL (Volts)
VOL (Volts)
α C
E1 E
eA
Pin No. 1 eB
Indicator
Area
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A3 A A2
B
D1
N
α
C
E1 E
eA
Pin No. 1 eB
Indicator
Area
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A2 A
B
D1
e
B
h x 45°
Index
Area
E H α C
Chamfer L
h x 45°
1 2 3
CP Base
Seating Plane
Plane
A1 A
N
Index
area
E H
α
C
L
1 2 3
e B
A Base plane
CP
Seating plane
D A1
Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per
side. D1 and E1 dimensions including mold mismatch.
2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m
(0.003”)max.
3: This outline conforms to JEDEC MS-026.
MMMMMMMMMMMMM PIC16C711-04/P
XXXXXXXXXXXXXXXX
AABBCDE 9452CBA
MMMMMM PIC16C71
XXXXXXXX /JW
AABBCDE 945/CBT
AABBCAE 9517SBP
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