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SPI Eases Interfacing For 5-By-5 Dot-Matrix Display: Do You Have An Idea For Design For
SPI Eases Interfacing For 5-By-5 Dot-Matrix Display: Do You Have An Idea For Design For
Do you have Electronic Design is always on the lookout for new ideas. Do
an Idea for you have one? Our Ideas for Design articles are short and to
Design for the point, often with a single figure or program listing to help
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for Design
Ideas
GIRISH CHOUDANKAR | EMPHATEC INC., MARKHAM, ONT., CANADA
data clock 3 5
row address decode
ELECTRONIC DESIGN
IdeasForDesign
1 0 1 0 0 0 0 0 A0 Character 0
1 0 1 0 0 0 0 1 A1 Character 1
1 0 1 0 0 0 1 0 A2 Character 2
1 0 1 0 0 0 1 1 A3 Character 3
0 0 0 C0 C1 C2 C3 C4 Character 0
0 0 1 C0 C1 C2 C3 C4 Character 1
0 1 0 C0 C1 C2 C3 C4 Character 2
0 1 1 C0 C1 C2 C3 C4 Character 3
1 1 1 1 0 0 0 1 F1 53%
1 1 1 1 1 1 1 1 FF 0% brightness
1 1 1 1 1 0 0 0 F8 Lamp test
1 1 0 0 0 0 0 0 C0 Clear
Load
Serial Clock
clock period
Data
(d)
IO
2. The bit-mapped characters supplied by the microcontroller occur within certain timing specifica-
tions. The times in this example are based on the use of a 5-MHz clock (a period of 200 ns).
display is blanked and the character reg- project I opted for the SPI hardware
ister address is set to character 0. The instantiation to reduce firmware over-
internal counter and control word regis- head. This choice also ensures the clock
ter are unaffected. is stable and isn’t influenced by other
The example circuit uses a Cypress priority events.
CY8C27443-24PXI programmable Instantiating SPI simplified the dis-
system-on-chip (PSoC) and a program play’s communication block. Below is
written in C. I chose the PSoC because the flow chart for firmware implementa-
it enables designers to select individual tion. (The code for the demo project can
hardware blocks. The serial interface to be downloaded from the online version
the display is straightforward and easy. of this article at electronicdesign.com.)
There are two ways to interface the
display. The first is to connect a micro- • Power up the display.
controller via the serial port in mode 0. • Bring Reset low (for at least 600 ns)
The serial port control register will be a to clear the multiplex counter, address
simple shift register. Serial data enters register, control word register, user
and exits through the RXD pin, and the RAM, and data register. The display
TXD pin outputs the clock. will be blank. The display brightness
The second method interfaces the dis- will be set to 100%.
play via the SPI in mode 0. Besides MISO • If different brightness is desired, load
(master in slave out) and clock, the dis- the proper display brightness control
play needs Reset and Load control lines. word from Table 4.
I chose SPI for this project because of its • Load the character address into the dis-
inherent advantages over serial port (Fig. play (Table 1).
3). The circuit uses a MAX1232 as a reset • Load column data into the display
controller, but you can choose any other (Table 2).
method for properly resetting the micro- • Repeat steps 4 and 5 for rest of the digits.
controller.
As noted, the PSoC enables you to Finally, one display CLK_I/O line
choose your own hardware modules, can drive 15 slave CLK_I/O lines, so
which speeds development. For this you can cascade displays to increase the
ElEctronic DEsign
IdeasForDesign
C1 +5 V +5 V
1 μF 16 V
1 14
SDCLK
____ SDCLK
____ Gnd
+ C2 2 Data 13
1 P1A Load Load Data
100 nF 3 VCC 12
50 V X
4 DS1 11
X SCDV5542 VCC
5 VCC 10
28 X
____ _______
6 9 + C3
1 VCC 27 RST CLKSEL 22 μF
P0[7] P0[6] 7 8 C4
2 26 Gnd CLK_I/O 35 V
10 nF
P0[5] P0[4]
3 25 50 V
P0[3] P0[2]
4 24
___ P0[1] P0[0]
5 23
Reset P2[7] P2[6] SDCCLK
____ 6 22
Load P2[5] U1 P2[4] Data
7 21
P2[3] CY8C27443 P2[2]
8 20 C5
P2[1] P2[0]
9 19 2 P1B +5 V 100 nF
SMP XRES 50 V
10 18
P1[7] P1[6] R1
11 17
P1[5] P1[4] 100k 3
12 16 1% P1C ___
P1[3] P1[2] VCC 1
P2D 4 15 5 P1E PB
13
P1[1] P1[0] 6 ____
VSS RST 2
P1F U2 TD
3
14 6 5 RST MAX1232 TOL
7 P1G ___ 7
ST
Gnd P2D
4
3. The author opted to use a SPI instantiation for the display because it reduced the firmware over-
head required.
___
RST
VCC
Data
SDCLK
0
A0
A1 Address Address decode 1-14
decoder
A2
15
A3
__ __
LD CE
4. The display’s CLK_I/O line can drive up to 15 slave CLK_I/O lines, so designers can easily cascade
multiple units.