IETE Journal of Research

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Design and Analysis of 2.4 GHz Low-Noise, High-

Gain 0.18 µm CMOS Cascode Low-Noise Amplifier
for IRNSS Applications

D. Jahnavi , G. Kavya & Anjana Jyothi Banu

To cite this article: D. Jahnavi , G. Kavya & Anjana Jyothi Banu (2020): Design and Analysis
of 2.4 GHz Low-Noise, High-Gain 0.18 µm CMOS Cascode Low-Noise Amplifier for IRNSS
Applications, IETE Journal of Research, DOI: 10.1080/03772063.2020.1782783

To link to this article: https://doi.org/10.1080/03772063.2020.1782783

Published online: 30 Jun 2020.

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IETE JOURNAL OF RESEARCH
https://doi.org/10.1080/03772063.2020.1782783

Design and Analysis of 2.4 GHz Low-Noise, High-Gain 0.18 µm CMOS Cascode
Low-Noise Amplifier for IRNSS Applications
D. Jahnavi 1,2 , G. Kavya 2 and Anjana Jyothi Banu 2

1 Information and Communication Engineering, Anna University, Chennai, India; 2 Department of Electronics and Communication Engineering,
S.A.Engineering College, Anna University, Chennai, India

ABSTRACT KEYWORDS
Low-Noise Amplifier (LNA) plays a crucial part in Radio Frequency (RF) front-end architecture. This ADS; generic PDK; IRNSS; LC
paper mainly focuses on designing LNA for Indian Regional Navigation Satellite System (IRNSS) network; Low-noise
receiver. IRNSS operates on two frequency bands (L5 and S band) and this design is proposed for S amplifier; RF CMOS
band with the center frequency of 2492.028 MHz. Cascode topologies are considered to be conven-
tional ones and they provide higher gain and better reverse isolation. Four different approaches of
single-stage cascode topology, such as Common Source (CS) cascode, Common Gate (CG) cascode,
shunt-resistive feedback cascode and current reuse cascode, were designed and their performance
metrics, based on gain, Noise Figure (NF), return losses and stability, are presented. Focused on the
gain and noise figure improvements, Common Source (CS) cascode with interstage series LC circuit
LNA was designed and optimized with input and output matching circuitries. The proposed opti-
mized circuit uses current reuse technique along with CS stage to improve the power gain and to
achieve low-noise figure. The interstage LC circuit is mainly implemented to act as a tuning circuit to
achieve a narrow range of frequency. The proposed work is simulated using 180 nm CMOS technol-
ogy Generic Process Design Kit (GPDK) and achieve a power gain (S21) of 24.89, 0.994 dB NF, −16.2 dB
input return loss (S11) and −11.06 dB output return loss (S22), with higher reverse isolation around
−30.47 dB at 1.8 V power supply.

1. INTRODUCTION center frequency of 2492.08 MHz. The performance

In recent technologies the evolvement of smaller and
more power-sensitive wireless devices has increased the
eruptive advancement of RF components. Apparently,
the growth of wireless devices quickens the develop-
ment of Low-Noise Amplifier in RF front end. Low-Noise
Amplifiers are considered to be an important element for
receiver sensitivity as they are placed at the first stage of
receiver to amplify weak signals coming from antenna.
Noise performance and power gain are the most impor-
tant parameters considered for the functioning of LNA.
However, achieving maximum power gain with mini-
mum noise figure simultaneously is a very tedious pro-
cess. Fortunately in the CMOS technology simultaneous
noise and power matching become possible.
IRNSS is an autonomous, indigenously developed satel-
lite navigation system which operates in two bands
(L5 and S) with the center frequency of 1176.45 and
2492.08 MHz, respectively. This work mainly concen-
trates on designing narrow band LNA for IRNSS (NavIC)
receiver at S band frequency. It operates between
2483.778 and 2500.27 MHz (16.5 MHz BW) with the
parameters required for LNA in this band should work
with gain value greater than 20 dB with low-noise figure.
Because of the smaller available bandwidth the design
has various constraints to achieve higher gain with better
stability and linearity.
Various works have been carried out on designing LNA’s
in narrow band frequency in 180 nm CMOS technology,
but each topology has certain pitfalls which affect the
LNA performance. Comparison of various topologies,
such as resistor terminated, resistive feedback, current
reuse, common gate, source inductive degenerated, [1]
has been done. Dual CS transistors with inductive degen-
eration improve gain by 10% [2] but lack in gain flatness
in a wideband range. Common Gate topology provides
flat gain [3,4] with better linearity but high noise figure,
similarly current reuse improves the linearity of the cir-
cuit with low noise figure [5,6] but lack in stability issues.
Dual band circuits are implemented [7–9] which use two
stage circuits combining two different topologies by con-
sidering their prevalence and achieving the desired LNA
parameters.

© 2020 IETE
2 D. JAHNAVI ET AL.: DESIGN AND ANALYSIS OF 2.4 GHZ LOW NOISE, HIGH GAIN 0.18 μM CMOS CASCODE LOW NOISE AMPLIFIER
Hence, this paper mainly targets designing single-stage
single-band LNA with low-noise figure and high gain
which remains a drawback in previous works as noise
figure obtained is greater than 2 dB. In continuation with
this, implementation of four different cascode topolo-
gies for 2.492 GHz center frequency with 180 nm RF
CMOS technology in ADS Software has been carried
out. Based on the performance of these LNAs, a novel
circuit has been designed using cadence virtuoso which
provides best results in gain, noise figure and better sta-
bility. Reduction in noise figure with better gain is mainly
achieved by using current reuse technique along with
interstage LC circuit and optimum impedance matching
networks. This technique improves the input impedance
as well as reducing noise at the input stage. Layout Extrac-
tion and post layout simulation have been carried out for
the proposed design using cadence.
The framework of this paper is as follows: Section 2 deals
with the basic LNA topologies and provides the benefit of
four different cascode topologies. Section 3 deals with the
design of the proposed system and its analysis. Section
4 discusses the simulated results with the performance
metrics and Section 5 provides the conclusion.
2. LNA TOPOLOGIES
Low-Noise Amplifier has an utmost importance in radio
receiver circuits. As an integral part in receiver LNA
must provide high-gain, low-noise figure, better input
and output matching with good linearity. The basic three
topologies, as shown in Figure 1, provide proper device
configuration.
Common Source (CS) topology in Figure 1(a) provides
low-noise figure, but with a cost of greater sensitivity
towards process variation, temperature and power sup-
ply. This topology has a stability issue as it often requires
compensation. The Common Gate (CG) topology is
mainly designed for better input impedance matching,
Figure 1: (a) Basic common source, (b) common gate, (c) cascode
topology [25]
Figure 2: Inductive source degeneration technique
as shown in Figure 1(b). This design provides low-noise
figure at low frequencies, but it gets higher at high fre-
quencies which turn to be a drawback. The third and
most widely used cascode topology is given in Figure 1(c)
which is an excellent tradeoff among all the three designs
as it provides highest voltage gain with better reverse iso-
lation factor. The sensitivity toward external aspects is
very much lesser than those of CS and CG circuits.
2.1 Inductive Degeneration Technique
Adding of inductor as a passive component is mainly
employed for providing desired impedance at a spe-
cific frequency and it also doesn’t affect the bias condi-
tion. Here this technique is mainly engrossed to improve
amplifier linearity. Inductor added at the source (Ls ), as
shown in Figure 2, is essentially used for improving gain
and provides stated input impedance without lowering
the noise performance of the circuit. [10]. Here in spite of
its numerous merits, this technique shows certain draw-
backs, as the name suggests it is negative feedback [11]
which reduces the gain of the amplifier and in order to
improve the gain, high DC current has to be applied.
In trade-off with merits and demerits, high linearity and
better matching led to the usage of this technique to a
greater extent.
gm LS
RS {Zin } = = wT LS (1)
Cgs
The input impedance Zin is calculated as given in
Equation (1) [10]; this indicates that the reactive feedback
from the inductor produces real impedance that simpli-
fies matching. The inductor value can be calculated as
LS = wRTS and if Ls is impractical, then wT can be reduced
by increasing the shunt Cgs value.
2.2 Cascode Inductive Degeneration Topology
The basic cascode topology, shown in Figure 3, is
designed by cascading common source and common gate
devices. The cascode device is a unilateral circuit essen-
tially used for improving the stability of the amplifier.
Cascode configuration of CMOS LNA endorse better
 D. JAHNAVI ET AL.: DESIGN AND ANALYSIS OF 2.4 GHZ LOW NOISE, HIGH GAIN 0.18 μM CMOS CASCODE LOW NOISE AMPLIFIER 3

In order to generate 50 input impedance from Equation

g L
(3) the real impedance value Cm1gs1S is considered. Equa-
tions (3)–(5) determine the input impedance (Zin ) calcu-
lation, voltage gain (Av ) and output resistance (R0 ) values
of the cascode amplifier, respectively.

The voltage gain (Av ) of cascode structure is given as

(Av ) = −Gm R0 where Gm depicts the overall transcon-
ductance and R0 is the output resistance [12]. Assuming
gm ro  1 then R0 = gm2 ro2 ro1 and both the transistors
in Figure 3 operate at saturation, then Gm = −gm1 . Thus
finally the voltage gain (Av ) is obtained, as given in
Equation (5).

2.3 Cascode Topologies

Figure 3: Cascode inductive degeneration topology Four conventional cascode designs are proposed for S
band with 2.492 GHz center frequency using 180 nm RF
CMOS technology.

2.3.1 Conventional (CS) Cascode Topology

The most widely used common source cascode topology
[22] is depicted in Figure 5 that has two transistors M1
and M2, where M1 is responsible for input impedance
matching and M2 avoids distortion caused by M1 tran-
sistor. The purpose of Lg1 and Lg2 is to tune the resonant
frequency of the circuit to the operating frequency. This
topology operates with very low supply voltages. Induc-
tor Ld resonates with total capacitance at the output node
Figure 4: Equivalent circuit of cascode inductive degeneration incurring a very high operating frequency. The degen-
topology eration Ls customizes gain for better linearity. Figure 6
depicts the performance metrics of CS cascode LNA;
input return loss (S11) and output return loss (S22) are
scope to provide concurrently high gain, improves reli-
−19 and −11 dB with 18.2 dB forward gain (S21) along
ability and wide frequency range with reasonable noise
with 1.2 dB noise figure and 1.32 stability factor (K). This
figure.
LNA provides IIP3 value around −4.77 dBm.
The noise contribution from the cascode is very small due
2.3.2 Common Gate (CG) Cascode Topology
to the degeneration technique which is used in the design.
Common gate cascode configuration is widely used in
The small signal equivalent circuit for Figure 4 is shown
wireless communications [22]. It is highly recommended
which is used to calculate gain and impedance.
for input impedance matching but with a cost of higher
1 noise figure. The CG cascode stage achieves a better
Vgs = iz ∗ (2) reverse isolation as it doesn’t suffer from miller effect.
jwCgs
As shown in Figure 7, RF input signal is injected at
  the source node of the M1 transistor and desired input
gm1 LS 1 impedance is achieved by fine-tuning the bias voltage at
Zin = + j w(Lg + LS ) − (3)
Cgs1 wCgs1 the CG input. Transistor M1 is responsible for balancing
the noise and parasitic capacitance Cgs , thus improving
|Av | = VV0i = (gm2 ro2 ro1 ) ∗ gm1 the impedance matching results. Transistor M2 acts as an
(4) isolation between input and output [3]. M2 also helps in
= gm1 ro1 gm2 ro2
determining the LNA noise performance. The size of M2
transistor is considered half of M1 transistor. Axiomat-
R0 = ro1 + ro2 + gm2 ro1 ro2 (5) ically, better noise performance is achieved by inductor
4 D. JAHNAVI ET AL.: DESIGN AND ANALYSIS OF 2.4 GHZ LOW NOISE, HIGH GAIN 0.18 μM CMOS CASCODE LOW NOISE AMPLIFIER
Figure 5: Conventional CS cascode topology
Figure 6: Output results of CS cascode LNA
Figure 7: Common Gate Cascode Topology
Ls as it acts as a parallel resonator with the parasitic
capacitance at the source node of the M1 transistor. Here
this proposed work has low-voltage gain and larger noise
figure.
The performance metrics of CG cascode LNA is shown
in Figure 8 with forward gain (S21) 14.633 dB which is
Figure 8: Output of CG Cascode LNA
quite lesser than CS cascode stage and this LNA provides
higher noise figure around 2.884 dB. But this topology
has a signature merit of 4.321 stability factor (K) which is
4 times greater than CS cascode and has higher stability
than the other topologies. The linearity IIP3 (third-order
Intercept point) value is −7.011 dBm for this design. The
input and output return losses, S11 and S22, are −13.8
and −12.5 dB, respectively.
2.3.3 Shunt Resistive Feedback Cascode Topology
The next cascode design approach is resistive parallel
feedback topology [22] which is mainly intended to over-
come the drawbacks of CS and CG cascode configura-
tion. As this topology remains to be CS cascode with
shunt feedback, this design provides certain merits and
demerits when compared with conventional CS cascode
topology. This method provides higher stability and bet-
ter output return loss but with a cost of higher noise
figure. It achieves a moderate voltage gain, lesser than
CS Cascode but with good wideband matching. However,
the trade-off is the noise figure and large power dissipa-
tion due to the additional feedback resistor Rf. As shown
in Figure 9 the Rf resistor is determined as the feedback
resistance to achieve a wider bandwidth of 2–4 GHz and
Cf capacitor is mainly used for the ac coupling principle.
This approach provides voltage gain greater than CG cas-
code stage but tends to suffer with very high NF and poor
linearity.
Shunt resistive feedback topology provides higher noise
figure of 3.293 dB with a forward gain (S21) around
16.540 dB, as shown in Figure 10. This topology provides
more noise figure than the rest of the topologies; the input
and output return losses are −12 and −15.9 dB, respec-
tively, with a better stability of 2.454 (K). The linearity
(IIP3) is −5.234 dBm. As this circuit depicts a higher
noise figure for the given center frequency (2.492 GHz),
it is not considered further for this application.
2.3.4 Current Reuse Cascode Topology
The last approach in this paper is current reuse cascode
topology. This design achieves more power gain and
 D. JAHNAVI ET AL.: DESIGN AND ANALYSIS OF 2.4 GHZ LOW NOISE, HIGH GAIN 0.18 μM CMOS CASCODE LOW NOISE AMPLIFIER
Figure 9: Shunt resistive feedback cascode topology
Figure 10: Output of Shunt Resistive Feedback Cascode LNA
improved noise figure than the resistive feedback ampli-
fier circuit. As shown in Figure 11 this topology design
is proposed to increase amplifier transconductance (gm)
without any change in power dissipation [12,13] which
seems to be a drawback in parallel feedback technique.
This topology boosts the transconductance (gm) in order
to minimize the MOSFET noise and improves the overall
gm by reusing the current [13,14]. M3 transistor, which is
coupled to M1 transistor, is also connected to the drain of
the M2 to improve the gate to source voltage at M2, thus
increasing the voltage gain [5,15].
Current reuse topology reuses the same DC bias cur-
rent thereby reducing the power dissipation. Simulation
results achieved by this topology are shown in Figure 12
which shows S11, S21, S22, NF, K and IIP3 as −13,
18.5, −14, 1.259 dB, 1.869 and −4.975 dBm, respectively.
High-gain and low-noise figure are achieved simultane-
ously to a greater extent. Hence, current reuse technique
along with CS cascode topology is considered further for
the IRNSS application in the S band frequency.
5
Figure 11: Current reuse cascode topology
Figure 12: Output of current reuse cascode LNA
The performances of all the aforementioned cascode
LNAs, designed using 0.18um CMOS technology and
simulated through ADS at 2.49 GHz center frequency, are
summarized in Table 1.
Table 1 discusses about the performance metrics of four
topologies designed using ADS. From Table 1, CS cas-
code and current reuse topology remain to be powerful
as they provide high-gain and low-noise figure with bet-
ter stability. CG cascode provides higher stability with a
demerit of higher noise figure. Shunt resistive feedback
cascode provides higher stability than conventional CS
cascode but with poor NF and minimum input return
loss which turns to be its drawback.
3. PROPOSED SERIES LC INTERSTAGE CASCODE
LNA
The proposed LNA is designed at 2.492 GHz centre fre-
quency for IRNSS applications. The circuit is designed for
the specifications mentioned for IRNSS receiver in the
S band Frequency [16] given in Table 2. The Proposed
Series LC interstage cascode LNA has been implemented
6 D. JAHNAVI ET AL.: DESIGN AND ANALYSIS OF 2.4 GHZ LOW NOISE, HIGH GAIN 0.18 μM CMOS CASCODE LOW NOISE AMPLIFIER

Table 1: Comparison of performance metrics of various topologies

Common Source Shunt Resistive Current Reuse
Parameters Cascode Common Gate Feedback Cascode Cascode
S11 (dB) −19.167 −13.813 −12.138 −13.252
S12 (dB) −26.185 −34.223 −30.821 −30.130
S21 (dB) 18.242 14.633 16.540 18.501
S22(dB) −11.129 −12.543 −15.989 −14.188
NF (dB) 1.216 2.884 3.293 1.259
Kf 1.325 4.321 2.454 1.869
Power Consumption (mW) 4.234 9.15 6.4 4.1

Table 2: Basic design specifications biasing resistor which is chosen large enough to ignore its
Parameters Values equivalent noise current [15]. Rb , Rg and M3 remain the
Frequency 2.492 GHz biasing circuit for the proposed LNA. The current reuse
Power Supply 1.8V technique consists of M3 transistor which is coupled to
Source Resistance 50
Forward Gain(S21) > 20 dB gate of M1 transistor improves the gate source voltage
Noise Figure (NF) < 2 dB (vgs ) of M1 leading to the increase in voltage gain of the
Input Return Loss (S11) < −14 dB
Output Return Loss (S22) < −10 dB transistor [5].

IRNSS receiver operates between 2483.778 and 2500.278

along with LC–tuned circuit at input matching network,
as shown in Figure 13. The main target of this work is to
improve the gain of the circuit with low NF. MOS tran-
sistor normally provides poor transconductance (gm) at
high frequencies, which results in gain drop. Hence, in
this proposed design, current reuse technique is implied
to improve the gain. Transistor M1 is cascaded with M2
transistor which forms a cascode structure. This cascode
topology mainly integrates good noise performance of CS
stage with excellent reverse isolation. M3 transistor forms
a current mirror with M1 transistor, where the width of
the former is determined by 1/10th of the latter’s width
for acquiring low power consumption. The Rb resistor
acts as the current limiter and Rg is considered to be the
MHz with 16 MHz bandwidth in the S Band frequency.
CS cascode along with interstage LC circuit is well suited
for this high-frequency range. The interstage LC net-
works are mainly implemented for better matching band-
width. LC resonant circuit is added at the input stage
to improve the LNA performance without degrading the
noise value and further improving the input impedance
of the circuit [24.] The resonant circuit is implemented
to achieve optimum results at desired frequency; it is
√
determined by w0 = 1/ LC where w0 is the resonant
frequency of the tuned circuit. A blocking capacitor Cb is
added at the input of the circuit to avoid distortion of sig-
nal at required frequency and also added to avoid disrup-
tive changes in vgs of M1 transistor. The output matching

Figure 13: Proposed series LC interstage cascode LNA

 D. JAHNAVI ET AL.: DESIGN AND ANALYSIS OF 2.4 GHZ LOW NOISE, HIGH GAIN 0.18 μM CMOS CASCODE LOW NOISE AMPLIFIER 7

Table 3: Component values for the proposed LNA 3.2 Noise Figure Analysis
Transistors Inductance Capacitance Resistance
W(μm) / L(μm) (nH) (pF) (Ohms) The noise performance of an RF amplifier is determined
M1 300/0.18 Li 2.29 nH Cb 5 pF Rg 5 k by its noise figure. NF is described as
M2 544/0.18 L1 4.79 nH C1 200fF Rb 200 
M3 30/0.18 Lg 6.9 nH Ci 0.5pF R1 1 k Total Noise power at output
Ls 1.1 nH C3 0.5pF Noise Figure =
Ld 3.89 nH C4 5pF
Noise power at output due to input source
Here two noise sources are mainly available in MOS cir-
cuits: noise due to resistors and noise due to transistors
(MOSFET channel noise). Noise source due to resistors
can be defined in Equation (8) as [15]

en 2 = 4KTδRf (8)

and noise due to MOS devices in Equation (9) is given as

[17,10]

in 2 = 4KTγ gm f (9)

where K is Boltzmann’s constant; δ and γ are the noise

Figure 14: Small signal analysis of the proposed LNA
network consists of T matching components with capac-
itors C3 and C4 which improves the output impedance
without degrading the power gain of the circuit.
The component values used in the circuit are given
in Table 3. The overall architecture improves the gain
of the circuit without degrading the noise figure and
thus providing excellent stability in the given band-
width. The small signal equivalent circuit is shown in
Figure 14 which is used to calculate gain, noise figure and
impedance calculation for the proposed design.
parameters of resistor and MOSFET, respectively; f =
Bandwidth and gm is the transconductance. There-
fore, the noise sources in this circuit are caused due to
Rb, Rg, R1 resistors and M1, M2 and M3 transistors,
respectively. It can be framed asen,out 2 , Rb = 4KTδRb f ;
en,out 2 , Rg = 4KTδRb f ; en,out 2 , R1 = 4KTδR1 f and
in,out 2 , M1 = 4KTγ gm1 f ; in,out 2 , M2 = 4KTγ gm2 f ;
in,out 2 , M3 = 4KTγ gm3 f and en,in 2 .Rs the noise from
the source [23]. Basically minimum noise figure with
power constraints [15] can be expressed as given in
Equation (10).
γ   w 
Fmin = [1 + 2.4 ] (10)
α wT
The noise factor thus calculated as shown in equation 11

3.1 Gain Analysis en,out 2 , Rb + en,out 2 , Rg + en,out 2 , R1 +

in,out 2 , M1 + in,out 2 , M2 + in,out 2 , M3
The gain of the proposed LNA is determined using the F = Fmin +
small signal equivalent circuit, as depicted in Figure 14. (en,in 2 .Rs )∗ Gain2
Generally the power gain is expressed as [11] (11)

Power delivered to Load

Power Gain = 3.3 Impedance Matching Analysis
Power delivered to the amplifier (6)
[1−(L )2 ](S21 )2
= [1−S22 (L )2 ][1−(L )2 ]
Impedance matching is an essential aspect to be con-
sidered while designing amplifier circuits [23]. For the
Gain analysis as shown in Equation (7) [12] of the pro- maximum power transfer the source and load impedance
posed LNA is determined using the small signal equiva- must be a conjugate match. In order to achieve superla-
lent circuit, as shown in Figure 13. tive results the input and output impedance of the device
must be matched and here in this paper an optimum
Gain = Gm1 Gm2 RL (7) impedance matching technique is employed to provide
greater results. Narrow band matching is achieved by
where Gm1 = Qin gm1 and Gm2 = Qin gm2 and Qin is adding tuned LC components; these matching circuits are
the quality factor of RLC circuit defined as Qin = implemented as they are more practical in the frequencies
wo L 1
R = wo RC between 30 and 300 MHz.
8 D. JAHNAVI ET AL.: DESIGN AND ANALYSIS OF 2.4 GHZ LOW NOISE, HIGH GAIN 0.18 μM CMOS CASCODE LOW NOISE AMPLIFIER

where
gm3 1
Zin1 = Rb + + Rg + jwLi + + jw(Lg + Ls )
cgs3 jwCi
gm1 Ls 1
+ + (13)
cgs1 jwCgs1

Figure 15: Equivalent Circuit of the LC-Tuned circuit [18]

Similarly the output impedance of the proposed design
can be expressed using equations 14 and 15.
1 1
Zout = + R1 + + Zout1 (14)
jwC3 jwC4

gm2 1
Zout1 = jwLd + + (15)
cgs2 jwCgs2

3.4 Layout Design

The fulfillment of a particular design can be determined
only after considering its layout design. The proposed
system has been designed in its layout using 180 nm
CMOS GPDKs. This provides the exact realization of
the designed LNA circuit. Here the proposed LNA is
Figure 16: Layout of the proposed series LC interstage cascode designed in cadence virtuoso and Spectre RF is used
LNA for the simulation. After performing simulation and
determining its parameters, the layout of the circuit is
The input matching circuit as shown in Figure 13 con- extracted, as shown in Figure 16. Further DRC, LVS and
sists of a biasing capacitor (Cb ) and tuned LC circuit. The parasitic extraction has been carried out using cadence
equivalent circuit of the parallel LC network is shown in assura and later post layout simulation has been per-
Figure 15. formed. This proposed LNA consumes 5.6 mW power
and occupies a silicon area of 0.55 mm2.
The input impedance of the proposed circuit can be
expressed as given in equations 12 and 13. 4. RESULTS AND DISCUSSION
1 The proposed single-stage S band LNA has been designed
ZIN = + jwL1g + R1g + Zin1 (12)
jwCb using Cadence Virtuoso and simulated using Spectre RF.

Figure 17: Performance metrics of the proposed LNA

 D. JAHNAVI ET AL.: DESIGN AND ANALYSIS OF 2.4 GHZ LOW NOISE, HIGH GAIN 0.18 μM CMOS CASCODE LOW NOISE AMPLIFIER 9

Technology
Table 4: Parameter analysis of the proposed LNA

CMOS

(nm)

180
180

180

180
180

180
Min (2.483 Max (2.500 Center Frequency
Parameters GHz) GHz) (2.492 GHz)
S11 (dB) −15.4 −17.9 −16.26
S12 (dB) −30.524 −30.4 −30.475

Consumption
S21 (dB) 24.899 24.70 24.89
−10.16 −11.87 −11.06

Power

(mW)
S22 (dB)

54.6
5.6
NA
8.1
1.3
8
NF 0.987 1.00 0.994
Kf 1.12 1.132 1.1275

IIP3 (dBm)

−6.16
−8.42
−15.9
−7

NA
NA
The pre-layout and post-layout simulations have been
carried out. Input return loss (S11), output return loss
(S22), forward gain (S21), reverse gain (S12), noise figure

Stability (K)

1.1275
and stability (K) are the important parameters of the

1.61

5.26
NA

NA
NA
LNA. Figure 17 shows the performance of the proposed
LNA. The corner analysis is executed (TT, SS, FF) and
results are illustrated for TT analysis.

Reverse Gain

−30.475
(S12) dB

−43.63

−39.3
−38
NA

NA
As depicted in Figure 17, S21 furnishes the forward gain
of the proposed circuit; 24.8 dB of gain is obtained at
a desired frequency. IRNSS receiver operates in S band

Coefficient
with 16 MHz bandwidth; hence the gain values remain

Reflection

(S22) dB

−11.06
Output

−0.87

−16.4
−19.2
−12
NA
higher at the center frequency (2.492 MHz). Table 4
depicts the minimum frequency and maximum fre-
quency in the bandwidth range [27] and the S21 has been
simulated. The noise figure of the proposed LNA remains
Coefficient
Reflection

(S11) dB
< −7.8

−16.26
−13.74

−17.2
−11.6
Input

lower than 1 dB, as shown in Figure 17. Referring to

−8
Table 4, the noise figure value slightly varies between 0.9
Table 5: Comparison of the proposed cascode LNA with previous CMOS LNA designs

Noise Figure
(NF) dB

0.994
0.416

1.29
4.2

3.2

3.5
Forward Gain
(S21) dB

24.89
19.2

18.2
15.9
15

15
Vdd (V)

1.8
1.8
0.6

1.8
1

Figure 18: IIP3 and OIP3 of the proposed LNA.

Frequency

1.5–3.5

2.5-3.1
2.492
(GHz)

2–3
3–5

5
Shunt feedback with Gain

reuse folded Cascode

Boosting Technique

interstage Series LC
gm-Boosting Current
Modified Cascode
Topology

CS Cascode with
Common Gate
CS Cascode

network

A Post-Layout Simulation.
B Pre-Layout Simulation.
Note: *Measurement.
This workA
[21] A
[20]*
[2] B
[5] B
[1]*
Ref

Figure 19: 1 dB Compression point of the proposed LNA

10 D. JAHNAVI ET AL.: DESIGN AND ANALYSIS OF 2.4 GHZ LOW NOISE, HIGH GAIN 0.18 μM CMOS CASCODE LOW NOISE AMPLIFIER
and 1 dB. The input (S11) and output return loss (S22) are
obtained as −16.26 and −11.06 dB, respectively. Within
the bandwidth range the input return loss varies from
−15.4 to −17.908 dB and output return loss varies from
−10.16 to −11.87 dB.
LNA design normally remains stable but at certain
aspects it starts to oscillating due to the voltage variations
and unexpected low and high frequencies. The stability
factor K, mentioned in [11,19], is expressed as
1 − (S11 )2 − (S22 )2 + (S12 S21 − S11 S22 )2
K= (16)
2(S12 S21 )
Here if K > 1, the circuit is determined as uncondition-
ally stable. From Figure 17 it is clear that the system
remains stable within the given frequency range. The
stability of the circuit is higher than “1” all over fre-
quency range. The linearity of LNA is a critical aspect
for the whole receiver. The parameters used to deter-
mine linearity are intercept point (IIP3) and 1 dB com-
pression point. First-order and third-order signals are
introduced in LNA to determine the linearity of the cir-
cuit. From Figure 18 it is observed that the IIP3 value for
resonant frequency is −6.16 dBm with output intercept
point (OIP3) of 6.033 dBm. 1 dB Compression point is
−16.0223 dBm, as shown in Figure 19.
Comparison between the existing LNAs and proposed
LNAs is given in Table 5. Here the comparison is mainly
carried out based on the technology used, frequency
range and topological design. The results provided in
Table 5 are obtained after post-layout simulation and
these values may range 1 ∼ 1.5 dB lesser than measure-
ment result. From the comparison table it is clear that
the proposed LNA provides higher gain with low-noise
figure without any compromise between the impedance
matching.
5. CONCLUSION
In this paper CS Cascode topology with current reuse
technique along with interstage LC network is designed
for the S band frequency having 2.492 GHz centre fre-
quency. The current reuse technique along with CS cas-
code topology improves the overall voltage gain and
noise figure of the circuit. The interstage LC networks
helps in achieving better matching bandwidth. This LNA
is mainly targeted to be implemented in transceivers
designed for IRNSS applications. This proposed LNA
provides high gain of 24.89 dB with low-noise figure of
0.99 dB with a better stability of 1.127. In future, this LNA
could be implemented in two-stage design for dual-band
frequencies of L5 and S band for IRNSS receivers.
ACKNOWLEDGEMENT
The authors would like to thank Indian Space Research Organi-
zation (ISRO) for funding this project (Ref: ISRO/RES/4/654/
18-19).
FUNDING
This work was supported by Indian Space Research
Organisation [Grant Number ISRO /RES/4/654/18-19].
ORCID
D. Jahnavi http://orcid.org/0000-0002-6964-8038
G. Kavya http://orcid.org/0000-0001-8209-1302
Anjana Jyothi Banu http://orcid.org/0000-0001-6242-9265
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Authors
D. Jahnavi received the B.E. degree in
Electronics and Communication Engi-
neering and the M.E. degree in Applied
Electronics from Anna University, Chen-
nai, TN, India, in 2010 and 2013, respec-
tively. She is currently pursuing Ph.D.
degree in Information and Communi-
cation Engineering at Anna University,
Chennai, TN, India. She is working as a Research Fellow in
S.A.Engineering College for a project funded by Indian Space
Research Organization (ISRO). Her current research interests
include CMOS RF/Microwave Integrated Circuits, IC fabrica-
tion.
Corresponding author. Email: jafivenkat@gmail.com
G. Kavya received the B.E degree in Elec-
tronics and Communication Engineering
in 1999 from the Govt. College of Engi-
neering, Salem, affiliated to Madras Uni-
versity and the M.E. degree in Electron-
ics Engineering in 2003 from MIT, Anna
University. She has received her Ph.D.
from Sathyabhama University in Electron-
ics Engineering in 2015. She is currently working as a Professor
11
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in the Department of Electronics and Communication Engi-
neering, S.A Engineering College, Chennai. She has 20 years
of teaching experience in handling UG and PG classes. She
has guided many B.E. and M.E projects. She is also guiding
Ph.D. research scholars. Her areas of interest include VLSI,
Microwaves and Signal Processing. She has contributed to
many papers in national and international journals. She is a
member of ISTE, IETE and IEEE professional societies. She
is currently working on a project funded by Indian Space
Research Organization (ISRO) as the Principal Investigator.
Email: drgkavya@saec.ac.in
Anjana Jyothi Banu received the B.E.
degree in Electronics and Communication
Engineering and the M.E. degree in Com-
munication Systems from Anna Univer-
sity, Chennai, TN, India, in 2010 and 2013,
respectively. She is currently working as
an Assistant professor, ECE Department
in S.A.Engineering College. Her interests
include CMOS RF/Microwave Integrated Circuits, wireless
communication and microwave engineering. She is an active
member of IEEE Photonic society and IETE.
Email: anjanajyothibanu@saec.ac.in