sensors
Article
A Digital-Analog Hybrid System-on-Chip for Capacitive Sensor
Measurement and Control
Zhenyi Gao 1 , Bin Zhou 1, * , Xiang Li 1 , Lei Yang 2 , Qi Wei 1, *






Citation: Gao, Z.; Zhou, B.; Li, X.;
Yang, L.; Wei, Q.; Zhang, R. A
Digital-Analog Hybrid System-on-
Chip for Capacitive Sensor
Measurement and Control. Sensors
2021, 21, 431. https://doi.org/
10.3390/s21020431
Received: 7 December 2020
Accepted: 7 January 2021
Published: 9 January 2021
Publisher’s Note: MDPI stays neu-
tral with regard to jurisdictional clai-
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nal affiliations.
Copyright: © 2021 by the authors. Li-
censee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and con-
ditions of the Creative Commons At-
tribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Sensors 2021, 21, 431. https://doi.org/10.3390/s21020431
and Rong Zhang 1
1 Engineering Research Center for Navigation Technology, Department of Precision Instrument,
Tsinghua University, Beijing 100084, China; gaozy17@mails.tsinghua.edu.cn (Z.G.);
li-x07@mails.tsinghua.edu.cn (X.L.); rongzh@mail.tsinghua.edu.cn (R.Z.)
2 College of Information Science and Engineering, Shandong Agricultural University, Tai’an 271018, China;
yanglei@sdau.edu.cn
* Correspondence: zhoub@mail.tsinghua.edu.cn (B.Z.); weiqi@tsinghua.edu.cn (Q.W.);
Tel.: +86-10-6279-5692 (B.Z.)
Abstract: Sensors based on capacitance detection are common in the field of inertial measurement and
have the potential for miniaturization and low power consumption. In order to control and process
such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented.
The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta
modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the
dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm
on the chip. The low-power Cortex-M3 processor supports software implementation of control
algorithms and circuit parameter configuration. The control signal is output through a digital
BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor
(CMOS) technology and tested for performance. The result shows that the maximum operating
frequency of the chip is 105 MHz. The total area is 77.43 mm2 . When the system clock is set to
51.2 MHz, the static power consumption and dynamic power consumption of the digital system are
18 mW and 54 mW respectively.
Keywords: capacitive sensors; signal processing; SoC; low power; miniaturization
1. Introduction
The measurement of physical quantities based on capacitance detection has the charac-
teristics of low cost, miniaturization, and high accuracy. This detection scheme is commonly
used in the field of inertial measurement such as gyroscopes, accelerometers [1,2], and
angular displacement sensors [3]. The use of this type of sensor needs to be provided with
an analog control signal. After the value of the capacitance is detected, it is converted
into a digital quantity through the C/V circuit and the ADC circuit and is demodulated
according to the signal modulation method [4]. The processing circuit discussed was
firstly built using discrete devices. In order to achieve higher system integration, low
power consumption, and to has the ability to apply complex processing algorithms, the
digitalization of processing circuits is getting higher, and application-specific integrated
circuits (ASIC) have become a development trend to replace discrete devices [5].
The ASIC implementation of the analog part of the processing circuit is relatively
mature at present. Hou et al. reported in 2019 an analog interface ASIC for a capacitive
angle encoder, which consists of a C/V converter and an ADC [6]. In 2019, Lv et al. also
presented an analog interface ASIC which consists of a C/V converter and a BPSDM
ADC [7], and the circuit is used for micro-electromechanical systems (MEMS) vibratory
gyroscopes. In 2020, Ju et al. reported an auto-tuning continuous-time BPSDM for capac-
itance signal detection of MEMS gyroscopes [8]. Similar interface circuits [2,9,10] differ
mainly in C/V converter and ADC. In the field of inertial measurement, interface ASIC
https://www.mdpi.com/journal/sensors
Sensors 2021, 21, 431 2 of 14

based on capacitance detection continue to improve performance in terms of noise floor,

dynamic range, and signal-to-noise ratio.
The digital signal processing involved in the measurement and control circuit was
originally implemented in discrete devices. The digital phase demodulation circuit of
the gyro signal implemented on the Printed Circuit Board (PCB) mentioned in [11] is a
typical example. Using a digital signal processor (DSP) to realize the control algorithm in
software, the demodulation method has higher flexibility and reliability. The MEMS inertial
measurement unit (IMU) introduced by Geiger et al. [12] is based on the abovementioned
scheme for signal processing. Signal processing on a DSP has issues about phase mismatch
and signal real-time performance. Implementing signal processing algorithms on a Field
Programmable Gate Array (FPGA) at the circuit level can solve the above problems and
become a mainstream solution. In related works [7,10,13–16], the researchers reported
their cases of signal measurement and control based on FPGA in the field of inertial
measurement. When the digital signal processing circuits are designed and manufactured
using integrated circuit technology, it can obtain performance beyond the FPGA solutions,
which are also reported in some products [12,17].
In order to cope with different usage scenarios and combine control and compensation
algorithms, a development trend of digital integration solutions is to use SoC solutions
to implement software-defined circuit parameters and structures. In addition, the digital-
analog hybrid system-on-chip can bring higher integration and lower the cost [5]. In
practical applications, sensor information fusion is very extensive, and the design of a single
measurement and control chip compatible with multiple sensors is also a development
trend, which plays an important role in the development of miniaturization and low power
consumption of terminal equipment. Based on mainstream solution, which is consisting
of an analog ASIC interface circuit and an FPGA to implement digital algorithms, the
proposed solution in this paper is to integrate the two parts in a single chip, which further
improves the system integration. In terms of compatibility, this paper proposed a general
signal model and described the circuit-level architecture design, which realizes one chip to
deal with different sensor signals. The proposed design will enable the chip has the ability
to switch the working state or to work in different states at the same time.
Taking capacitive sensors in the field of inertial measurement as the research objects,
this paper reports a digital-analog hybrid SoC with sensor compatibility. The system
includes analog C/V converter, BPSDM, digital system based on Cortex-M3 [18] processor,
dedicated demodulation circuit based on LMSD algorithm, digital BPSDM and current
steering digital to analog converter (DAC). The system includes two signal demodulation
channels and two AC control signal output channels. The dedicated demodulation circuit
can demodulate digital quantities in the form of trigonometric functions to obtain sensor
information. The chip was taped out under SMIC 180 nm technology and tested for
performance, and its sensor compatibility was verified in the frequency sweep experiment
of a MEMS gyroscope and the demodulation test of an angular displacement sensor. The
next section will discuss the description for the architecture of the SoC. Sections 3 and 4
respectively present the implementation contents of analog integrated circuits and digital
integrated circuits. Section 5 provides the experimental results, and conclusions and future
research plans are discussed in Section 6.

2. Overall Description for the Architecture and Function of the Designed SoC
2.1. Description of the Architecture and the Signal Model
The simplified architecture of the designed SoC is shown in Figure 1. The capacitance
signal from the sensor is converted into a digital signal by an analog readout circuit, and
the measurement information is calculated in the digital processing system. The program
running in the processor can configure the parameters of the digital demodulation circuit
and the driving circuit, and then output the driving signal in the form of trigonometric
function through the DAC.
 capacitance signal has the following form:
∆ = ∙ sin( ∙ + ). (2)
represents the frequency of the carrier. In the above two formulas, and rep-
Sensors 2021, 21, 431 resent the relevant phase information. In addition, represents the magnitude of 3 ofthe
14
capacitance. The value change of has a linear relationship with the physical quantity to
be detected, and the information detected by the sensor can be obtained from it.

Figure1.1.Architecture
Figure Architecturediagram
diagramof
of the
the SoC.
SoC.

The system provides two channels for sensor drive and signal detection. The circuit
parameters and drive signals can be adjusted by software programs to realize closed-loop
control. For the control and measurement of MEMS gyroscopes, accelerometers, and
angular displacement sensors, the configuration of the system is sufficient. More signal
processing channels will enable a single chip to control more sensors.
The sensors discussed convert the physical quantity that needs to be detected into a
change in capacitance, and the change in capacitance has the following form [3,8,10–16]:

∆C = A·carr(ωc , ϕc )· sin(ωs ·t + ϕs ). (1)

In the above formula, ∆C represents the change value of the capacitance, carr(·) is the
expression of the carrier in the form of a square wave and ωc is the frequency of the carrier,
and ωs is the frequency related to the sensor characteristics and signal modulation method.
For example, in a gyro, the modulated signal is in the form of a sine function and ωs
represents a resonance frequency of drive axis or detection axis, and the capacitance signal
has the form of Equation (1). While in an angular displacement sensor, the modulated
signal has a constant value, and the carrier is a sine function. In this case, the capacitance
signal has the following form:

∆C = A· sin(ωs ·t + ϕs ). (2)

ωs represents the frequency of the carrier. In the above two formulas, ϕc and ϕs represent
the relevant phase information. In addition, A represents the magnitude of the capacitance.
The value change of A has a linear relationship with the physical quantity to be detected,
and the information detected by the sensor can be obtained from it.
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2.2. Overall Description of the Key Circuits

2.2. Overall Description
The twoofkey the Key Circuits
modules of the analog readout circuit are the C/V converter and t
The two
ADC.keyThe
modules
former of converts
the analogthe readout circuit value
capacitance are theinto
C/V a converter and the
voltage value, andADC.
the latter co
The formerverts
converts the capacitance
the analog value
voltage value into
into a voltage
a digital value,
value. Theand the will
details latterbeconverts
described thein Section
analog voltage The
value into
key a digital
circuit value.
of the digitalTheprocessing
details will be described
system is the LMSDin Section 3. which extrac
module,
The key
thecircuit
amplitudeof theanddigital
phaseprocessing
information system from is the LMSD
digital module,
signal inwhich extracts
the form of formula (1
the amplitude and phase information from the digital signal in the
According to the signal modulation mode and carrier form of different sensors, form of Formula (1). the p
Accordingrameter
to the signal modulation mode and carrier form of different
configuration of the LMSD calculation channel can be carried out by the prograsensors, the pa-
rameter configuration
running in of thethe LMSD calculation
processor. channel can behardware
The software-defined carried out by the program
parameters enable a sing
running incircuit
the processor.
to process The software-defined
multiple types of sensor hardware
signals.parameters
When the enablesensor asignal
singlehascir-the form
cuit to process multiple
formula (2), thetypes of sensor
common clocksignals.
gating [19] When the sensor
technology in signal
digital has thedesign
circuit form ofcan turn o
Formula (2),
thethe common
drive clock clock
of thegating [19] technology
redundant module. The in digital
detailscircuit
of the design can turn
algorithm andoffthe circu
the drive clock of the redundant module.
will be described in Section 4. The details of the algorithm and the circuits will
be described inTheSection 4.
drive signal generator outputs a drive signal in the form of a trigonometr
The drive signal
function, generator
which outputs abydrive
is modulated digital signal
BPSDM in the form
[20] andofoutput
a trigonometric
by a 20-bit curre
function, which is modulated
steering DAC [21]. by Thedigital BPSDM
four-stage [20] and output by a 20-bit
cascade-of-integrators current steering
feed-forward structure was im
DAC [21]. plemented
The four-stage cascade-of-integrators feed-forward structure was
in the design of the digital BPSDM, and the center frequency of pass band ca implemented
in the design
be of the digitalthrough
configured BPSDM,software.
and the center
Therefrequency
is no moreofnovelpass band
contentcaninbethe
configured
related design an
through software. There is no more novel content
no more specific introduction in the article. in the related design and no more specific
introduction in The
the article.
Phase Locked Loop (PLL) is a digital-analog hybrid module that can convert th
The Phase
outputLocked
clock ofLoop (PLL) oscillator
the crystal is a digital-analog
to a stablehybrid module
clock signal. The that canclock
stable convertsignal is use
the output clock of the crystal oscillator to a stable clock signal. The stable clock signal is
to drive the SoC and the clock frequency can be configured dynamically by software.
used to drive the SoC and the clock frequency can be configured dynamically by software.
dedicated bootloader was integrated into the SoC, which supports program loadin
A dedicated bootloader was integrated into the SoC, which supports program loading
through on-chip One Time Programmable (OTP) memory, off-chip flash memory
through on-chip One Time Programmable (OTP) memory, off-chip flash memory or online
online Joint Test Action Group (JTAG) debugger. Detailed information about unique d
Joint Test Action Group (JTAG) debugger. Detailed information about unique designs for a
signs for a variety of application scenarios has been reported in previous work [22].
variety of application scenarios has been reported in previous work [22].
In terms of communication bus and memory, Advanced Microcontroller Bus A
In terms of communication bus and memory, Advanced Microcontroller Bus Archi-
chitecture (AMBA) [23] is used as a communication protocol for the transmission of co
tecture (AMBA) [23] is used as a communication protocol for the transmission of control
trol signals and data between the processor and the circuit modules. The size of on-ch
signals and data between the processor and the circuit modules. The size of on-chip
OTP memory is 128 KB, which is sufficient for inertial measurement needs. In additio
OTP memory is 128 KB, which is sufficient for inertial measurement needs. In addition,
16 General16Purpose
GeneralInput Purpose Input
Output Output
(GPIO) (GPIO) interfaces,
interfaces, 2 serial Asynchronous
2 serial Universal Universal Asynchrono
Receiver/Transmitter (UART) modules, one Serial Peripheral Interface (SPI) Interface
Receiver/Transmitter (UART) modules, one Serial Peripheral and the JTAG(SPI) and th
JTAG interface constitute the entire system
interface constitute the entire system debugging interface circuits. debugging interface circuits.

3. Design 3. Design Description

Description of the C/Vof the C/V Converter
Converter and the ADCand the ADC
3.1. Implementation Details of the
3.1. Implementation C/V Converter
Details of the C/V Converter
A charge amplifier
A charge was implemented
amplifier in the C/Vinconverter.
was implemented The basic principle
the C/V converter. The basicof a
principle of
charge amplifier
chargebased on differential
amplifier capacitancecapacitance
based on differential detection is detection
shown in is
Figure
shown2a.inUsing a 2a. Usin
Figure
capacitor as a feedbackaselement,
a capacitor the amplifier’s
a feedback element, thenoise bandwidth
amplifier’s noisecan be reduced
bandwidth can and
bethe
reduced an
detection accuracy can be improved [24].
the detection accuracy can be improved [24].

(a) (b)
Figure 2. The designed C/V converter based on DC capacitance cancellation. (a) Schematic diagram of the charge ampli-
Figure 2. The designed C/V converter based on DC capacitance cancellation. (a) Schematic diagram
fier for differential capacitance detection; (b) DC capacitance cancellation scheme.
of the charge amplifier for differential capacitance detection; (b) DC capacitance cancellation scheme.
Sensors 2021, 21, 431 5 of 14

As shown in Figure 2a, assume that the capacitance value to be detected is Cs =

C0 ± ∆C, where C0 is the basic capacitance value, ∆C is the change in capacitance value,
and Cc is the on-chip cancellation capacitance in the circuit. An AC voltage is added at the
input end of the differential capacitor as a voltage source, and a reverse voltage source is
added at the input end of the cancellation capacitor. According to the amount of charge
transfer on the detection capacitor and the cancellation capacitor, the amount of charge
change at one input of the charge amplifier is calculated as follows:

Q = ∆(Cs × VS ) + ∆(Cc × (−VS ))

= ∆Cs × Vs + Cs × ∆Vs − ∆Cc × Vs − Cc × ∆Vs (3)
= ±∆C × Vs + (C0 ± ∆C ) × ∆Vs − Cc × ∆Vs .

When the second-order small quantities are ignored and Cc = ±C0 , Equation (3) is
transformed into the following equation:

Q = ±∆C × Vs . (4)

The principle of the DC cancellation capacitor Cc is shown in Figure 2b) The voltage
source is a carrier with the opposite phase to the high-frequency carrier, and the internal
structure is a DC capacitor array, including eight cancellation capacitors and switches. The
eight CMOS switches S1, S2, S3,..., S8 are controlled by the digital system to determine the
value of Cc is 2n ·C (n = 1, 2, . . . , 8). After the processing of the capacitive inertial sensor is
completed, C0 has been determined, and this method can correct part of the DC error of
the sensor. In this design, the value of the basic capacitance C is 49 fF.
The complementary recycling folded cascode (CRFC) architecture [6] was adopted
as the amplifier in the C/V conversion circuit. Combined with Equation (3), the output
transfer function of the charge amplifier is as follows:

− jω − jω
Vo+ = 1
× (∆C × Vs ),Vo− = 1
× (−∆C × Vs ). (5)
RF + jωCF RF + jωCF

According to Equation (5), the C/V circuit converts the capacitance change value
into a voltage value with a linear change relationship. The existence of the cancellation
capacitor can suppress the DC error and improve the gain coefficient of the conversion
circuit.

3.2. Implementation Scheme of the BPSDM ADC

According to Equation (1), the sensor signal is modulated to high frequency, and a
band pass ADC is applied, which can effectively reduce the impact of the low frequency
noise of the operational amplifier on the circuit. The schematic diagram of the BPSDM
circuit is shown as in Figure 3. The adopted solution is a continuous-time third-order band
pass modulator, in which a resonator, a quantizer and a DAC are included. The resonator
is mainly composed of RC filter structure [8], which provides noise shaping capability
for ADC. The quantizer with successive approximation structure outputs a 3-bit digital
code stream, which is used to provide a quantized digital signal and a feedback signals.
A capacitive feedback array is implemented in the DAC feedback network. The quantized
signals are fed back to the input of the C/V module, and negative feedback charge is
injected at the feedback point to offset the charge change caused by the sensor capacitance
change, forming a negative feedback analog signal and realizing a switched capacitor DAC
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Figure 3. Schematic diagram of the BPSDM circuit.

3. Schematic diagram of the BPSDM
Figure Figure
3. Schematic diagram of the BPSDM circuit. circuit.

The circuit of the Theanalog readout system readout

was implemented in implemented
Cadence, which Cadence,
is a
The circuit
circuit ofof the analog
the analog system was
readout system was implemented ininCadence, whichisisa
which
software for integrated
asoftware circuit
softwarefor design
forintegrated and
integratedcircuitsimulation.
circuitdesign The
designand carrier
andsimulation.frequency
simulation.The The was set
carrier to
frequency was
carrier frequency was setset
to
100 kHz and the to signal
100 frequency
kHz and thewas set to
signal 10 kHz for
frequency wassimulation.
set to 10 According
kHz for to Equa- According to
simulation.
100 kHz and the signal frequency was set to 10 kHz for simulation. According to Equa-
tion (1), the simulated
Equationinput signal
(1), the was obtained
simulated andwas
input signal the obtained
simulated output
and signal was
the simulated output signal was
tion (1), the simulated input signal was obtained and the simulated output signal was
collected. As show in Figure
collected. 4, with
As show signal 4,
in Figure modulating
with signaland noise shaping,
modulating the shaping,
and noise shape ofthe shape of the
collected. As show in Figure 4, with signal modulating and noise shaping, the shape of
the original signal is notsignal
original clearisinnot
theclear
timeindomain
the timewaveform of the output
domain waveform of the3 output
bit digital
3 bit digital signal.
the original signal is not clear in the time domain waveform of the output 3 bit digital
signal. In the frequency domain,domain,
In the frequency the noise thefloor near
noise thenear
floor signal
thefrequency point ispoint
signal frequency low, is low, and the
signal. In the frequency domain, the noise floor near the signal frequency point is low,
three spectral
and the three spectral lines oflines of the and
the carrier carrier
theand thecan
signal signal can be clearly
be clearly distinguished.
distinguished.
and the three spectral lines of the carrier and the signal can be clearly distinguished.

(a)
(a)

(b)
(b)
gure 4. Simulation data of analog readout system. (a) Time-domain waveform of analog circuit output signal; (b) am-
Figure4.4.Simulation
Simulationdata
dataofofanalog
analogreadout
readoutsystem.
system.(a)
(a)Time-domain
Time-domainwaveform
waveformofof analog
analog circuit
circuit output
output signal;
signal; (b)(b) am-
ampli-
itude spectrumFigure
of the signal.
plitude spectrum of the signal.
tude spectrum of the signal.
Sensors 2021, 21, x FOR PEER REVIEW 7 of 14
Sensors 2021, 21, 431 7 of 14

The digital signal output by the analog readout circuit is demodulated in the digital
The digital
processing signal
system, output
which by the analog
is introduced readout
in the circuit isThe
next section. demodulated in the
amplitude of eachdigital
com-
ponent in the modulated signal and the signal amplitude to be measured will becompo-
processing system, which is introduced in the next section. The amplitude of each calcu-
nent in
lated inthe
themodulated signal
digital circuit andand the signal
output amplitude
or further to bein
processed measured willprocessor.
Cortex-M3 be calculated in
the digital circuit and output or further processed in Cortex-M3 processor.
4. Design Description of Digital Demodulation Module
4. Design Description of Digital Demodulation Module
The digital signal processing circuit demodulates the signal to obtain the sensor
The digital signal processing circuit demodulates the signal to obtain the sensor
signal. The methods used for signal demodulation mainly include multiplication de-
signal. The methods used for signal demodulation mainly include multiplication demod-
modulation [25], LMSD and other optimized demodulation algorithms [26,27]. Among
ulation [25], LMSD and other optimized demodulation algorithms [26,27]. Among these
these methods, the calculation speed of LMSD is fast and easy to implement in circuit,
methods, the calculation speed of LMSD is fast and easy to implement in circuit, and
and optimized demodulation solution based on LMSD is adopted in the circuit.
optimized demodulation solution based on LMSD is adopted in the circuit.
The principle of the demodulation scheme is shown in Figure 5. As shown in Figure
The principle of the demodulation scheme is shown in Figure 5. As shown in Figure 4b
4b and Equation (1), the signal processed in the circuit is modulated twice at most. In the
and Equation (1), the signal processed in the circuit is modulated twice at most. In the time
time domain,
domain, with with the multiplication
the multiplication operation
operation of theoftwo
thefrequency
two frequency signals,
signals, the following
the following form
form of reference signals are generated in the circuit:
of reference signals are generated in the circuit:
( ) = cos( ∙ t + φ ) × sin( ∙ t + φ ),
r1 (k) = cos(ωc ·t + ϕc0 ) × sin(ωs ·t + ϕs0 ),
r2 ((k) )==cos
cos(
(ωc ·t∙+
t +ϕφ ) ×cos
c0 ) × cos(
(ωs ·t ∙+t + φ), ),
ϕs0
(6)
r3 ((k) )==sin (ωc ·t∙+
sin( c0 ) ×
t +ϕφ ) ×sin (ωs ·t ∙+t +
sin( φ), ),
ϕs0
r4 (k) = sin(ωc ·t + ϕc0 ) × cos(ωs ·t + ϕs0 ).
( ) = sin( ∙ t + φ ) × cos( ∙ t + φ ).
where ωc and ωs indicate the frequency related to the modulated signal, ϕc0 and ϕs0
where and indicate the frequency related to the modulated signal, φ and φ
represent the initial phase of the reference signal.
represent the initial phase of the reference signal.

Figure 5. Block diagram of the demodulation method.

Figure 5. Block diagram of the demodulation method.

The demodulationalgorithm
The demodulation algorithmdecomposes
decomposesthe the modulated
modulated signal
signal intointo
fourfour reference
reference sig-
signals in Equation (6) by iterative calculation, and calculates the amplitudes of
nals in Equation (6) by iterative calculation, and calculates the amplitudes of the reference the ref-
erence
signals.signals. The iteration
The iteration result isresult is expressed
expressed by the following
by the following four variables:
four variables:
( ) = ( ( ), ( ), ( ), ( )). (7)
w(k) = (w1 (k), w2 (k), w3 (k), w4 (k )). (7)
And the iteration process is performed according to the following formulas:
And the iteration process is performed according to the following formulas:
( ) = ( , , , ),
r (k() =
)=(r1 , (r2 ,)r∙3 , r(4 )), ,
y(k) = w(k)·r (k) T , (8)
(8)
err (k() =
) =s(k() − )− y(k(), ),
w((k + )=
+ 11) = w((k)) ++ 2µ2 ·err ∙ (k()·r)(∙k)(. ).
Sensors 2021, 21, 431 8 of 14
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where µ is the
where step
is the stepfactor
factorused
used for
for parameter updating, kisisthe
parameter updating, the number
number of sampling
of sampling
points, s(k) (indicates
points, ) indicates
thethe sampling
sampling signal, y(k )(is)the
signal, is the calculated
calculated reference
reference signal
signal andand
err (k)
( ) represents
represents the error between
the error between the sampling
the sampling signal
signal and and
the the reference
reference signal.
signal.
According
According to to
thethe iterative
iterative calculationresult
calculation w(k )(, the
resultofof ), the signal
signal amplitude
amplitude A in in
Equa-
tionEquation (1) obtained
(1) can be can be obtained
throughthrough following
following equation:
equation:
( )= ( )+ ( )+ ( )+ ( ). (9)
A2 (k) = w12 (k ) + w22 (k ) + w32 (k ) + w42 (k). (9)
The data path described above is based on a twice modulated sampling signal, and
theThe
reference
data pathsignal is also modulated.
described above is based When onthe sampling
a twice signal is
modulated modulated
sampling only and
signal,
once and has the form of Equation (2), the circuit parameters can
the reference signal is also modulated. When the sampling signal is modulated only be configured through
software.
once and has When the values
the form of
of Equation (2), φthe are
and set to
circuit 0, the reference
parameters can besignal only contains
configured through
the unmodulated sine and cosine signals. The path has also been simplified,
software. When the values of ωs and ϕs0 are set to 0, the reference signal only contains and the the
simulation of the simplified data path has been carried out in previous work [16]. In this
unmodulated sine and cosine signals. The path has also been simplified, and the simulation
way, the demodulation of modulated signals of any order can be achieved on the circuit
of the simplified data path has been carried out in previous work [16]. In this way, the
level.
demodulation of modulated signals of any order can be achieved on the circuit level.
The mathematical calculations involved in the above scheme are implemented by
The mathematical calculations involved in the above scheme are implemented by
using combinatorial logic to realize an iterative calculation in a single clock cycle. Based
using combinatorial
on Cordic algorithm logic
[28],to realize
the signalan iterative
generator is calculation
implemented inina combination
single clock logic.
cycle.Af-
Based
on ter
Cordic algorithm [28], the signal generator is implemented in combination
28 iterations, it can complete the calculation and output the sine and cosine signal in logic. After
28 iterations,
one clock cycle. The output result is shown in Figure 6, and the error is less than one
it can complete the calculation and output the sine and cosine signal in
clock
1.5cycle.
× 10 The
. output result is shown in Figure 6, and the error is less than 1.5 × 10−7 .

(a)

(b)
Figure
Figure 6 Digital
6. Digital reference
reference signals.
signals. (a)(a) Waveformsofofsine
Waveforms sine and
and cosine
cosine signals;
signals;(b)
(b)error
errorofof
digital reference
digital signal.
reference signal.

Digital
Digital simulationwas
simulation wasperformed
performed on
on the
thedata
datafrom
fromthe
theanalog readout
analog circuit.
readout The The
circuit.
simulation tool is VCS from Synopsys and the simulated input data is shown in Figure 4
simulation tool is VCS from Synopsys and the simulated input data is shown in Figure 4
in Section 3. In the simulation, = 10,000, = 100,000, φ = −0.2171, φ = 0.08,
in Section 3. In the simulation, ωc = 10,000, ωs = 100,000, ϕc0 = −0.2171, ϕs0 = 0.08,
= 0.03, and related parameters were quantified into fixed-point numbers and config-
µ = 0.03, and related parameters were quantified into fixed-point numbers and configured
into the circuit through software. The demodulation results are shown in Figure 7. Figure 7a
shows the convergence process of the amplitude components for the four reference signals,
and Figure 7b shows the calculation result of the sensor measurement signal.
Sensors 2021, 21, x FOR PEER REVIEW 9 of 14

Sensors 2021, 21, 431
ured into the circuit through software. The demodulation results are shown in Figure 7.
Figure 7a shows the convergence process of the amplitude components for the four9 of
ref-
14
erence signals, and Figure 7b shows the calculation result of the sensor measurement
signal.

(a)

(b)
Figure 7.
Figure 7. Simulation
Simulationresults
resultsfor
fordigital
digital demodulation.
demodulation. (a)(a) Convergence
Convergence process
process of reference
of reference signal
signal amplitude
amplitude compo-
components;
nents; (b) the simulated sensor
(b) the simulated sensor signal. signal.

The
The circuit
circuit parameters
parameters of the demodulation
of the demodulation module,
module, such
such as the configuration
as the configuration of of
frequency, phase, step factor, etc., are completed by a program running in the processor,
program running in the processor,
and
and the demodulation
demodulation resultresult can
can also be sent out of the chip through the processor and
the communication
communication interface.
interface.TheThedigital
digitalpart
partalso
also includes
includes thethe generation
generation of drive
of drive sig-
signals,
nals,
whichwhich is realized
is realized by aby a signal
signal generator
generator to to generate
generate a sineand
a sine andcosine
cosinesignal,
signal, and
and the
configuration of ofthe
thefrequency,
frequency, phase
phase andand amplitude
amplitude of theofdrive
the signal
drive issignal
realizedis realized
through
through
software.software.
When the measured
measured sensor
sensorsignal
signalisismodulated
modulatedonly only once,
once, as as shown
shown in Equation
in Equation (2),
(2), the signal
the signal generator
generator in theincircuit
the circuit
can becan
setbebyset by software
software to generate
to generate a reference
a reference sig-
signal with
a frequency
nal of 0 Hz, which
with a frequency of 0 Hz,canwhich
achievecanthe compatibility
achieve of the demodulation
the compatibility algorithm.
of the demodulation
The relatedThe
algorithm. simulation experiments
related simulation have been reported
experiments have been inreported
the previous works
in the [15,16].
previous works
[15,16].
5. Performance and Function Testing of the Chip
5.1.
5. Test Results of
Performance theFunction
and Chip Testing of the Chip
TheResults
5.1. Test designed SoC
of the was taped out under the SMIC 180 nm CMOS technology. The
Chip
layout and the die picture of the chip are shown in Figure 8, in which the main parts are
The designed SoC was taped out under the SMIC 180 nm CMOS technology. The
marked out. The total area of the chip is 8.9 × 8.7 = 77.43 mm2 . The maximum running
layout and the die picture of the chip are shown in Figure 8, in which the main parts are
frequency of the chip is 105 MHz. The analog power supply and digital power supply of the
marked out. The total area of the chip is 8.9 × 8.7 = 77.43 mm . The maximum running
chip are separated. A 5 V voltage source is provided for the analog circuit, and the digital
frequency of the chip is 105 MHz. The analog power supply and digital power supply of
circuit needs a 1.8 V voltage source. When the clock frequency is 51.2 MHz, a processing
algorithm was run in the processor to evaluate the power consumption. The currents of the
analog and digital circuits are 80 mA and 30 mA, and the power consumption is 400 mW
and 54 mW respectively. When the chip is in the power-on idle state, the static current of
the digital circuit is 10 mA, and the static power consumption is 18 mW.
 the chip are separated.
the chip areA 5separated.
V voltageAsource is provided
5 V voltage sourceforis the analogfor
provided circuit, and the
the analog circuit, an
digital circuitdigital
needs circuit
a 1.8 Vneeds
voltage source.
a 1.8 Whensource.
V voltage the clock
When frequency is 51.2
the clock MHz, is
frequency a 51.2 M
processing algorithm
processingwasalgorithm
run in thewas
processor to evaluate
run in the processor thetopower consumption.
evaluate The
the power consumption
currents of the analog of
currents andthedigital
analogcircuits are 80circuits
and digital mA and are3080mA,
mA andand the power
30 mA, andcon-
the power
Sensors 2021, 21, 431 sumption is 400 mW and
sumption 54 mW
is 400 mW respectively.
and 54 mW When the chip
respectively. is inthe
When thechip
power-on idlepower-on
is in the
10 of 14
state, the static current
state, of thecurrent
the static digital circuit is 10 mA,
of the digital andisthe
circuit 10 static
mA, andpower
theconsumption
static power consum
is 18 mW. is 18 mW.

Output
Circuit

PLL

Analog Readout
Circuit

Digital Processing System

(a) (a) (b) (b)

Figure 8. The Figure
layout
Figureand thelayout
8.8.The
The die piecture
layout andthe
and ofdie
the the designed
diepiecture SoC.
piectureofof (a) Chip SoC.
thedesigned
the designed layout; (b)
SoC.(a)(a) dielayout;
Chip
Chip picture.
layout;(b)
(b) die
die picture.
picture.

From thethe power

power consumption
From the powerresults,
consumption results, thethe
consumption digital
digitalsystem
results, thehas
system the the
has
digital characteristics
characteristics
system has the of lowof
characterist
power
low powerconsumption,
consumption,
low power whileconsumption,
the power
while the consumption
power
while the of
consumption the analog
power of thecircuit
consumption analog is of
large thecompared
circuit is large
analog circuit is
with state-of-the-art
compared withcompared works.
state-of-the-art
with There is a certain
works.
state-of-the-art Theredifference
is a certain
works. Therebetween
difference the power
is a certain between consumption
difference the power
between the p
in analog circuit
consumption in tested
analogincircuit
consumption experiment
tested and
in analog in thetested
resultsinfrom
experiment
circuit and simulation
the
experiment results and and
from theprevious
simulation
results from works
andsimulation
in the laboratory.
previous works After analysis
in the laboratory.
previous works in the and circuit
After inspection,
analysisAfter
laboratory. such
and circuit
analysis test results
inspection,
and circuit are
such related to the
test results
inspection, such test r
on-chip
are relatedreference
to are voltagetogeneration
the related
on-chip reference
the on-chip circuits
voltage usedvoltage
generation
reference for ADC andused
circuits
generation DAC, forandADC
circuits the excessive
and
used DAC,
for ADC and
operational amplifiers.
and the excessive and the The circuit
operational
excessive parameters
amplifiers.
operational The without
circuit
amplifiers. proper
parameters
The circuit optimization
without
parameters also
proper have
optimi-
without anproper op
impact on the
zation also havepower
zation consumption
an impact
also on the
have in the on
power
an impact analog
consumptioncircuit.consumption
the power in the analog circuit. in the analog circuit.
In order to verify
In order to verify the chip’s
the chip’s
In order to verify ability
abilitythe to to process
process
chip’s signals
signals
ability in the
in the form
to process form
signals ofin oftheEquations
Equationsform(1) (1)
of and
Equations (1
and (2), the frequency
(2), the frequency sweep
(2), the sweep test
test of asweep
frequency of a
gyro testgyro
and of and the
thea step step
gyrotest
andofthetest of
anstep an
angular angular displacement
displacement
test of an angular sensor displacement s
sensor were carried
were carried out.
wereThe out. The experimental
experimental
carried out. The site and site
experimental andsitethe
the circuit circuit
boards
and boards
involved
the circuit involved
are shown
boards are
involved inshown
Figure
are shown in F
in Figure 9. The
9. The demodulation demodulation of
of the angular of
9. The demodulation the angular
displacement displacement
the angular sensor sensor
needs to
displacement needs
obtain
sensor to obtain
the sine
needs the the
signal
to obtain sine
andsine signa
signal and the
the cosine signal cosine signal
from the
the cosine from
modulated
signal the modulated
from thesensor sensor
signalssensor
modulated signals
and calculate and
signals and calculate
the angle
calculate the
value. angle
the The
angle value
value. The frequency
frequency sweep sweep
experiment
frequency sweep experiment
ofexperiment of
the gyro requiresthe gyro requires
the chip
of the gyro the chip
to provide
requires to
the chip provide
excitation
to provide excitation
signals of
excitation sign
signals
differentoffrequencies
different frequencies
different forfrequencies
the drive foraxis thethe
for drive
and theaxis
drive and
detection
axis and theaxis
thedetection axis
of the gyro,
detection axisof
and the
of gyro,
gyro,and
demodulate
the and demod
demodulate the signal to
the signal amplitudes amplitudes to find the frequency
find the resonance resonance corresponding
frequency corresponding to the maximum to the
the signal amplitudes to find the resonance frequency corresponding to the maxi
maximum amplitude
amplitude according according
to the to
frequency the frequency
sweep sweep curve.
curve. sweep curve.
amplitude according to the frequency

(a) (a) (b) (b) (c) (c)

Figure 9. The testing site and testing boards. (a) Equipments for function testing; (b) step test of an angular displacement
sensor; (c) frequency sweep experiment of a MEMS gyroscope.

The output signal of the angular displacement sensor [3] used in the test has a period-
icity with a period of 10◦ . During the experiment, the turntable rotates at a speed of 0.5◦
per second, and the measurement time is 100 s. The demodulation and angle calculation
results from the chip are shown in Figure 10. Since the angle to be measured changes
 Figure 9. The testing site and testing boards. (a) Equipments for function testing; (b) step test of an angular displacement
sensor; (c) frequency sweep experiment of a MEMS gyroscope.

The output signal of the angular displacement sensor [3] used in the test has a perio-
Sensors 2021, 21, 431 11 of 14
dicity with a period of 10°. During the experiment, the turntable rotates at a speed of 0.5°
per second, and the measurement time is 100 s. The demodulation and angle calculation
results from the chip are shown in Figure 10. Since the angle to be measured changes with
time, the two
with time, thedemodulated signalssignals
two demodulated are a sine
aresignal
a sineand a cosine
signal and asignal,
cosineassignal,
shownas inshown
Figure
10a. The angular output and error results are plotted in Figure 10b using dual coordinate
in Figure 10a. The angular output and error results are plotted in Figure 10b using dual
axes.
coordinate axes.

(a)

(b)
Figure 10.
Figure 10. The
Thetesting
testingsite
siteand
andtesting
testingboards.
boards.(a)(a)
Equipments forfor
Equipments function testing;
function (b) (b)
testing; stepstep
testtest
of an
ofangular displacement
an angular sen-
displacement
sor.
sensor.

The chip was also electrically connected

connected to an MEMS gyroscope [29] on the PCB, as
shown in Figure
Figure 9c.
9c.The
Theresonant
resonantfrequency
frequencyofofthe
the gyroscope
gyroscope drive
drive axisaxis
andandthethe detec-
detection
tion
axis axis is measured
is measured in the
in the open-loop,
open-loop, non-tuning
non-tuning state.The
state. Thedigital
digitalcircuit
circuit is
is configured
through
through an algorithm running in the processor to generate drive signals and reference
signals
signals of different frequencies,
frequencies, andand the
the demodulation
demodulation results
results are
are sent
sent through
through UART. UART.
Different demodulation results were collected by by adjusting
adjusting thethe frequency
frequency value.value. The
maximum value
maximum value of the demodulation result corresponds to the resonance frequency of
the gyro. TheThe frequency
frequency sweep
sweep experiment
experiment was
was performed
performed on on both
both the drive axis and
the detection aixs, and the frequency sweep curve is shown in Figure Figure 11.11. The ordinate
represents the numerical
represents numerical value of the demodulation result, which is multiplied by the
scaling factor to obtain
obtain the
the true
trueoutput
outputofofthe
thegyro.
gyro.The
Thescale
scalefactor
factoris is
related
related to to
thethe
sensor
sen-
and needs to be obtained by further sensor experiments. From Figure 11,
sor and needs to be obtained by further sensor experiments. From Figure 11, the experi- the experimental
results show
mental resultsthat
showthethat
resonant frequency
the resonant of the measured
frequency gyroscope’s
of the measured drive axis
gyroscope’s andaxis
drive the
detection
and axis differ
the detection axisbydiffer
aboutby5 about
Hz, which
5 Hz,iswhich
basically consistent
is basically with thewith
consistent measurement
the meas-
results ofresults
urement the same batch
of the of gyroscopes.
same batch of gyroscopes.
The above two tests verified the correctness of the main measurement and control
functions of the chip. Other functions of the chip have also been tested. On-chip interface
circuit used to drive other AD/DA chips, UART interface circuit, SPI interface circuit,
program loading test from off-chip FLASH or on-chip OTP memory, JTAG debugging
interface circuit, on-chip single-cycle trigonometric function calculation circuit and other
functions also have been verified.
Sensors 2021, 21, 431 12 of 14
Sensors 2021, 21, x FOR PEER REVIEW 12 of 14

Figure 11. Sweep frequency curves of the drive axis and detection axis of the gyro.
Figure 11. Sweep frequency curves of the drive axis and detection axis of the gyro.

The above two tests verified the correctness of the main measurement and control
5.2. Discussion
functions of the chip. Other functions of the chip have also been tested. On-chip interface
circuitThe realization
used to driveofotherintegrated
AD/DA circuits
chips,for processing
UART interfacecircuits is aSPI
circuit, means and develop-
interface circuit,
ment trend to further realize high integration and low
program loading test from off-chip FLASH or on-chip OTP memory, JTAG debugging power consumption in the field of
inertial measurement.
interface circuit, on-chipThe measurement
single-cycle and control
trigonometric chip reported
function calculation in this article
circuit and is the
other
first monolithic integrated,
functions also have been verified. sensor-compatible measurement and control system that has
appeared in recent years. The test results show that the designed and implemented digital-
analog
5.2. hybrid SoC can work normally. Different sensor experiments have further verified
Discussion
the compatibility of the chip in control and processing when the signal of the capacitive
The realization of integrated circuits for processing circuits is a means and devel-
sensor meets a specific form. In terms of power consumption, the power consumption of
opment trend to further realize high integration and low power consumption in the field
digital systems is relatively low, while the design of analog circuits needs to be further
of inertial measurement.
optimized to meet low-power The measurement
usage scenarios. and control chip reported in this article is the
first monolithic integrated, sensor-compatible
The reference signals required by the ADC and measurement
DAC in theand control
analog system
circuit that has
are generated
appeared in recent years. The test results show that the designed
by the internal reference power circuit. This part of the power consumption is relatively and implemented dig-
ital-analog hybrid SoC can work normally. Different sensor
large, and this part will be removed in the future design. In addition, there are many experiments have further
verified
operational the amplifiers
compatibility in theof circuit,
the chip andin the
control
staticand
powerprocessing when isthe
consumption signal of
relatively the
large.
capacitive sensor meets a specific form. In terms of power consumption,
The use of operational amplifiers will also be optimized. In this design, the interface the power con-
sumption of digital
circuit requires many systems
voltageissources.
relativelyIn low, whiledesign,
the future the design of analog
passive circuitcircuits needs to
implementation
be further optimized to meet low-power usage scenarios.
schemes will be combined to minimize the use of voltage sources. According to the
The reference
previously reported signals
powerrequired
consumption by theofADC and analog
a single DAC ininterface
the analog chipcircuit
[6,8], are gen-
a power
erated by the of
consumption internal
tens of reference
mW of analog power circuit.
circuits, andThis partpower
a total of theconsumption
power consumption of no more is
relatively
than 100 mW, large,isand this part
the next will be
expected removed
goal. During inthe
theexperiment,
future design. theInanalog
addition, there
circuit are
needs
many
externaloperational amplifiers and
reference capacitors in the circuit,When
resistors. and the thestatic
values power
of theconsumption
electronic devicesis relative-
don’t
ly large. The use of operational amplifiers will also be optimized.
match the internal values, it will cause the mismatch of the circuit parameters, so that In this design, the the
in-
terface circuit
signal input fromrequires
the ADC manyto thevoltage
digitalsources. In the future
system contains design,signals
interference passiveandcircuit im-
no longer
plementation
meets Equation schemes
(1). When willthebesensor
combinedhas ato minimize
large processing the use
error,ofthevoltage
presetsources.
value of Ac-the
cording to the
cancellation previouslydoes
capacitance reported power
not match theconsumption
actual value, of anda single
the aboveanalog interface
problem will chip
also
[6,8],
occur.a This
power consumption
situation is common of tens of mW of
in practical analog circuits,
applications andbe
and will a solved
total power con-
by digital
sumption of no more
signal processing than 100inmW,
algorithms is the
future next expected
optimization goal. During the experiment, the
designs.
analog circuit needs external reference capacitors and resistors. When the values of the
6. Conclusions
electronic devices don’t match the internal values, it will cause the mismatch of the cir-
cuit parameters, so that the
This article reports the design
signal andinputtestfrom the of
results ADC to the digitalhybrid
a digital-analog systemmeasurement
contains in-
and control
terference chip used
signals and no forlonger
capacitivemeetssensors
Equation in the(1).field
When of the
inertial
sensormeasurement.
has a large pro- The
reportederror,
cessing chip monolithically
the preset value integrates the analog interface
of the cancellation capacitance circuit
doesandnotthe digital
match theprocess-
actual
ing system,
value, and the and has the
above characteristics
problem will also of miniaturization
occur. This situation andis low
commonpower inconsumption
practical ap-
of the digital system. Benefiting from an on-chip processor
plications and will be solved by digital signal processing algorithms in future and the digital demodulation
optimiza-
algorithm
tion designs. compatible with the signal model, the chip has high flexibility in use and can
meet different usage scenarios and sensor measurement.
6. Conclusions
Sensors 2021, 21, 431 13 of 14

In the integrated measurement and control technology of inertial sensors, the chip
reported in this article has a significant improvement in circuit integration and richness of
functions compared to previous work [22]. Future research will focus on the power con-
sumption optimization of analog circuits, system-in-package of MEMS structures and SoC
chips. Combining high-performance processors and digital signal processing algorithms to
further improve sensor accuracy is another research interest.

Author Contributions: R.Z. proposed the system’s integration plan and compatibility design plan.
B.Z. and Z.G. implemented algorithm development the digital front-end design. L.Y. implemented
the digital backend design. Q.W. and X.L. implemented the analog circuit design and layout design.
Z.G. and X.L. tested the chip. Z.G. wrote the paper. B.Z., Q.W. and R.Z. revised the paper. All authors
have read and agreed to the published version of the manuscript.
Funding: This project is supported by the National Key R&D Program of China under (grant No.
2018YFB1702500).
Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.
Data Availability Statement: Data sharing not applicable.
Conflicts of Interest: The authors declare no conflict of interest.

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