OBJECT - Phase-Locked Loop Basics,

PLL
A phase-locked loop (PLL) is a closed-loop frequency-control system based on the phase
difference between the input clock signal and the feedback clock signal of a controlled
oscillator. Figure 1 shows a simplified block diagram of the major components in a PLL. The
main blocks of the PLL are the phase frequency detector (PFD), charge pump, loop filter,
voltage controlled oscillator (VCO), and counters, such as a feedback counter (M), a pre-
scale counter (N), and post-scale counters(C).

Figure 1. PLL Block Diagram

PLLs in Alter FPGAs align the rising edge of the reference input clock to a feedback clock
using the PFD. The falling edges are determined by the duty-cycle specified by the user. The
PFD detects the difference in phase and frequency between the reference clock and feedback
clock inputs and generates an “up” or “down” control signal based on whether the feedback
frequency is lagging or leading the reference frequency. These “up” or “down” control
signals determine whether the VCO needs to operate at a higher or lower frequency,
respectively.

The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump
receives an up signal, current is driven into the loop filter. Conversely, if it receives a down
signal, current is drawn from the loop filter.

The loop filter converts these signals to a control voltage that is used to bias the VCO. Based
on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the
phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO
frequency increases. A down signal decreases the VCO frequency. The VCO stabilizes once
the reference clock and the feedback clock have the same phase and frequency. The loop
filter filters out jitter by removing glitches from the charge pump and preventing voltage
over-shoot.

A divide counter (M) is inserted in the feedback loop to increase the VCO frequency above
the input reference frequency. VCO frequency (FVCO) is equal to (M) times the input
reference clock (FREF). The PFD input reference clock (FREF) is equal to the input clock (FIN)
divided by the pre-scale counter (N). Therefore, the feedback clock (FFB) applied to one input
of the PFD is locked to the FREF that is applied to the other input of the PFD. The VCO output
feeds post-scale counters which allow a number of harmonically related frequencies to be
produced within the PLL.

The output frequency of the PLL is equal to the VCO frequency (FVCO) divided by the post-
scale counter (C).

In the form of equations:

 FREF = FIN / N
 FVCO = FREF × M = FIN × M/N
 FOUT = FVCO / C = (FREF × M) / C = (FIN × M) / (N × C)

Where:

 FVCO = VCO frequency

 FIN = input frequency
 FREF = reference frequency
 FOUT = output frequency
 M = counter (multiplier), part of the clock feedback path
 N = counter (divider), part of the input clock reference path
 C = post-scale counter (divider)

     The PLL is a very interesting and useful building block available as single integrated circuits from
several well known manufacturers. It contains a phase detector, amplifier, and VCO, see Fig. 1 and
represents a blend of digital and analogy techniques all in one package. One of its many applications
and features is tone-decoding.
There has been traditionally some reluctance to use PLL's, partly because of the complexity of
discrete PLL circuits and partly because of a feeling that they cannot be counted on to work reliably.
With inexpensive and easy-to-use PLL's now widely available everywhere, that first barrier of
acceptance has vanished. And with proper design and conservative application, the PLL is as reliable
a circuit element as an op-amp or flip-flop.
Fig. 2 shows the classic configuration. The phase detector is a device that compares two input
frequencies, generating an output that is a measure of their phase difference (if, for example, they
differ in frequency, it gives a periodic output at the difference frequency). If  fIN doesn't equal  fVCO,
the phase-error signal, after being filtered and amplified, causes the VCO frequency to deviate in the
direction of  fIN . If conditions are right, the VCO will quickly "lock" to  fIN maintaining a fixed
relationship with the input signal.

PLL Components
Phase Detector: Let's have a look at the basic phase detector.
There are actually two basic types, sometimes referred to as
Type I, and Type II. The Type I phase detector is designed to be
driven by analogy signals or digital square-wave signals,
whereas the Type II phase detector is driven by digital
transitions (edges). They are typified by the most common used 565 (linear Type I) and the CMOS
4046, which contains both Type I and Type II.
The simplest phase detector is the Type I (digital), which is simply an Exclusive-OR gate (see Fig. 5a.).
With low-pass filtering, the graph of the output voltage versus phase difference is as shown, for
input square-waves of 50% duty-cycle. The Type I (linear) phase detector has similar output-voltage-
versus-phase characteristics, although its internal circuitry is actually a "four-quadrant multiple
General Features and Applications:
 200ppm/°C frequency stability (drifting) of the VCO
 Power supply range of 5 to 12 volts with 100ppm/% typical
 0.2% linearity of demodulated output
 Frequency range 0.001 Hz to 500 KHz
Highly linear triangle wave output
 Linear triangular wave with in phase zero-crossings available
 TTL and DTL compatible phase detector input and square wave output
 Adjustable hold in range from 1% to more than 60%