IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO.

1, JANUARY 2007 247

Performance Improvement of Shunt Active

Power Filter With Dual Parallel Topology
Lucian Asiminoaei, Member, IEEE, Cristian Lascu, Frede Blaabjerg, Fellow, IEEE, and Ion Boldea, Fellow, IEEE

Abstract—This paper describes the control and parallel oper-

ation of two active power filters (APFs). Possible parallel oper-
ation situations of two APFs are investigated, and then the pro-
posed topology is analyzed. The filters are coupled in a combined
topology in which one filter is connected in a feedback loop and the
other is in a feedforward loop for harmonic compensation. Thus,
both active power filters bring their own characteristic advantages,
i.e., the feedback filter improves the steady-state performance of
the harmonic mitigation and the feedforward filter improves the
dynamic response. Another characteristic of the proposed topology
is the possibility of joint operation of both filters either as fre-
quency-sharing or load-sharing, with or without redundancy. The
frequency-sharing operation is possible due to the control algo-
rithm, which is based on selective harmonic compensation using
equivalent harmonic integrators. Implementation details and a dis-
cussion on the efficiency improvement for various switching fre-
quencies are provided. The evaluation of the proposed topology
concludes that this approach is very practical for achieving both
low and high order harmonic compensation and stable grid op-
eration. This is supported by extensive measurement results on a
15-kVA laboratory setup, indicating a reduction in total harmonic
current distortion from the existing 30% to less than 2% for a typ-
ical adjustable speed drive application.
Index Terms—Active filters, harmonic analysis, interconnected
power systems, power system harmonic, pulse width modulated in-
verters.
I. INTRODUCTION
T is a fact that the continuous proliferation of power elec-
I tronic equipment either for residential or industrial appli-
ances has the drawback of increasing the nonsinusoidal currents
flowing into the power network [1]. Different harmonic miti-
gation solutions are currently proposed and used [2] involving
passive power filters, active power filters, or different other so-
lutions [3]. In the last decade, the use of active power filters
techniques has become more attractive due to the technological
progress in the power switching devices, digital signal proces-
sors (DSPs), numerical methods, and new control algorithms.
As a result, if initially the active power filters were tested mainly
Manuscript received May 12, 2006; revised November 1, 2006. This paper
was presented at the 37th IEEE Power Electronics Specialist Conference, Jeju,
Korea, June 18–22, 2006. Recommended for publication by Associate Editor P.
Krein.
L. Asiminoaei is with Danfoss Drives A/S, Graasten DK-6300, Denmark
(e-mail: las@danfoss.com).
C. Lascu and I. Boldea are with the Faculty of Electrical Engineering,
University “Politehnica” of Timisoara, Timisoara RO-1900, Romania (e-mail:
cristi@et.upt.ro; boldea@lselinux.upt.ro).
F. Blaabjerg is with the Institute of Energy Technology, Aalborg University,
Aalborg DK-9220, Denmark (e-mail: fbl@iet.aau.dk).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2006.888912
0885-8993/$20.00 © 2006 IEEE
Fig. 1. General block diagram of a shunt APF connected in (a) feedforward
loop detecting the harmonic current at the load side and (b) feedback loop de-
tecting the harmonic current at the source side.
in the laboratory conditions, now they are more and more im-
plemented in real-life applications.
Typically, a shunt active power filter (APF) is used for miti-
gation of the harmonic currents by connecting it either directly
to the non-linear load or to the point of the common coupling
(PCC), depending on which case is the most profitable in terms
of power losses, system stability and investment. The APF de-
tects the harmonic content in the load current, here an adjustable
speed drive (ASD), and produces such a current that, once in-
jected into the grid, it cancels the harmonic currents and leaves
only the fundamental to be supplied by the power system.
There are two types of harmonic compensation loops for an
APF, either feedforward or feedback loop as it can be seen in
Fig. 1.
The feedforward control loop is very common in APFs
mainly because of its good stability [3] and straightforward
installation, but it is prone to higher errors in the harmonic
compensation if the loop has many uncompensated delays [4].
The feedback control, instead, yields much better performance
in the stationary conditions but, on the other hand, it may
become unstable especially, for unknown grid conditions [4],
[5].
Thus, it seems that a combination of feedback and feedfor-
ward topologies together may give better performance com-
pared to a typical implementation of just a single feedforward
APF. A similar approach is also proposed in [5] where the APF
is a single unit inverter with combined control using feedfor-
ward and feedback loops together. In [5] the power inverter is
a single unit, therefore the dynamic performance of the APF
is imposed by the front-end inductor. A lower inductor gives a
higher dynamic but on the other hand it also increases the total
current ripple.
This paper proposes a structure for shunt APF that consists
of two parallel inverters separately controlled as active power
filters, where the first is connected in feedback and the second

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248 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

Fig. 2. Simplified diagram of the proposed shunt APF topology with feedback
and feedforward loops. The current sensor is placed in between the connection
points of each inverter to the power system.

in feedforward loop (Fig. 2). The proposed topology provides

several advantages compared to a single unit inverter APF. One Fig. 3. Possible combinations of two APFs connected as (a) and (b) both in
feedforward, (c) and (d) both in feedback, (e) and (f) one in feedforward and
characteristic is that the total loading of harmonic compensa- one in feedback loops.
tion can be shared between inverters. For example the feedback
APF can be of high power, dedicated for compensation of the
lower order harmonics and also for isolation of possible un- The transfer functions and are the open loop
wanted resonance from the grid. The feedforward APF, which transfer functions of each inverter system (which include the
may be configured for faster dynamics, can be used to compen- inner current controller , equivalent delays due to DSP
sate for higher order harmonics and even for transient conditions and PWM inverter ), defined as (see also
not mitigated by the other APF. Fig. 2)
Another new characteristic that can be achieved by the pro-
posed structure is the reduction of the line current ripple if the
inverters have the same switching frequency, and their carriers
are interleaved by 180 . The reduction of the switching ripple (1)
injected into the grid minimizes the high frequency losses in the
power line, the electromagnetic interference (EMI) and the size
of the switching ripple filter.
The paper describes the proposed structure in respect to the
hardware implementation and the control algorithms used for
the harmonic current compensation. The proposed topology and (2)
the control algorithms are sustained by practical measurements
on a laboratory setup with total rated power of 15 kVA at 400 V.

II. DESCRIPTION OF APF PARALLEL TOPOLOGY where: and are the transfer functions of the inner
current controllers (equivalent generalized integrators), as they
A. Selection of the Topology will be defined in Section III; and are each
inverter’s equivalent gain; and are the switching pe-
By using two separate inverters, different topologies may be riods of each inverter. Here it is assumed that the A/D sampling
configured as it is illustrated in Fig. 3. Dependent on the place- frequency is the same as the PWM switching frequency.
ment of the harmonic current sensor, either one or both APFs Further, the equations that hold for the feedforward APF (see
can be configured in feedforward or feedback loop. also Fig. 2) can be written as
Regarding the feedforward APF topology the most common
control method is the current-controlled source. On the other
(3)
hand it is proven in literature that the feedback APF topology
provides a better transient response operating as voltage-con-
trolled source [6]. Thus, for the analysis carried out in Fig. 3 the which gives
feedforward APF is controlled as a current source and the feed-
back APF is controlled as a voltage source. (4)

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ASIMINOAEI et al.: PERFORMANCE IMPROVEMENT OF SHUNT ACTIVE
TABLE I
CALCULATION OF THE LINE CURRENT I FOR EACH CASE IN FIG. 3
For the feedback APF
(5)
which gives
(6)
Thus, one may describe the resultant line current as a func-
tion of the initial harmonic current from the ASD and the ex-
isting source voltages ( and , i.e., fundamental respective
harmonic voltages from the grid side). The analytical expression
of the line current determined for all six topologies in Fig. 3
is given in Table I.
As it can be noticed the line current in case-(a) does not
depend on the existing voltage harmonic distortion, and the re-
sultant transfer function is the direct effect of each individual
transfer function of the active power filters. Case-(c) is useful
for damping the resonances between the grid and possible ac-ca-
pacitor at the load side, because both and give the
effect of a damping in series with the grid impedance. However,
the harmonic current mitigation directly depends on the filter’s
inductances, which may create design restrictions depending on
the grid impedance value . For case-(b) and case-(d), the com-
mand law depends on the imposed reference and
for each filter, which is useful for sharing the loading between
filters, during different operating conditions. Case-(f) achieves
better harmonic mitigation compared to case-(e) regarding the
influence of the harmonic grid voltages .
Furthermore, for case-(b), case-(d) and case-(f), the schemes
use just one pair of harmonic detection sensors, which reduce
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249
the complexity of the hardware design, the number of analog
digital (AD) converters and possible the speed of the calcula-
tions.
However, case-(b) and case-(d) require a careful design re-
garding the imposed harmonic current references. In the sim-
plest way the reference can be given as half of the measured
harmonic current for each inverter, but then both inverters must
be rated at the same nominal power. For other references values,
additional processing is necessary in order to correctly balance
the reference signals and as it is shown in Fig. 3.
Finally, the actual study selects only the topology shown in
case-(f).
B. Description of the Selected Topology (Case-f)
The proposed topology is shown in Fig. 2. As it can be no-
ticed, the APF is composed of two separate inverters, each of
them using independent current and voltage controllers. To min-
imize the cost this structure may be furthermore reduced by
connecting the inverters together on the dc-link [4]. Thus, only
one dc-link capacitor would be needed and implicitly a single
voltage controller. However, it makes the hardware design and
the control more complicated, as a zero sequence current cir-
culates between inverters [7]. In order to break the circulation
path of the zero sequence currents between inverters, a galvanic
isolation is inserted by means of either isolating transformer or
separate dc-capacitors. Thus, the inverters can be independently
controlled.
The load current sensor for harmonic detection is placed in
between the connection points of the inverters, thus achieving
a feedback path for the first inverter (PWM inverter 1), and a
feedforward path for the second inverter (PWM inverter 2). This
new topology may allow each inverter to perform different tasks,
depending of the imposed current references.
250
Thegenerationofharmonicreferencecurrentisdoneinmaster-
slave configuration, as the first inverter dictates the harmonic ref-
erence of the second. Two separate master-slave configurations
can be implemented, one is the harmonic-sharing and the other is
the load-sharing control. In the harmonic-sharing mode the first
inverter mitigates only several harmonic currents, and the second
inverter takes care of the rest of the harmonic spectrum.
It is also possible to operate the filters in load-sharing mode,
when both filters compensate the same harmonic spectrum but
with different imposed reference amplitudes. If the harmonic
reference is equally divided between inverters then each takes
50% of the total required power. Other ratio of harmonic refer-
ences in each inverter is also possible and useful for inverters
with different rated powers or when it is desired to control the
distribution of the power losses, but the reference generation al-
gorithm is more complicated.
A third possibility is to configure the proposed topology in a
redundant-mode, which is a benefit provided by the proposed cas-
caded configuration. The redundant-mode is a particular case of
the load-sharing mode, when the harmonic reference is not di-
vided between inverters but set at maximum for only one inverter.
Thus, APF1 has the task of the main harmonic compensator. Since
APF2 follows APF1, when APF1 ceases its harmonic mitigation,
APF2 automatically can take over, if it is configured to do so. This
offers a wireless independent control feature, because there are
no connectivity wires between the inverters to change informa-
tion about the internal variable or states of each control loop. Each
APF’s control is only based on information available locally at
the inverter terminals. However, the redundant-mode implies that
the rated power of APF2 is sufficiently large to cover the overall
harmonic mitigation, which may not be cost-effective.
In order to optimize the cost, one may use the feedback inverter
(PWM inverter 1) to compensate only a part of the harmonic spec-
trum, for instance, the low order harmonics as most of the power
density is contained here. As the compensation is carried out in the
feedback loop, the steady state response is expected to be much
more tolerant to nonlinearities and parameter variation [6].
Consequently, since the inverter is of high rated power a lower
switching frequency is desirable. Regarding the selection of the
switching frequency one choice is to use different switching
frequencies (i.e., APF1 low, APF2 high) in order to have re-
duced power losses but still a good overall harmonic mitigation
performance. Another choice is to use the same switching fre-
quency for both, which allows implementation of interleaving
techniques to reduce the switching frequency ripple, and conse-
quently EMI and the line filter.
In this paper, the second choice was used due to some hard-
ware limitation (APF1 and APF2 have the same switching fre-
quency), but a discussion presented in Section VI analyzes the
potential operational efficiency improvement if APF1 switches
at a lower frequency. In the case when both power inverters
have the same switching frequency, by interleaving their carriers
by 180 it may significantly reduce the line switching current
ripple. Thus, the highest ripple amplitude is seen at a doubled
switching frequency, which is much easier to filter out. As the
frequency of the switching current is higher it gives lower EMI
and is also damped much faster in the power lines due to their
inductive effect.
The feedforward inverter (PWM inverter 2) receives the in-
formation of the harmonic content only after the first inverter
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007
Fig. 4. Principle algorithm of harmonic extraction and reference current con-
trol in synchronous fundamental frame.
has already mitigated part of the harmonic spectrum. The cur-
rent reference for the feedforward APF contains only the har-
monics left in the line currents. The second inverter is designed
for mitigation of high order harmonics. As a result, the second
inverter is configured for a faster dynamic response, thus com-
pensating the slower dynamic of the first inverter (which may
react slowly and imprecisely in transient conditions especially
if its switching frequency is lower).
The entire topology has the advantage of a good harmonic
mitigation in stationary conditions (due to the feedback in-
verter), but also very good response in transient conditions (due
to the faster feedforward inverter) [8]. The power losses of the
second inverter are kept at a lower value since the high order
harmonics are not so large. Another advantage of this topology,
but not tested here, is that the feedback APF can provide an
active damping of existing resonances between the grid and a
possible installed ac-capacitor at the load side, e.g., EMI filter
or custom passive harmonic filter, although this requires an
increased bandwidth of the APF current controller.
III. CONTROL ALGORITHM
The control algorithm is developed in the synchronous funda-
mental reference dq-frame. The input signals, measured in abc-
coordinates (i.e., stationary reference frame), are transformed
into the fundamental -rotating reference frame by means of
the Park transformation
(7)
where , and , , are the currents in the -frame, re-
spective in -frame; and is the angular position of the ref-
erence frame.
The frame rotates at fundamental angular frequency that
makes the fundamental current to appear as dc-component and
the harmonics as ac-signals. Thus, harmonic detection becomes
a matter of removing the dc-signal by means of a high-order
high pass filter [(HPF) in Fig. 4 with a cutoff frequency between
25 Hz and 120 Hz] [9]. The HPF outputs the harmonic current
to be compensated by the active filter. This is a fourth order
filter implemented in fundamental frame, which removes the
fundamental current, i.e., the dc-signal
(8)
where the cutoff frequency is 300 rad/s, and 0.8.
ASIMINOAEI et al.: PERFORMANCE IMPROVEMENT OF SHUNT ACTIVE 251

The reference for the fundamental current controller is re-

ceived from the dc-voltage controllers. The fundamental current
controllers regulate the -axes active current, while
the reactive current on the -axes is set to zero, as in this appli-
cation no reactive power needs to be controlled.
The harmonic current control is realized by separate control
of each harmonic, each controller for one pair 6 1 of
positive and negative sequence harmonics. The total harmonic
reference is the superposition of commands produced by all cur-
rent controllers. Harmonic current controllers are equiv-
alent harmonic integrators, one controller being tuned here for
each harmonic pair 6 1 [10].
In order to control at the same time, a pair of both positive
and negative characteristic harmonics from a typical ASDs with
Fig. 5. Control block diagram of the proposed topology in dq-frame. APF1 has six-pulse diode based front-end rectifier, with a single controller,
a single inner harmonic current controller tuned for mitigation of the 6th har-
monic order in dq-frame (i.e., fifth and seventh in stationary frame). APF2 has
the controller transfer function is selected as in [11]
a multituned inner current controller realized by superposing several harmonic
controllers tuned at orders of 6k in dq -frame. (12)
where and are the proportional and the integral gains
For line synchronization purposes, the line voltages are
of the selected harmonic integrator.
measured, and the line frequency and phase are extracted
Notably, represents the transfer function of an equiv-
by means of a phase locked loop (PLL).
alent harmonic integrator (resonant controller) tuned for fre-
The block diagram of the proposed current control topology
quency (for both negative and positive sequences), which
is shown in Fig. 5.
provides zero gain for the dc-component and infinite gain at the
The control contains one dc-voltage control loop for each
selected frequency . Such type of controller is implemented
APF. The dc-voltage controllers are classical pro-
in fundamental reference frame for each harmonic order , up
portional–integral (PI) units, which receive as inputs the dif-
to the 31st harmonic [12].
ference between the reference voltage and the measured
Finally, the total harmonic current controller is realized as
dc-voltage . The output represents the fundamental active
the superposition of individual controllers given by (12). In a
current references, on the -axis of the synchronous frame
general form the resultant harmonic controller is
(9)
where and are the proportional and the integral
gains of each dc-voltage PI controllers. (13)
The current controllers are, on the other hand, divided for Controller gains are selected so as , and
each APF into two distinct paths: the fundamental current con- of small value in order to create a narrow selectivity, thus
trol and the harmonic current control [11]. avoiding the overlap between the neighbor harmonic controllers.
The APF reference voltage is the sum of all current controller The number of harmonic pairs , which can be compensated
outputs and it is realized by a space vector modulation strategy in this way, can be selected based on the available computa-
(SVM in Fig. 4). tional resources and on the sampling and switching frequency
The fundamental current controller is of a feedback type, [13]–[16].
which provides pole-zero cancellation for this plant, the line The feedback APF1 harmonic current controller is imple-
inductor. Vector model of the line inductor, in synchronous fun- mented as only for equal to 6. For APF1 there
damental frame, is is only a single harmonic controller, i.e., 6, sixth harmonic
order in -frame meaning compensation of fifth and seventh
(10) harmonic currents in stationary frame.
The feedforward APF2 has with
where and are the resistance and inductance of the line 6,12,18,24,30 . The superposition of the individual har-
inductor, is the filter voltage, is the instantaneous filter monic controllers is done by summing the output voltage
current, and is the line voltage vector. reference of each
A complex-coefficient PI controller ( and ),
with cross-coupling decoupling and line voltage feedforward (14)
compensation can be used

(11) (15)
where and are the proportional and the integral
gains of each complex current controllers. if APF2 is set for redundant-mode 1, else 0.

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252 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

Fig. 7. Picture of laboratory setup where the proposed topology is tested.

Fig. 6. Bode plots of (a) open loop transfer functions H s ( ) for APF 1 (b)
open loop transfer function H s ( ) for APF 2, and (c) overall closed loop system
TABLE II
PARAMETERS USED IN CONTROL FOR BOTH INVERTERS APF1 AND APF2
transfer function as in Table I.

By replacing (14) and (15) into the initial open loop transfer
functions of each active filter in (1) and (2), one can deter-
mine the Bode plots of each system as it is given in Fig. 6. The
behavior of the open loop transfer functions , of
each active filter APF1, respectively, APF2 is dominated by the
transfer functions of the harmonic integrators re-
spectively . Therefore, the close loop Bode plot of
the overall system (APF1 together with APF2) looks as a mul-
tiple notch filter tuned for the selected frequency in -frame
[see Fig. 6(c)].
Thus, APF1 mitigates only the lower harmonic currents (fifth
and seventh) the controller having a very high selectivity (i.e.,
low value for gain) in order to determine a precise mitiga-
tion of these harmonics. However, it is known that lower values
of give also a slow dynamic response.
The filter APF2 mitigates the rest of the characteristic har-
monic currents up to 31st order. The selectivity of the equivalent
harmonic integrators is set wider (i.e., higher values for the
gains) in order to cope with the variation of the line frequency.
As the line frequency varies, the harmonics suffer also a small
frequency shift, which it is more severe as the harmonic goes
higher. Thus, in order to provide a better harmonic tracking, it
is advisable to have a wider selectivity of the higher order res-
onant controllers. As the selectivity of the controller is wider,
the dynamic response of the APF2 becomes faster compared to
APF1.
The redundant-mode feature is implemented in the APF2
control by setting 1 [see Fig. 5 and (15)] which enables the
sixth harmonic inner current controller in . This can be
seen in Fig. 6(b) where the open loop transfer function
is plot in two cases, with and without a harmonic integrator
tuned for 300 Hz. If is not tuned for 300 Hz it means
that the filter APF2 cannot mitigate the same harmonics as the
first filter APF1. If is tuned for 300 Hz, it allows APF2
to mitigate also the fifth and seventh harmonics. But since its
mitigation follows after APF1, the effect is similar as sharing
the harmonic load when the first filter APF1 does not fulfill its
task. This may happen in transient conditions due to the slow
response of the APF1 as previously presented.
Another particular case is when the APF1 is programmed to
reduce (but not completely) the amount of mitigated harmonics
due to different operating conditions, which automatically en-
ables the second filter APF2 to take over the harmonic miti-
gation without any special communication between both active
power filters. However, as initially mentioned, in this case the
power rating of the second filter should be sized for that pur-
pose.
IV. IMPLEMENTATION
The proposed topology and control method are tested on a
laboratory setup (Fig. 7) composed of two Danfoss inverters
VLT 5006 rated as 400 V/7.6 kVA each. The switching fre-
quency was set to 12.6 kHz for both inverters. The control algo-
rithm is implemented with a dSpace system DS1103, using the
Matlab/Simulink Real Time Workshop toolbox [17], having the
control parameters set as in Table II.
In practice a proper the design of the inductors depends on
the mitigated harmonic current spectrum and its power level.
A higher power inverter requires a lower inductance in order
to reach lower iron losses. A faster inverter (i.e., compensation
of higher harmonic orders) requires also a lower inductance to

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ASIMINOAEI et al.: PERFORMANCE IMPROVEMENT OF SHUNT ACTIVE
Fig. 8. General diagram of the laboratory setup.
TABLE III
MEASURED HARMONIC CURRENT OF ASD LOAD AT 5.9 kVA POWER
achieve a higher output current gradient . APF1 compen-
sates here only fifth and seventh, but due to the higher power
level of the first inverter its boost inductance is of a lower value.
The second inverter APF2 compensates here the high order har-
monic currents, and even if the inverter is of a smaller power
it still requires a lower inductor to achieve a high bandwidth
and high . The selected values of the boost inductors are
5.6 mH for the feedback APF1 and 3.0 mH for the feedforward
APF2 (Fig. 8).
The nonlinear load that creates the harmonic currents is a
three-phase diode rectifier, which replicates the behavior of a
typical adjustable speed drive (ASD). The rectifier may be set
as dc-smoothed capacitor or inductor by switching “sw1” and
“sw2” such that different cases may be created.
The load is a variable resistor with values between 50–200 .
This way one may create different levels of harmonic currents.
Harmonic distortion created by the ASD is measured as indi-
cated in Table III and Fig. 9, for a typical industrial ASD of a
rated power of 5.9 kVA.
A. Feedback Compensation
This section describes the mitigation performance of only the
APF1-feedback compensation loop (the APF2-feedforward is
disconnected). Here the reference is set for mitigation of only
the fifth and seventh harmonics. As it can be seen in Fig. 10,
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253
Fig. 9. Measured line current and supply voltage when none of the active filters
is running. The line current consists of the ASD current.
Fig. 10. Measured steady-state response of the APF1—feedback compensa-
tion. The harmonic compensation reference is set for mitigation of fifth and
seventh harmonics.
and more detailed in Table V column 3, the reduction of the
fifth and seventh harmonics currents is from the initial values
of 25% respective 8.7% down to 0.2% respective 0.6%. As the
higher harmonics are not compensated, the resultant waveform
of the line current is still distorted (see Fig. 10).
B. Feedforward Compensation
This experiment was carried out with only the APF2-feed-
forward loop (the APF1-feedback is disconnected). The refer-
ence is set for mitigation of the high order harmonics, from 11th
up to 31st. As discussed in Section III the feedforward inverter
is able to take over all harmonic currents, including the fifth
and seventh by enabling the redundant mode [ 1 in (15)].
Two tests are performed with and without this functionality en-
abled, in order to show its harmonic mitigation performance. It
is clear that, if the filter is able to compensate for high order har-
monics, it is also able to compensate for low orders as the fifth
and seventh. However, this feature would require a considerable
increase of the inverter power rating, not evaluated here.
254
TABLE IV
CHARACTERISTICS OF THE PROPOSED TOPOLOGY DEPENDING ON THE DESIRED COMPENSATED
SPECTRUM AND SELECTED SWITCHING FREQUENCY OF EACH INVERTER
Fig. 11. Measured steady-state response of the APF2—feedforward compen-
sation. The harmonic compensation reference is set for mitigation of the high
order (11th to 31st) harmonic currents.
A typical stationary response for the feedforward APF2 is
given in Fig. 11, where the total line current still contains a sig-
nificant quantity of harmonic distortion, but with smoother cur-
rent gradients. As the current spectrum indicates (see Table V
column 5) the APF2 filter compensates only for the harmonic
currents higher than 11th order.
C. Combined Compensation
Different tests can be performed with the proposed topology
depending on the imposed compensated spectrum and the se-
lected switching frequency of each inverter, as it can be seen in
Table IV. In this paper only Case-1 and Case-3 are tested.
First, both feedback and the feedforward loops are connected
together and set as in Case-1, Table IV. The result, seen in the
line current waveform, represents the cumulative effect of both
loops. Thus, both low order and high order harmonics are com-
pensated, as shown in Fig. 12. Table V compares the harmonic
current spectrum for each of the measured cases. The proposed
topology brings the THD from the initial value of 27%, without
any filtering, down to less than 2% with both APF filters active.
The control method uses harmonic integrators, which ideally
present infinite amplification at the selected harmonic. There-
fore, the mitigation performance of each branch should theo-
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007
Fig. 12. Measured steady-state response of the proposed topology. Both low
order and high order harmonic currents are mitigated down to 2% THD , by
enabling APF1 and APF2 together.
retically be identical (see columns 2 and 4). Furthermore, it is
proven in [6], that although some of the gains are different,
the transfer functions of the feedforward and feedback loops
are equivalent. This should give the same harmonic mitigation
performance of the feedback compared to the feedforward re-
spective the proposed topology. However, it is experimentally
noticed that the proposed topology provides a better harmonic
current mitigation, presumably due to the cascade configuration
(see columns 6 respective 7 of Table V). In order to measure the
data presented in columns 2 and 4 of Table V, the control of each
branch APF1 or APF2 is configured as in (13) by enabling all
five orders of the harmonic integrators, 6,12,18,24,30 .
The second test is with the proposed topology set as in Case-3
Table IV, but in a particular case as redundant-mode, which is
done by setting the parameter 1 in (15) and Fig. 5. The
steady state harmonic mitigation performance can be seen in
Table V column 7, which is the best compared to the other pre-
sented cases. Fig. 13 shows the dynamic response of the entire
APF for a load step of 5 kW due to the ASD. Active filter APF1
responds slower because of the lower gain of its equiva-
lent harmonic integrator. Active filter APF2 responds faster and
takes over the compensation of the fifth and seventh harmonics
during the transient. This is possible due the enabled redun-
ASIMINOAEI et al.: PERFORMANCE IMPROVEMENT OF SHUNT ACTIVE 255

TABLE V
COMPARISON OF THE APF’S HARMONIC MITIGATION PERFORMANCE FOR EACH MEASURED
CASE: FEEDBACK, FEEDFORWARD AND THE PROPOSED PARALLEL TOPOLOGY

Fig. 13. Dynamic response of the proposed topology in redundant-mode, for a Fig. 14. Dynamic response of the proposed topology in redundant-mode, when
load step of 5 kW created by the ASD. APF1 responds slower than APF2 due the APF1 is powered on while APF2 was compensating the overall harmonic
to different parameters set for the current controller. current spectrum. Once APF1 becomes active APF2 keeps its main task of com-
pensating only the higher harmonic orders.

dant-mode as it is also shown in Fig. 6. As APF1 reaches the

steady-state conditions, APF2 ceases to mitigate the fifth and
seventh harmonic currents.
Another measurement with the redundant-mode is presented
in Fig. 14, with APF1 starting up (reproducing a possible
maintenance intervention when APF1 had to be stopped and
restarted). Fig. 14 shows the dynamic response of the proposed
topology when APF1 starts. The active filter APF2 is running,
replacing the harmonic mitigation tasks of APF1. As soon as
APF1 becomes active, both active filters return to normal oper-
ation (i.e., APF1 takes out lower harmonics and APF2 higher
harmonics), due to the load-sharing feature. As APF1 has to
start from zero-conditions, its dc-voltage has to be increased
to the reference value, which explains the fundamental current
drained at the beginning. As it can be seen the output current of
both APF inverters are similar, which means that both must be
sized to withstand the maximum harmonic current.

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256 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007

TABLE VI
COMPARISON OF A SINGLE UNIT INVERTER AND THE PROPOSED DUAL PARALLEL
TOPOLOGY OPERATING EITHER IN HARMONIC-SHARING OR LOAD-SHARING MODE

V. DISCUSSION For the given case the measured THD is 27%, while the fifth
As the active filtering device proposed here is composed from and seventh gives a THD 26% for APF1 and the higher
two inverters, one may argue if this is economically feasible. It harmonic currents 11th up to 31st give a THD 6% for
is expected that two inverters are more expensive than a single APF2
one, as each inverter has to contain its own gate-drives, insulated THD
gate bipolar transistor (IGBT) switches, snubbers, logic-control
THD (17)
and protection circuits.
The costs of the gate-drives, and the control and protection As it can be seen, the second inverter is of a smaller power, i.e.,
circuits are fairly lower compared to the power switches. Thus, 10%–50% of APF1, which in turn means a relatively lower cost.
they can be neglected, since nowadays there is a large diversity An interesting discussion is also the potential operational ef-
of cost-effective integrated modules on the market. ficiency improvement between the harmonic-sharing and load-
Therefore, the most expensive components are considered the sharing modes. In harmonic-sharing mode APF1 may switch at
power switches and the passive components: boost inductor lower frequency, sufficiently to handle the low order harmonics,
and dc-capacitor , which are all sized based on the designed and APF2 switches at higher frequency to handle the higher
rated power of the inverters. order harmonics. In load-sharing mode APF1 and APF2 switch
An estimation of the designed rated power of the inverter is at high frequency and each may be set to take care half of the
the inverter kVA rating, calculated based on the inverter root- harmonic current. An estimate of the efficiency is determined
mean-square (RMS) output current. The ampere requirement of here based on the estimation of the switching losses in IGBTs.
the power switches is determined by the peak current and not the The IGBT’s conduction losses and the losses in the passive com-
RMS value, thus large IGBTs may still be required depending ponents are not evaluated.
on the load current behavior. However, as the RMS value of the Evaluation of the switching losses is done in the same way as
current determines the inverter power losses and consequently in [18], assuming that the inverter has a linear switching loss de-
the size, volume and costs of the active and passive components, pendency with the amplitude of the current. The average value
a simplified assumption is considered here, that the cost of the of the switching power losses over the fundamental pe-
inverter is mainly determined by its kVA rating. riod is defined in (18). Further, (19) is derived assuming that
For a single unit inverter the designed rated power of the in- the energy losses due to commutation are proportional to
verter is turn-on and turn-off durations and the absolute value of
the output filter current . The filter current may be expressed
THD
in a similar way as in (16) depending on the ASD current and
THD (16) its THD , which is constant for a given case. The power losses
can be related to the switching frequency and the inverter cur-
where and are the power of the APF respective the rent THD as in
ASD; and are the RMS current of the APF
respective the fundamental current of the ASD; and
is the total harmonic current distortion from the ASD.
For the proposed topology, because the harmonic power is di- (18)
vided between two inverters, the RMS current in each inverter
is lower than as for a single unit inverter. Thus, the total rated
power of each inverter is reduced. The second inverter APF2
compensates only the higher harmonics, which have a lower
spectral power compared to the fifth and seventh, in ASD’s ap- (19)
plications, therefore, the rated power of the second inverter is
lower.
Table VI shows the theoretical and the measured THD from THD (20)
nonlinear load. In the actual case the measured THD has a
lower content of higher harmonics due to the 3% front inductor where is the dc-voltage, and are the turn-on re-
in series with the ASD. spective turn-off intervals, is the switching frequency,

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ASIMINOAEI et al.: PERFORMANCE IMPROVEMENT OF SHUNT ACTIVE 257

Fig. 15. Estimated efficiency limit based on the switching frequency and the Fig. 16. Steady-state response of the APF filters’ currents and their duty-cycles.
load current THD .

is output inverter current, which can be expressed as a function overall smaller power, even though the efficiency may not be
of the load current and filter THD , is a constant very high. The efficiency of the harmonic-sharing mode is
including all other constant parameters, and is the abso- attractive only if the switching frequency of the APF1 inverter
lute value function. (mitigating the lower order harmonics) is at maximum two
Assuming that in the harmonic-sharing mode the inverter times smaller than the switching frequency of the APF2 inverter
switches at a lower frequency, the switching losses of APF1 (mitigating the higher order harmonics).
inverter are reduced by a factor of As it was previously mentioned, another advantage of the
topology is that, having two separately controlled inverters, they
THD can be interleaved by 180 , to reduce the line switching current
THD (21) ripple.
Fig. 16 shows the filter currents and along with their
Switching losses in harmonic-sharing mode are duty-cycles. It can be noticed that, even the output currents are
different, the duty-cycles look similar. This is because the in-
THD THD verter voltage must be comparable to the line voltage in order
(22) to make the current flowing through the line inductors. Thus,
the duty-cycles contain a fundamental component that makes
Switching losses in load-sharing mode are equally distributed their waveforms to resemble. This property is used to reduce
between inverter the switching ripple of the line current if one uses two carriers
THD (23) shifted by 180 . A simplified illustration of the interleaving is
provided in Fig. 17 for one phase only. The amplitude of the
The efficiency improvement of the harmonic-sharing compared current ripple in each inverter depends on the used inductors.
to load-sharing mode is estimated as Furthermore, even though the carriers are interleaved by
THD THD 180 , the duty-cycles are ac-signals, therefore determining
different pulse width lengths in each inverter. Thus a complete
THD cancellation of the current ripple at the switching frequency
(24) is not possible. However, the interleaving helps in minimizing
Fig. 15 gives a graphical interpretation of (24), as a function of the total line current ripple. The switching frequency is only
the switching frequency factor . partially canceled, as it can be seen in Fig. 18, which reduces
Thus, assuming a reduction by half of the switching fre- the requirement of a stronger line filter against EMIs. A smaller
quency, i.e., 0.5, the efficiency improvement of the EMI filter is assumed to be inexpensive, as it requires smaller
harmonic-sharing is line connected capacitors. Furthermore, smaller capacitors
mean an increase of the system stability, because possible
for theoretical
power system resonances between the capacitors and source
ASD model for measured data (25) impedances are shifted to higher frequencies. The resonances
may be easily damped and may not interfere with the control.
One may determine the boundary limit of the switching fre- If the rated power of APF2 is of a small value, as it is cal-
quency where the efficiency of the harmonic-sharing is lower culated in (17), then the load-sharing feature cannot be used.
compared to the load-sharing. Considering also the data in Therefore, one may need to assign a higher rated power for the
Table VI, it seems that in load-sharing the inverters have an second inverter (APF2), in order to operate in load-sharing. This

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258
Fig. 17. Simplified description of the current ripple based on the on-off con-
duction instants with the carriers interleaved by 180 .
Fig. 18. Harmonic spectrum of the filters’ currents and total line current. Spec-
trum shows the reduction of the switching frequency f in the source current
I due to 180 interleaved carriers.
means a higher cost for the second inverter, but the advantage
is the achievement of redundancy and ride-through functions
when one inverters fails. The ratio of the inverter’s size becomes
a matter of practical design. For instance if APF2 is only used
for mitigation of transient conditions due to slower APF1 re-
sponse, then its rated power may be selected in the range of
25%–50% of APF1 power. If APF2 is going to be permanently
used for load-sharing, then its rated power would be comparable
to APF1.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 1, JANUARY 2007
VI. CONCLUSION
This paper describes a new topology for dual operation of ac-
tive power filters. The novelty consists in a parallel connection
of two active filters, one working in feedforward current loop
and the other in feedback current loop, both sharing the same
load current sensor. The proposed topology is theoretically an-
alyzed and then practically tested on a laboratory platform.
The most significant features of the proposed solution are as
follows.
— It improves the stationary performance compared to an
APF based on a single inverter.
— It provides an improved dynamic response in frequency-
sharing operation due to the fact that one filter is pro-
grammed for fast compensation, while the other is effec-
tive in stationary operation.
— Load distribution with or without redundancy is possible
in load-sharing operation.
— Wireless operation of the two filters is an intrinsic property
of this topology in all operating situations.
— Current ripple reduction is possible and was confirmed in
interleaving operation.
— The overall achieved THD performance is below 2% from
uncompensated THD value of 27%.
The proposed solution is targeted for medium power Ad-
justable Speed Drives applications where the harmonic pollu-
tion is a significant issue.
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Lucian Asiminoaei (S’03–M’06) was born in
Galati, Romania, on April 3, 1973. He received the
B.Sc. and M.Sc. degrees in electrical engineering
from “Dunarea de Jos” University of Galati, in 1996
and 1997, respectively, and is currently pursuing the
Ph.D. degree at the Institute of Energy Technology,
Department of Power Electronics and Drives, Aal-
borg University, Aalborg, Denmark.
From 1996 to 1999, he was with Iron & Steelworks
Sidex S.A., Galati, as a Maintenance Engineer and in
1999 moved to the IT Department, IspatSidex LNM
Group, Galati, as a Hardware Engineer. In February 2003, he joined the Institute
of Energy Technology, Department of Power Electronics and Drives, Aalborg
University, and is involved in projects sponsored by Danfoss Drives A/S, Den-
mark and Power Lynx A/S, Denmark. His areas of interests include harmonic
mitigation, harmonic measurement, and design of active and hybrid filters.
Cristian Lascu received the M.S. and Ph.D. de-
grees in electrical engineering from the University
Politehnica Timisoara, Timisoara, Romania, in 1995
and 2002, respectively.
In 1995, he joined the Department of Electrical
Engineering, University Politehnica Timisoara where
his research was focused on power electronics and
high performance electrical drives. He was a Visiting
Researcher at the Institute of Energy Technology,
Aalborg University, Aalborg East, Denmark, in 1997
and 2005, and with the Department of Electrical
Engineering, University of Nevada, Reno, from 1999 to 2000. From 2002 to
2004, he was with SIEI S.p.A., Italy, working on advanced power electronics
and drives for electrical vehicles under a European Marie Curie Fellowship.
Dr. Lascu received the IEEE IAS Prize Paper Award in 1998.
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259
Frede Blaabjerg (S’86–M’88–SM’97–F’03) was
born in Erslev, Denmark, on May 6, 1963. He
received the M.Sc.EE. and Ph.D. degrees from
Aalborg University, Aalborg, Denmark, in 1987 and
1995, respectively.
He was with ABB-Scandia, Randers, Denmark,
from 1987 to 1988. He became an Assistant Pro-
fessor in 1992 at Aalborg University, in 1996 an
Associate Professor, and in 1998 a Full Professor
in power electronics and drives. In 2000, he was a
Visiting Professor with the University of Padova,
Padova, Italy, as well as a part-time Programme Research Leader in wind
turbines at the Research Center Risoe. In 2002, he was a Visiting Professor
at Curtin University of Technology, Perth, Australia. He is involved in more
than ten research projects within the industry. Among them is the Danfoss
Professor Programme in Power Electronics and Drives. He is the author or
coauthor of more than 350 publications in his research fields including Control
in Power Electronics (New York: Academic, 2002). He is an Associate Editor
for the Journal of Power Electronics and Elteknik. He has been very involved in
Danish Research policy in the last ten years. His research interests are in power
electronics, static power converters, ac drives, switched reluctance drives,
modeling, characterization of power semiconductor devices and simulation,
wind turbines, and green power inverters.
Dr. Blaabjerg received the 1995 Angelos Award for his contribution in
modulation technique and control of electric drives, the Annual Teacher Prize
from Aalborg University, in 1995, the Outstanding Young Power Electronics
Engineer Award from the IEEE Power Electronics Society in 1998, five IEEE
Prize paper awards during the last five years, the C. Y. O’Connor fellow-
ship from Perth, Australia in 2002, the Statoil-Prize for his contributions in
power electronics in 2003, and the Grundfos-prize for his contributions in
power electronics and drives in 2004. He is an Associate Editor of the IEEE
TRANSACTIONS ON INDUSTRY APPLICATIONS and the IEEE TRANSACTIONS ON
POWER ELECTRONICS. He is a member of the Danish Academy of Technical
Science, the European Power Electronics and Drives Association, and the
IEEE Industry Applications Society Industrial Drives Committee. He is also a
member of the Industry Power Converter Committee and the Power Electronics
Devices and Components Committee, IEEE Industry Application Society.
Ion Boldea (M’77–SM’81–F’96) received the B.S.
and Ph.D. degrees in electrical engineering from the
University Politehnica, Timisoara, Romania, in 1967
and 1973, respectively.
He is currently a Full Professor at the University
Politehnica Timisoara. He has worked and published
extensively on linear and rotary electric machines
and their power electronics control, with and without
motion sensors. He co-authored Induction Machine
Handbook (Orlando, FL: CRC, 2001), Linear Motion
Electromagnetic Devices (London, U.K.: Taylor &
Francis, 2001), Electric Drives (Boca Raton, FL: CRC, 2006), and The Electric
Generators Handbook (Boca Raton, FL: CRC, 2006). He spent about five years
as a Visiting Scholar in the U.S. and U.K., and presented keynote addresses,
intensive courses, and does consultant work in the U.S., Europe, and Asia. He is
Associate Editor of the Electric Power Components and Systems Journal, and
Director and Founder of the Internet-only, Journal of Electrical Engineering.
Dr. Boldea is an active member of the Industrial Drives and Electric Machines
Committee, IEEE Industry Applications Society, and Co-chairman of the IEEE
IAS Technically Sponsored OPTIM 96, 98, 00, 02, 04, and 06 International
Conferences.