Register No.

: 20BLC1123 Name: Jaswanth Sai K R

Date: 05/08/2021 Exp 1. Study and verification of Basic Logic Gates

Implementation of simple Boolean Expressions .

Aim: Verify the truth table for AND , OR , NOT, NAND ,XOR and NOR
and verify the same for three Boolean expressions.

Software Required: Logic Gate Simulator.

Procedure:

1. Place the USER-INPUT blocks in the platform of the Logic Gate

Simulator according to the number of inputs required for the
Boolean expressions.
2. Place the required gates in the platform and connect the USER-
INPUT blocks to the gates.
3. Place the USER-OUPUT block near the gate and connect them.
4. Switch the input form ON to OFF and vice versa and verify the
truth table.
5. Acquire the Boolean expressions and verify the truth table of the
three Boolean expressions.

LOGIC Diagram:

1. AND GATE
Register No.: 20BLC1123 Name: Jaswanth Sai K R

2. OR GATE

3. NOT GATE

4. NOR GATE

5. NAND GATE
Register No.: 20BLC1123 Name: Jaswanth Sai K R

6. XOR

7. Question 1) a)
Register No.: 20BLC1123 Name: Jaswanth Sai K R

Question 1)b)

Question 1)c)
Register No.: 20BLC1123 Name: Jaswanth Sai K R

OUTPUT AND TRUTH TABLE:

1. AND GATE

A B Output Logic gate diagram

0 0 0

0 1 0

1 0 0
Register No.: 20BLC1123 Name: Jaswanth Sai K R

1 1 1

2. OR GATE

A B Output Logic gate diagram

0 0 0

0 1 1

1 0 1

1 1 1

3. NOT GATE
Register No.: 20BLC1123 Name: Jaswanth Sai K R

A Output Logic gate diagram

0 1

1 0

4. NOR GATE

A B Output Logic gate diagram

0 0 1

0 1 0

1 0 0

1 1 0

5. NAND GATE
Register No.: 20BLC1123 Name: Jaswanth Sai K R

A B Output Logic gate diagram

0 0 1

0 1 1

1 0 1

1 1 0

6. XOR GATE

A B Output Logic gate diagram

0 0 0
Register No.: 20BLC1123 Name: Jaswanth Sai K R

0 1 1

1 0 1

1 1 0
Register No.: 20BLC1123 Name: Jaswanth Sai K R

7. Question 1) a)
Expression is Y = AB’+AC’

A B C B’ C’ AB’ AC’ Y=AB’+A Diagram

C’
0 0 0 1 1 0 0 0

0 0 1 1 0 0 0 0

0 1 0 0 1 0 0 0

0 1 1 0 0 0 0 0

1 0 0 1 1 1 1 1

1 0 1 1 0 1 0 1

1 1 0 0 1 0 1 1

1 1 1 0 0 0 0 0
Register No.: 20BLC1123 Name: Jaswanth Sai K R

Question 7) b)
Expression is Q = ABC+A(B’+C’)

A B C B’ C ABC B’+C’ A(B’+C’) Q=ABC Diagram

’ +
A(B’+C’)
0 0 0 1 1 0 1 0 0

0 0 1 1 0 0 1 0 0

0 1 0 0 1 0 1 0 0

0 1 1 0 0 0 0 0 0

1 0 0 1 1 0 1 1 1

1 0 1 1 0 0 1 1 1

1 1 0 0 1 0 1 1 1

1 1 1 0 0 1 0 0 1
Register No.: 20BLC1123 Name: Jaswanth Sai K R

Question 1) c)
Expression is X = M+M.C+A.M+A.C+A.M.C

A M C A.M M.C A.C A.M.C M+M. X=A.M+M. Diagram

C C+A.C
0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0

0 1 0 0 0 0 0 1 0

0 1 1 0 1 0 0 1 1

1 0 0 0 0 0 0 0 0

1 0 1 0 0 1 0 0 1
Register No.: 20BLC1123 Name: Jaswanth Sai K R

1 1 0 1 0 0 0 1 1

1 1 1 1 1 1 1 1 1

Result:

The circuit of the gates AND, OR ,NOT, NOR, NAND and XOR are
designed and the truth tables of the gates are verified. The same is
verified for the three Boolean expressions.