Name:

KHAIRUL RAZMAN BIN MOHD RAZALI

2009485736

Group:

EE2106A

Lecturer’s Name:

PN WAN FAZLIDA HANIM

Current reference circuit for short-channel devices.
1) Beta-Multiplier reference circuit without differential
amplifier.

Schematic

Figure 1.1: BMR circuit without differential amplifier.

The circuit above shows a current reference circuit for short-channel devices current using the
beta multiplier reference circuit architecture with start-up circuit included at the left side. The start-up
circuit use to trigger the reference circuit to start functioning. The operation occurs when the gates of
M1/M2 are at ground while gates of M3/M4 are at VDD. The MSU1 is off and MSU2 is between VDD
and VDD-VTHP. MSU3 be like an NMOS switch, turns on and leak current to gates M1/M2 from gates
M3/M4. This cause current to snap to desired state then MSU3 turn off. During normal operation the
start-up circuit will not affect BMR circuit.
Test-bench schematic

Figure 1.2: Test-bench of BMR circuit without differential amplifier.

The circuit in Figure 1.1 was generate to symbol then a test-bench schematic was create as shown
at Figure 1.2 where the voltage supply is added with VDD=1.8V. The test-bench circuit was simulated to
get the netlist and output waveform using DC analysis as shown below.
Netlist
*
* .CONNECT statements
*
.CONNECT GROUND 0
.CONNECT VSS 0
* ELDO netlist generated with ICnet by 'aic4' on Tue Mar 22 2011 at 17:55:50
*
* Globals.
*
.global VSS VDD
*
* Component pathname : /home/aic4/assignment4/question1
*
.subckt QUESTION1 VBIASP VBIASN
M3 VBIASN VBIASP VDD VDD php L=0.36u W=18u M=1
MSU3 VBIASP N$828 VBIASN VSS nhp L=0.18u W=1.8u M=1
R1 N$206 VSS 6.5K
MSU2 N$828 N$828 VDD VDD php L=3.6u W=1.8u M=1
M4 VBIASP VBIASP VDD VDD php L=0.36u W=18u M=1
MSU1 N$828 VBIASN VSS VSS nhp L=0.36u W=9u M=1
M1 VBIASN VBIASN VSS VSS nhp L=0.36u W=9u M=1
M2 VBIASP VBIASN N$206 VSS nhp L=0.36u W=36u M=1
.ends QUESTION1
*
* MAIN CELL: Component pathname : /home/aic4/assignment4/BMR_tb
*
V1 VDD VSS DC 1.8V
X_QUESTION11 N$2 N$1 QUESTION1
*
.end
Waveform output

Figure 1.3: Graph Iref vs Vdd

The graph shows how the reference currents vary with VDD. At VDD = 1.2V the reference
circuit is 8µA. With only the BMR circuit, the reference current will varies with VDD value which is not
good. To reduce the sensitivity, others circuit need to be added.
 2) Beta-Multiplier reference circuit with differential amplifier
without compensation capacitor.

Schematic

Figure 2.1: BMR circuit with differential amplifier without compensation capacitor.

The circuit above shows a BMR circuit with differential amplifier added at the middle to reduce
the sensitivity of current reference due to change of VDD. M4 is no longer gate-drain connected so its
drain can move to the same potential as M2’s drain, which is Vbiasn. Amplifier used to compare the Vd
of M1 (Vbiasn) with Vd of M2’s output resistance. The output resistance, R1 lowered from 6.5k to 6.2k
to get the desired current output equal to 8µ.
 Test-bench schematic

Figure 2.2: Test-bench of BMR circuit with differential amplifier without compensation capacitor.

The circuit in Figure 2.1 generated to symbol then a test-bench schematic was create as shown at
Figure 2.2 where the voltage supply and pulse signal are added. The test-bench circuit was simulated to
get the netlist and output waveform using DC analysis and transient analysis as shown below.
Netlist
*
* .CONNECT statements
*
.CONNECT GROUND 0
.CONNECT VSS 0
* ELDO netlist generated with ICnet by 'aic4' on Wed Mar 23 2011 at 14:40:08
*
* Globals.
*
.global VSS VDD
*
* Component pathname : /home/aic4/assignment4/question2
*
.subckt QUESTION2 VBIASP VBIASN
MA1 N$16 N$17 VSS VSS nhp L=0.36u W=9u M=1
MA2 VBIASP VBIASN VSS VSS nhp L=0.36u W=9u M=1
MA3 N$16 N$16 VDD VDD php L=0.36u W=18u M=1
MA4 VBIASP N$16 VDD VDD php L=0.36u W=18u M=1
MSU3 VBIASP N$12 VBIASN VSS nhp L=0.18u W=1.8u M=1
MSU1 N$12 VBIASN VSS VSS nhp L=0.36u W=9u M=1
R1 N$8 VSS 6.2K
MSU2 N$12 N$12 VDD VDD php L=3.6u W=1.8u M=1
M3 VBIASN VBIASP VDD VDD php L=0.36u W=18u M=1
M4 N$17 VBIASP VDD VDD php L=0.36u W=18u M=1
M1 VBIASN VBIASN VSS VSS nhp L=0.36u W=9u M=1
M2 N$17 N$17 N$8 VSS nhp L=0.36u W=36u M=1
.ends QUESTION2
*
* MAIN CELL: Component pathname : /home/aic4/assignment4/question2/question2_tb
*
V2 N$4 VSS PULSE ( 0V 1.8V 1uS 1nS 1nS 20nS 100nS )
X_QUESTION21 N$203 N$202 QUESTION2
V1 VDD N$4 DC 1.8V
*
.end
Waveform output

Figure 2.3: Graph Iref vs Vdd

Figure 2.4: Graph Iref vs time

The graph in Figure 2.3 shows how the reference current vary with VDD after the differential
amplifier circuit is added where it significantly reduce the sensitivity so, the circuit can get desired current
output at constant value of 8µ.

The graph in Figure 2.4 shows the current reference varies with times before the MCP and MCN
are added to the circuit which show the reference is not stable and the current oscillate.
 3) Beta-Multiplier reference circuit with differential amplifier
and compensation capacitor.

Schematic

Figure 3.1: BMR circuit with differential amplifier and compensation capacitor.

The circuit above shows a BMR circuit with differential amplifier and compensation capacitor
(MCP and MCN) added to make the reference stable.
Test-bench schematic

Figure 3.2: Test-bench of BMR circuit with differential amplifier and compensation capacitor.

The circuit in Figure 3.1 generated to symbol then a test-bench schematic was create as shown at
Figure 3.2 where the voltage supply and pulse signal are added. The test-bench circuit was simulated to
get the netlist and output waveform using DC analysis and transient analysis as shown below.
Netlist
*
* .CONNECT statements
*
.CONNECT GROUND 0
.CONNECT VSS 0
* ELDO netlist generated with ICnet by 'aic4' on Wed Mar 23 2011 at 15:09:03
*
* Globals.
*
.global VSS VDD
*
* Component pathname : /home/aic4/assignment4/question3
*
.subckt QUESTION3 VBIASP VBIASN
MCP VDD VBIASP VDD VDD php L=18u W=18u M=1
MCN VSS VBIASN VSS VSS nhp L=18u W=18u M=1
MA1 N$11 N$1 VSS VSS nhp L=0.36u W=9u M=1
MA2 VBIASP VBIASN VSS VSS nhp L=0.36u W=9u M=1
MA3 N$11 N$11 VDD VDD php L=0.36u W=18u M=1
MA4 VBIASP N$11 VDD VDD php L=0.36u W=18u M=1
MSU3 VBIASP N$5 VBIASN VSS nhp L=0.18u W=1.8u M=1
R1 N$2 VSS 6.2K
MSU2 N$5 N$5 VDD VDD php L=3.6u W=1.8u M=1
M3 VBIASN VBIASP VDD VDD php L=0.36u W=18u M=1
M4 N$1 VBIASP VDD VDD php L=0.36u W=18u M=1
MSU1 N$5 VBIASN VSS VSS nhp L=0.36u W=9u M=1
M1 VBIASN VBIASN VSS VSS nhp L=0.36u W=9u M=1
M2 N$1 N$1 N$2 VSS nhp L=0.36u W=36u M=1
.ends QUESTION3
*
* MAIN CELL: Component pathname : /home/aic4/assignment4/question3/question3_tb
*
V2 N$816 VSS PULSE ( 0V 1.8V 1uS 1nS 1nS 20nS 50nS )
X_QUESTION31 N$613 N$612 QUESTION3
V1 VDD N$816 DC 1.8V
*
.end
Waveform output

Figure 3.3: Graph Iref vs Vdd

Figure 3.4: Graph Iref vs time

The graph in Figure 3.3 shows no effect in reference current output value even after a
compensation capacitors are added, as the circuit still can get desired current output at constant value of
8µ.

The graph in Figure 3.4 shows the current reference varies with times after the MCP and MCN
are added to the circuit which shows the change in the graph where the reference current is stable and the
oscillations are not present.