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Application Note 4108

A Fairchild Power Switch based on
Switched Mode Power Supply for CRT Monitor Use

1. Introduction
FS6S series is a Fairchild Power Switch (FPS) that is describes the features and design considerations of the FS6S
specially designed for off-line SMPS of CRT monitor with series for the monitor power supply, which improves upon
minimal external components. This device is a current mode the existing KA5S-series. The FS6S series has three package
PWM controller combined with a high voltage power types: TO-3P-5L, TO-220-5L and TO-220F-5L as shown in
SenseFET in a single package. The PWM controller features figure 1-1.
integrated oscillator to be synchronized with the external
The FS6S series has a synchronization pin, which accepts an
sync signal, under voltage lockout, optimized gate driver and
external sync signal. In order to remove the screen noise
temperature compensated precise current sources for the
generated by the switch action, the FS6S series synchronizes
loop compensation. This device also includes various fault
its switching with the external sync signal. When in power
protection circuits such as over voltage protection, over load
saving mode, the FS6S series pulls down the output voltages
protection, abnormal over current protection and over
to a predetermined level and enters burst mode with a
temperature protection.
switching frequency of 50kHz.
The FS6S series has a more rugged SenseFET than the
previous Fairchild Power Switch series. The FS6S series
features include burst mode operation for low power
consumption in standby mode. This application note

TO-220-5L TO-220F-5L TO-3P-5L

Figure 1-1. Package Line-Up

Rev. 1.0.3
©2002 Fairchild Semiconductor Corporation
AN4108 APPLICATION NOTE

Table 1: Product Line-up (Monitor Application) 2. Internal Block and Important

Product Rating Package
Features
FS6S0765RCB 7A/650V TO-220-5L 2.1 Internal Block and Features
• Current mode control
FS6S0965RT 9A/650V TO-220F-5L
• Burst mode operation for low power consumption in
FS6S0965RCB 9A/650V TO-220-5L standby
• Higher rugged SenseFET (QFET)
FS6S1265RE 12A/650V TO-3P-5L • Optimized gate Driver for low EMI
• Low standby power consumption (low startup current and
FS6S1565RB 15A/650V TO-3P-5L
low operating current)
• Various internal protection circuits (Auto-restart)
– Over Voltage Protection (OVP)
– Over Load Protection (OLP)
– Thermal Shutdown Protection (TSD)
– Over Current Latch (OCL)
• Minimization of production defects by reinforcing VCC
surge immunity and internal diode.
• Reduction of secondary side diode voltage stress during
startup and transient by introducing slope to the sync
threshold voltage.

Vcc Drain

3 1
Vref Vpp=5.8/7.2V

OSC Internal
Vref
SoftStart Bias
& Sync 5 Vref
UVLO

Vfb Burst mode

Vth=1V controller
S
Q Ron
R
Vcc
Vth=11V/12V
Roff

PWM

Feedback 4 2.5R
Ifb R
Vref Vcc Vfb Offset

Rsenese
Idelay
OCL Filter
OLP (130nsec)
Vth=1V 2 GND
Vth=7.5V
S Q TSD
Vcc (Tj=160 ℃)
UVLO Reset R
OVP (Vcc=9V)
Vth=30V

Figure 2-1. Internal Block Diagram

©2002 Fairchild Semiconductor Corporation

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APPLICATION NOTE AN4108

2.2 Starting resistor design and UVLO

By assuming an universal input voltage (85-265Vac), startup Rstart

resistor is designed as follows: DC Link

+

The minimum average input voltage (Vamin) applied to the Cvcc

startup resistor, is obtained as 0

3 0

min 1 π
Va = ------- ∫ ( 2 ⋅ 85 ⋅ sint – 15 ) dt
2π o Internal Bias
Power On
2 × 85 2 – 15π Reset 3 3
2Vp – 15π 1
+
1 5V
= ----------------------------- = ------------------------------------------ = 30.8 V - 2 2 Vref
2π 2π Latch
Comparator 15V/9V UVLO
Good Logic
9V
Vz
The resistor for startup is calculated by assuming a startup
0
current of 200uA as follows 0 0
Fairchild Power Switch(SPS)
Rstart = 30.8 ÷ 200µA = 154K
Figure 2-3. UVLO Block
The maximum RMS voltage applied to the startup resistor is
approximately obtained as 2.3 Fairchild Power Switch Protection Circuits.
max 1 π 2 265 FPS has several self-protection circuits, which can be used
V rms ≅ ------- ∫ ( 2 ⋅ 265 ⋅ sint – 15 ) dt ≅ ----------
2π o 2 without adding external components, thus providing system
reliability without increasing cost. Under auto restart mode,
= 187 V
protection circuits become disabled when VCC falls below
The maximum loss in the startup resistor is obtained as 9V (stop voltage), after which the FPS tries to restart. Under
latch mode, protection circuits become deactivated only
max 2 when VCC falls to 6.5V (reset voltage), then the Fairchild
( V rms ) Power Switch tries to restart. When VCC drops to 9V due to
P ( loss ) = ------------------------------------ = 0.23W
Rstart latch protection, the operating current of the IC drops from
10mA to 100µA. Therefore the VCC capacitor starts to
charge towards 15V through the starting resistor. For VCC to
The FPS starts switching operation when the VCC voltage fall to 6.5V (reset voltage), the input voltage must be
reaches 15V (the start voltage). Once it starts switching, the removed.
current consumed by the control IC increases to 10mA
(operating current). The starting resistor cannot provide the 2.3.1 Over Load Protection (OLP)
operating current and consequently, the transformer auxiliary
Overload as described here is different from a load short
winding supplies most of this current once FPS starts up.
circuit. It is a condition where a load becomes greater than
The start time will be delayed if the VCC capacitor is too
the preset level, though it is operating normally.
large, so a moderately sized capacitor should be used.
Essentially, the overload protection circuit forces the
Typically, 22 ~ 47µF capacitor is used. This operation is
Fairchild Power Switch to stop its operation if the load draws
described in Figure 2-2. VCC should be maintained above 9V
a higher current than the predetermined maximum value. A
after starting. However, it should be set so that OVP (OVP
problem associated with this type of protection circuit is that
threshold is typically 30V) is not triggered during the normal
it can trigger erroneously on load transients. As a security
operation.
measure, the Fairchild Power Switch triggers the protection
Icc
circuit after a specific time delay. This avoids false
triggering on short load transients.
The above operations are executed as follows. Since the
Fairchild Power Switch uses current mode control,
maximum switch current is limited internally. For a fixed
input voltage, this limits the power. Therefore, if the power
10mA
at the output exceeds this maximum, VO shown in figure 2-4
becomes less than the set voltage, and KA431(LM431) can
draw only the allowed minimum current. As a result, the
photo-transistor’s current becomes zero. If all the current of
100uA
the 0.9mA Fairchild Power Switch current source flows
Vcc
through the internal resistor (2.5R+R= 3.3K), Vfb becomes
Vstop=9V Vstart=15V OVP approximately 3V. At this time the 2µA current source starts
to charge Cfb. Because the photo transistor’s current is zero,
Vfb continues to increase. The Fairchild Power Switch shuts
Figure 2-2. Start-up Waveform down when Vfb reaches 7.5V. The shutdown delay time can
be easily determined as the time required to increase the Cfb

©2002 Fairchild Semiconductor Corporation

3
AN4108 APPLICATION NOTE

by 4.5V (from 3V to 7.5V) using 2µA. When Cfb is 47nF, To obtain the same results, a zener diode (approx. 3.9V) can
delay time is approximately 100ms. The FPS will not shut be series-connected to a capacitor (47nF) which can then be
down within this time. Increasing Cfb to get a longer delay parallel connected to Cfb as shown in Figure 2.4.
time can become a problem, because Cfb is an important
parameter in determining the SMPS dynamic response time.
One method to delay the shutdown time is to add a resistor
between the feedback pin and GND and to subtract the
amount of the delay current. When the 4.7MΩ resistor was
used experimentally with a Cfb of 47nF, shutdown time was
almost doubled to 180~200ms. When Vfb voltage is 7.5V,
the current flowing to the 4.7MΩ resistor is approximately
1.6µA.

Fairchild Power Switch(SPS)

2uA 0.9mA
Vo
Vfb D1 D2

4
Idelay Cfb

1 4 Cd 0 Vfb*

2 3

Vz=3.9V
3
1

+
0 1
0 2 - 0
8 OLP
KA431
Latch
7.5V
6

Figure 2-4. Fairchild Power Switch Long Delayed Shutdown

2.3.2 Over Voltage Protection 2.3.3 Over Current Protection (OCP).

The Fairchild Power Switch has self protection features that The existing concept of Ipeak control does not go beyond
function even when abnormal states occur such as an open or limiting the amount of current during normal operation.
short circuits in the feedback loop. The OCP block prevents damage to Fairchild Power Switch
When the feedback terminal shorts as viewed from the from abnormal states, such as a diode or a load short. A
primary side, the feedback terminal voltage becomes zero diode or a load short causes a large current to flow through
and prevents switching from starting. If it opens, the the SenseFET for a short time. This can be tens of amperes.
protection circuit acts as an over voltage protection circuit. The leading edge blanking circuit sets the minimum turn on
When there is an abnormal state or a possibility of opening time at 600nS. Tens of amperes for 600nS could destroy the
due to improper soldering etc. in the secondary side Fairchild Power Switch and so the OCL block senses this
feedback circuit, the primary side continues to switch using instantaneous current and latches like the existing protection
the maximum set current until the protection circuit starts to circuits.
operate. In such instances, it is common for the secondary
side voltage to become greater than the rated voltage, which
can lead to a fuse blowing or, more seriously, a fire if a
protection circuit is not in place. Even if this was not the
case, ICs immediately connected to the secondary output
without a regulator can be destroyed.
Therefore, Fairchild Power Switch employs the over voltage
protection circuit to protect against feedback anomalies.
The Fairchild Power Switch VCC is proportional to the
output voltage. When the Fairchild Power Switch VCC
exceeds 30V, the over voltage protection feature is triggered.
Therefore, VCC must be maintained at less than 30V during
normal operation.

©2002 Fairchild Semiconductor Corporation

4
APPLICATION NOTE AN4108

frequency synchronization method which uses the horizontal

deflection frequency delivered to the number 5 pin of the
Figure of OCL Operation
Fairchild Power Switch. Figure 3-1 shows the circuit around
the pins. At start up, a ramp is generated on pin 5 by
charging Cs with Ifb and the current through the 50kΩ
resistor. This ramp increases the maximum duty cycle
slowly, which results in soft start. After the soft start, Vcs
remains at 5V and thus the voltage at pin 5 becomes 5V DC
plus the external sync input. The sync comparator generates
300ns
the comparator output waveform (Vcomp) by comparing the
voltage of pin 5 with a sawtooth waveform of 5.8~7.2V as
shown in Figure 3-1. The internal timing capacitor, Ct,
charges and discharges between 5.8 and 7.2V thresholds.
Minimum Turn-on Time
The oscillator output waveform VCK becomes low while Ct
charges and high while it discharges. This output signal is
sent to the set terminal of the S/R latch.
1 Latch
S
3
Q`
2 Vrs 0V 2V
R

Vpin5 5V

3
0V
+
1
- 2 Vcomp
0V
Rsense Vthh
OCL Level
Vct
0V Vthl
0 0 Vsync.th
Vck
Figure 2-5. Over Current Latch (OCL) 0V

3. External Frequency Figure 3-1 Synchronous Operation

Synchronization Method
As mentioned, the Fairchild Power Switch operates within a
wide frequency range synchronized to the horizontal
deflection frequency of a monitor. This section describes the

Ifb
SPS

PWM Comp
5V 2 -
1
3 +
50K

5 0

+ sync comp
Cs Vcs
3 Vcomp
+
1
2
OSC
-
External 7.2V
Sync Rs Vrs
Input 5.8V

Figure 3-2. Synchronization Circuit

©2002 Fairchild Semiconductor Corporation

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AN4108 APPLICATION NOTE

V th h = 7 .2 V

V sync

V th l= 5 .8 V

P in 5

Figure 3-3 Negative Slope Synchronized to Sync Pulses

The inverse slope of the oscillator output becomes the sync
comparator reference, Vsync, which oscillates between 7.2V
and 5.8V with the basic frequency of 25kHz.
Figure 3-2 shows that when the sync signal is applied or
Vsync reaches the Ct voltage of 7.2V, Vct starts to decrease
toward the low threshold voltage Vth1. The oscillator output,
Vck, outputs a high signal while Vct decreases. As soon as
Vct comes down to Vthl, Vct starts to increase, Vck drops
down, and the SenseFET gate turn on signal is generated.
The high duration of Vck is restricted to 5% of one switching
period to keep switching noise off screen. If a constant sync
comparator reference is used, the SenseFET can be turned on
just after being turned off by the first sync signal. In this case
the secondary rectifying diode is turned off while it is still
conducting.
This causes a high reverse voltage spike between the anode
and cathode of the diode due to the long reverse recovery
time. In order to solve this problem, FS6S series uses the
negative slope as the sync comparator reference. Generally
the levels of sync pulses increase gradually to a certain
value. If these gradual increasing sync pulses are compared
with the negative slope, the first sync pulse that touches the
negative slope will be placed in the back area of the basic
period of the oscillator as shown in Figure 3-3.
This makes the MOSFET turned off at low or no current
levels of the secondary windings of the switching
transformer, which can reduce the reverse voltage spike of
the rectifying diode significantly. The level of the applied
sync signal should be large enough to cross the sync
threshold. The level should not exceed 9V for safe frequency
synchronization since it is clamped by the 9V voltage source
at the sync comparator terminal in the Fairchild Power
Switch. Furthermore, the sync signal is added to DC 5V
across the soft start capacitor on pin 5.
Therefore, the voltage level should be between 8V and 9V
(pure sync signal voltage level is 3 ~ 4V) for safe frequency
synchronization.
3.1 Sync Transformer Method
This is the most commonly used method for frequency
synchronization in monitor designs and is shown in Figure
3.4. The horizontal sync signal is applied to pin 5 of the
Fairchild Power Switch through a transformer.
Delay time is short and thus the switching noise is pushed to
the left of the monitor screen, and does not appear in the
visible area. One turn from the FBT can also be used instead
of the sync.
3.2 Photo-coupler Method
Unlike the sync transformer method, this method shown in
Figure 3-5 produces a slight delay time but almost no noise
on the screen. The zener diode can compensate the Current
Transfer Ratio (CTR) of photo-coupler. Though this method
is not frequently used, it has a few advantages for auto-
assembly during manufacture.
3.3 Quasi Resonance Method
The resolution on the screen is slightly poor when using the
quasi-resonance method shown in Figure 3-6. Switching
noise is present on the screen but is not visible since it is not
correlated with the picture scan. The Fairchild Power Switch
does not depend on the external sync signal but uses the self
oscillation frequency which varies with load. However,
additional devices, such as the sync transformer or photo-
coupler etc., are not required because the Fairchild Power
Switch is not synchronized to the sync frequency.
The method is not only highly cost competitive but also
advantageous in terms of power loss because it uses zero
voltage switching.

©2002 Fairchild Semiconductor Corporation

6
APPLICATION NOTE AN4108

4. Display Power Management

R102 D102
Signalling (DPMS) Design Method
R103
With high interest in power management recently, much
IC101
effort has been concentrated in implementing the DPMS
5

4
S/S
Drain
1 kbreak mode. The FS6S series uses burst mode for DPMS in order
TX2 Vfb
2

C110
+ 3
Vcc
GND
to achieve cost effectiveness and minimize the power
C201 kbreak
FS6S0965R
consumption.
Sync
C108
Signal(from
H_DRV) C109
+
4.1 Burst Mode Operation
R104
D104

D103 The FS6S-series has a particularly useful function for the

DPMS mode: burst mode operation. Normally, customers
IC301
0 use an auxiliary power system for DPMS in large monitors.
4 1
This method can lower power consumption but increases
3 2
costs. The FS6S-series can drop the output voltage with only
minimal external components by using burst mode. This
0
reduces power loss in DPMS mode. In the DPMS mode, Vfb
Figure 3-4. Sync Transformer Synchronization Method is pulled low by the external micro-controller.
4.2 Implementation of the Burst Mode
R102 D102
The required circuit for implementing the burst mode is
R109
R103
shown in Figure 4-1. Q1, D1, Rx, R5 and R6 are added to the
Sync
Signal(from
H_DRV)
R201 secondary feedback network. During normal operation, Q1
IC101
5
S/S
Drain
1 kbreak
is on, which isolates Rx from the feedback network. Vo2 is
4
Vfb
1 4
+ 3
Vcc
GND
2
sensed and the amplified error is transferred to the primary
C110
2 3 FS6S0965R
side through the photo coupler.
U5
By turning off Q1, Rx is connected to the feedback network.
C108

C109
+
The error amplifier increases the current through the photo
R104

D105 coupler, and thus Vfb of the FS6S-series drops to zero.

Therefore no additional opto coupler is required to switch
0
into burst mode. Rx can be calculated by the following
IC301
4 1 equation when a KA431(LM431) is used as an error amp.
3 2
R7 × R8 ( Vol – 2.5 – V D1 )
Rx < ----------------------------------------------------------------------
0 2.5 ( R7 + R8 ) – R8 ⋅ Vo2

Figure 3-5. Photo-coupler Method where Vo1 and Vo2 are the reduced voltages in burst mode.

R102 D102

R103

IC101
5
S/S
Drain
1 Resonance CAP
4
Vfb C112
2
GND
3 1n
Vcc
FS6S0965R
R110 D103

C108
+
C109 R104 C111

IC301 0
4 1

3 2

Figure 3-6. Quasi-Resonance Method

©2002 Fairchild Semiconductor Corporation

7
AN4108 APPLICATION NOTE

Vo2

Vo1 R7

Ic Ib

R1 Ia
R2 R3 Rx R5

4 1
R8
C1
3 2
Micom signal

1
D1 Q1

KA431 R6

Figure 4-1. Rx Setting Circuit for Burst Mode Operation

4.3. Experimental Results of Burst Mode Operation

4.3.1. VCC/Vds and Vregin/Vregout waveforms in burst mode.

Vcc
5V/div

Vds
200V/div

Figure 4-2. VCC/Vds in Burst Mode Operation

©2002 Fairchild Semiconductor Corporation

8
APPLICATION NOTE AN4108

Vregin
2V/div Vregout
1V/div

Figure 4-3. Vregin/Vregout Operation in Burst Mode.

Experimental results are shown in, Figure 4-2 and Figure 4- When the Fairchild Power Switch operates Burst Mode: Pin
3. With minimum load and normal operation: Vac = 240V, = 2.72W, VCC = 11~12V, Vo = 132V and Vregin=7.07V
Pin = 4.82W, VCC = 20V, Vo = 190V and Vregin = 12.24V.

4.5 Circuits for DPMS mode

T1 D201
1 16

L201
+ 2

BD101 C107 +
R101 C201 +
C202
1 3 + C106 2 15
IC202
D202
3 14 1 2
-

D101 VIin Vout

4

L202 4 3
+ + R206 Vc GND
C203 C204
RT101 0
4 13 Q201
C105
R102 D102 R207 D204
6
1k
R103
D203 Suspend
12 1 2
Signal(from
7 L203 Q202 micom)
Line Filter: LF101 IC101 + +
3

5 C205 C206
S/S
1
Drain R208
4 11
Vfb
2
+ GND
3 Q203
C110 Vcc R209
FS6S0965R Q204
C103 C104

Off
C108
External Sync + -Signal(from
C102 R104 C109 micom)
TRNSFMR DEL16-640A11_1

C301 C302
C101

0
F101
FUSE

R203
R204

IC301
4 1
C207 R205
3 2

0
1

R201

IC201 8
6

R202

Figure 4-4. Micro Controller Method for Controlling DPMS Mode

©2002 Fairchild Semiconductor Corporation

9
AN4108 APPLICATION NOTE

T1 D201
1 16

L201
+ 2

BD101 C107 +
R101 C201 +
C202
1 3 + C106 2 15
IC202
D202
3 14 1 2
-

D101 VIin Vout

4

L202 4 3
+ + R206 Vc GND
C203 C204
RT101 0 R102
4 13 Q201
C105
R103 D102 R207 D204
6
1k
D203 Suspend
12 1 2
Signal(from
7 L203 Q202 micom)
Line Filter: LF101 IC101 + +

3
5 C205 C206
S/S
1
Drain R208
4 11
Vfb
2
+ GND
3 Q203
C110 Vcc R209
FS6S0965R Q204
C103 C104

Off
C108
External Sync + -Signal(from
C102 R104 C109 micom)
TRNSFMR DEL16-640A11_1

C301 C302
C101

0
F101
FUSE
u-com
R203
R204 R210
5V-Reg
IC301
4 1
0
C207 R205 D7
3 2

0
1

R201

IC201 8
Q205
6

R202

LOW:Off -mode

Figure 4-5. Using Burst Mode Operation for DPMS.

©2002 Fairchild Semiconductor Corporation

10
APPLICATION NOTE AN4108

5. Monitor Application
5.1 Flyback converter demo circuit

T1 D201
1 16

L201 R201 180V

+ 2

BD101 C107 + + R209 300k 300mA

47nF/630V R101 19T 46T C201 C202 33K
68K/2W 22uF/400V 22uF/400V
1 3 + C106 2 15
220uF/400V R202
D202 4.2k
3 14
4 -

L202
D101 + +
18T 37T C203 C204 80V
RT101 0 47uF/160V 47uF/160V 100mA
4 13
C105
R102 D102 D203
6 12
47nF
15
R103 L203
150K/1W + C205 + 15V
1000uF/35V C206
11T 1000uF/35V 800mA
7
7T
Line Filter: LF101 IC101
5 D204
S/S
1 11
Drain
4
Vfb
2 L204
GND C207 C208
C108
+ 3
Vcc + + -15V
1000uF/35V 1000uF/35V
1uF/50V FS6S0965RT 7T 600mA
C103 C104

D205
4.7nF 4.7nF 10

R104 C110 L205

C102 47nF External Sync 470 C109 + 3T + + 6.5V
47nF 47uF/50V C209 C210
1000uF/16V 1000uF/16V 600mA
9

C9 C10
C101 TNR
4.7nF
4.7nF
0
F101
FUSE

R203 IC202
1k R206 R207 KA7805
IC301 R204 R205 2.7k 4.7K 1 2
HC11A817A 1k 33k VIN VOUT

GND
4 1
C211 +
47n C212 R210 5V
3 2 100u/16V 39

3
Sw201 130mA
Switch
1

0 D206 Q201

IC201 8
KA431(LM431) R208
6

4.7K

Figure 5.1 Fairchild Power Switch Flyback Converter DEMO BOARD for a Monitor Application

©2002 Fairchild Semiconductor Corporation

11
AN4108 APPLICATION NOTE

5.2 Part List for Fairchild Power Switch Flyback

Converter DEMO BOARD for a Monitor Application
Part Name Value Part Name Value
LF101 BSF-1925 R206 33K, 1/4W
IC101 FS6S0965RCB R207 2.7K, 1/4W
BD101 KBL407 R208 4.7K, 1/4W
RT101 NTC R209 4.7K, 1/4W
R101 68K,3W R210 39, 1/4W
R102 15, 1/4W C201 22µF/400V
R103 150K, 1W C202 22µF/400V
R104 470, 1/4W C203 47µF/160V
C101 TNR C204 47µF/160V
C102 BOX CAP, 47nF C205 1000µF/35V
C103, C104 EMI FILTER CAP, 47nF C206 1000µF/35V
C105 BOX CAP, 47nF C207 1000µF/50V
C106 220µF/400V C208 1000µF/50V
C107 47nF/630V C209 1000µF/16V
C108 47µF/50V C210 1000µF/16V
C109 47nF/50V C211 47nF / 50V
C110 1µF/50V C212 100µF/16V
D101 UF4007 D201 RG4C
D102 TVR10G D202 SUF15J
- - D203 UG4D
IC201 KA431(LM431) D204 UF1G
IC202 KA7805/LM7805/MC7805 D205 UG4D
R201 120K, 1/4W D206 TVR10G
R202 1.8K, 1/4W - -
R203 33K, 1/4W IC301 QT817A
R204 1K, 1/4W C301 4.7nF/2KV
R205 1K, 1/4W C302 4.7nF/2KV
Parts in Boldface are available from Fairchild Semiconductor.

©2002 Fairchild Semiconductor Corporation

12
APPLICATION NOTE AN4108

5.3 Transformer Specification

1 16 (2)33T
(8)17T 170V φ = 0.3mm
φ = 0.3mm (2-ply) Lm = 330µH
(3-ply) 15
2
14 (6)27T
Vin 75V
φ = 0.3mm
GND2 13 (2-ply)
3 Core: EER4044
(1)18T Bobbin: EER4044
φ = 0.3mm 1: (4) → (3) 18T φ = 0.3mm (3 ply-wire)
(3-ply) 12 (5)6T 2: (16) → (15) 33T φ = 0.3mm (2 ply-wire)
4 11V φ = 0.3mm 3: (10) → (9) 3T φ = 0.45mm
4: (11) → (9) 9T φ = 0.2mm
11 5: (12) → (9) 6T φ = 0.3mm (3 ply-wire)
(4)9T
15V φ = 0.2mm 6: (14) → (13) 27T φ = 0.3mm (2 ply-wire)
10 7: (6) → (7) 9T φ = 0.3mm
8: (2) → (1) 17T φ = 0.3mm (3 ply-wire)
6 6.3V (3)3T
(7)9T φ = 0.45mm
φ = 0.3mm Bias Winding GND1 9
7

Figure 5-2 FS6S0965RCB Transformer Specification for a 95W Monitor Application.

1 18
(8) 15T 190V
φ = 0.25mm (2) 60T
(9-ply) 17 φ = 0.45mm Lm = 230µH
2
16
Vin 85V (6) 27T
φ = 0.45mm
3 GND2 15 Core: EER4445
(1) 16T Bobbin: EER4445
φ = 0.25mm 1: (4) → (3) 16T φ = 0.25mm (9 ply-wire)
(9-ply) 14 2: (18) → (15) 60T φ = 0.45mm
15V (5) 5T
3: (12) → (11) 2T φ = 0.45mm
4 φ = 0.45mm
4: (13) → (11) 8T φ = 0.3mm (3 ply-wire)
13 (4) 8T 5: (14) → (11) 5T φ = 0.45mm
25V 6: (16) → (15) 27T φ = 0.45mm
φ = 0.3mm
(3-ply wire) 7: (6) → (7) 8T φ = 0.3mm
12 8: (2) → (1) 15T φ = 0.3mm (9 ply-wire)
6 6.5V
(3) 2T
(7) 8T Bias Winding φ = 0.45mm
φ = 0.3mm GND1 11

Figure 5-3. FS6S0965RCB Transformer Specification for a 120W Monitor Application.

©2002 Fairchild Semiconductor Corporation

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AN4108 APPLICATION NOTE

- FS6SXX65R Comparison Table of Electrical Characteristics -

FS6S-series KA5S-series KA2S-series

Content Unit
Min Typ Max Min Typ Max Min Typ Max
Start-up Current - 100 170 - 100 170 100 300 550 uA
Operating Current - 10 15 - 7 12 6 12 18 mA
Initial Frequency 22 25 28 18 20 22 18 20 22 kHz
Burst Mode Frequency 40 50 60 - - - - - - kHz
Over Current Protection 0.9 1.0 1.1 - 1.1 - - - - V
Burst Mode Ipeak 0.6 0.85 1.1 - - - - - - A
Burst Mode Range 11.0 - 12.0 - - - - - - V
Over Voltage Protection 27 30 33 23 25 28 23 25 28 V
Shutdown Delay Current 1.6 2.4 2.4 3.0 4.0 5.0 1.4 1.8 2.2 uA
Table 3. FS6S-Series Comparison with Previous KA5S and KA2S - Series

©2002 Fairchild Semiconductor Corporation

14
APPLICATION NOTE AN4108

©2002 Fairchild Semiconductor Corporation

15
AN4108 APPLICATION NOTE

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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 2002 Fairchild Semiconductor Corporation