Harmonic Mitigation in Power Quality Analysis

A End Term Project Report

Submitted by

Suraj Kumar (B17EE015)

Akash Kumar Singh (B17EE029)
Shrey Kumar (B17EE030)

Under the Supervision of

Dr. Ksh Milan Singh

In partial fulfillment for the award of the degree of Bachelor of

Technology

in

Electrical and Electronics Engineering

Department of Electrical Engineering

National Institute of Technology
Meghalaya

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Conten
t
List of Figures.........................................................................................................................................4
1. Introduction.......................................................................................................................................6
1.1 Literature Review.........................................................................................................................6
1.2 Problem Finding...........................................................................................................................7
1.3 Objectives....................................................................................................................................7
2. Methodology....................................................................................................................................8
2.1 Analog Phase-Locked Loop..........................................................................................................8
2.1.1 Working Principle of PLL.......................................................................................................8
2.1.2 Phase-Locked Loop Detector................................................................................................9
2.1.3 Exclusive OR Phase Detector................................................................................................9
2.1.4 Edge Trigger Phase Detector...............................................................................................11
2.1.5 Monolithic Phase Detector.................................................................................................11
2.1.6 Applications of Analog Phase-Locked Loop.........................................................................11
2.1.7 Disadvantage of Analog PLL................................................................................................11
2.2 Digital Phase Locked Loop (DPLL)..............................................................................................11
2.2.1 Working Principle of DPLL...................................................................................................12
2.2.2 Proposed Architecture........................................................................................................13
2.2.3 Digital Phase detector.........................................................................................................13
2.2.4 Digital Loop Filter (DLF).......................................................................................................14
2.2.5 Digital Controlled Oscillator (DCO)......................................................................................14
2.2.6 Programmable Divider........................................................................................................15
2.2.7 Modulated hoping DFT (mHDFT)........................................................................................15
2.2.8 Modulated hoping DFT (mHDFT) Algorithm.......................................................................15
2.2.9 Technique for mHDFT.........................................................................................................17
2.3 White Noise...............................................................................................................................19
2.3.1 Application of Noise............................................................................................................20
Disadvantage of white noise............................................................................................................22
2.3.2 Cramer Rao bound..............................................................................................................22
2.4 SDFT and Sliding Goertzel..........................................................................................................23
2.5 Complexity of different algorithms............................................................................................24
3. Result analysis.................................................................................................................................26

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 3.1 With Noise.................................................................................................................................27
3.1.1 CRLB analysis......................................................................................................................29
3.2 Dc shift applied to input signal...................................................................................................30
3.3 Testing of signal with higher amplitude.....................................................................................31
3.4 Stability of low pass filter...........................................................................................................32
Conclusion...........................................................................................................................................37
References...........................................................................................................................................38

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List of Figures

Fig. 1: Basic diagram of phase locked loop (PLL)

Fig. 2: Table for EXOR detector

Fig. 3: Exclusive OR Phase Detector

Fig. 4: Edge Trigger Phase Detector

Fig. 5: Block diagram of Proposed ADPLL

Fig. 6: Block diagram of Linear Phase Detector

Fig. 7: Block diagram of digital control oscillator

Fig. 8: Block diagram of programmable divider

Fig. 9: Hoping-DFT structure for window length M and hopping length L

Fig. 10: mHDFT structure with phase correction

Fig. 11: Proposed Phased-Locked Loop model for harmonics estimation

Fig. 12: White Noise

Fig. 13: Input signal

Fig 14: Extracted harmonic components

Fig. 15: (a) White noise added signal with SNR 0dB

Fig. 15: (b) Extracted harmonic components with noise SNR 0dB

Fig. 16: (a) White noise added signal with SNR 10dB

Fig. 16: (b) Extracted harmonic components with noise SNR 10dB

Fig. 17 MSAE and CRLB for amplitude measurement (MSAE vs. SNR (dB))

Fig. 18: (a) Input signal with Dc shift of 5v

Fig. 18: (b) Extracted harmonic components for Dc shift 5v

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Fig. 19: (a) Input signal with fundamental harmonic amplitude 100v

Fig. 19: (b) Extracted harmonics component with new amplitude

Fig. 20(a): pole zero plot of low pass filter

Fig 20(b): frequency of low pass filter

Fig 21(a): pole zero plot of SDFT filter with n=20 and k=1

Fig 21(b): frequency response of SDFT filter

Fig 21(c): pole zero plot of Sliding Goertzel with n=20, k=1

Fig 21(d): frequency response of Sliding Goertzel

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1. Introduction

1.1 Literature Review

Earlier large scale generation of electricity was carried out by fossils fuels: coal, gas or oil
nuclear power plants etc. which was centralised [1-2]. This conventional mode of power
generating will lead to trouble in near future as there will be a shortage of fossils fuel and also
there is loss of power due to long transmission line. Hence we cannot simply rely on these
conventional modes of electricity generation.

Power quality refers to ability of power system to generate pure noise free sinusoidal power
supply that has stable voltage and frequency associated with it [1]. There are many power
quality concerns like voltage sag, voltage swells, harmonics etc. Poor power quality leads to
wastage of power and money.
Power quality issues (mainly harmonics) in the conventional mode of electricity generation is
not much severe as there was number of non-linear loads which contributes towards
harmonics is negligible in the utility, But due to shortage in resource and power losses we are
shifting toward generation through renewable energy resources like wind, solar etc. [3] which
is based on distributed generating units in which power flow is not unidirectional unlike
conventional one. These sources require power electronic interface to get connected with the
grid and to meet the standard/regulations imposed by the utility.

Hence from above we find that, the modern power system is characterized by the presence of
large number of power electronics converters based distributed generators (DG) along-with
traditional power plants [2]. Almost all these power electronics converters are committed to
provide a controlled and high quality power exchange to the utility or local linear/non-linear
loads connected at the point of common coupling (PCC). Thus there are many issues in
microgrid.

There are many power quality concerns in smart grid [2]. One of the major power quality
concern is harmonic which are generated by non-linear loads. There are various traditional
techniques used to mitigate harmonics [4]. Some of these techniques are line reactor,
isolation transformer, active filters etc.

Out of the various active power filter configurations (series, shunt and hybrid), shunt active
power filter (SAPF) is quite popular to remove harmonics locally at the load side making the
utility free of harmonics [5]. Shunt active filter is used for local compensation but can be
extended to complex multinode system by optimal control techniques. Also there are various

6
controller techniques in SAPF which reduces THD (total harmonic distortion) to certain level
[6].

While studying several issues in modern power system [1] it is found that static DG’s are
used mostly however there are many power quality problems many of which are solved by
power electronic converter like active power filter or power electronics converters like
FACTS devices. Control designs are necessary [6] for proper operation of these devices.

The control schemes (for DGs, FACTS contrivances, APF etc.) that are predicated on the
postulation of the ideal (sinusoidal and balanced set) voltages to tackle these issues, may fail
if the voltage deviates from the ideal conditions. Thus, there is requirement of correct
estimation of the phase, frequency and the amplitude of the voltage under all (ideal and non-
ideal) conditions for the congruous operation of the DGs (or converters). Therefore it is
important to first attend the issue of correct estimation of the phase, frequency and the
amplitude of the fundamental positive sequence component of the grid signal [7].

The phase locked loop (PLL) which is based on time domain analysis is used to estimate
unknown quantity from PCC. The conventional PLL is unable to determine the unknown
quantity if grid signals are highly distorted (harmonics). Several modifications are there for
PLL like improved generalised filter enhanced phase locked loop (IGFEPLL) based control
algorithm [7]. This control algorithm estimates the amplitude and phase of signal.

Digital phase lock loop can be also used to extract harmonics by using modulated hopping
DFT (mHDFT) [8] which is used for up to 13th order harmonic mitigation. Digital phase lock
loop has several advantages over analog one and thus can be applied to mitigate harmonic
problems.

1.2 Problem Finding

For proper operation of power converter it is required to sense the grid voltage necessary for
synchronization and elimination of harmonics therefore it is required to get suitable PLL
scheme which will give information about grid voltage and frequency under the harmonics
and to utilize these scheme for successful harmonic compensation of current by power
electronics devices, also it is found that voltage quality is improved for multimode system
using optimized SAPF but complex conditions of noise are yet to be devised for harmonics.
Digital PLL can be helpful in this type of condition using mHDFT algorithm.

1.3 Objectives
1. Extraction of harmonics higher order harmonics using mHDFT algorithm in Digital
phase lock loop.
2. Reduction of error in mean square amplitude error (MSAE) due to adding white noise
as compared with Cramer-Rao lower bound in mHDFT algorithm.
3. Improvement in stability of existing mHDFT filters.
4. Reduction in time complexity of mHDFT filter.

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8
2. Methodology
2.1 Analog Phase-Locked Loop
A phase-locked loop consists of a phase detector and a voltage controlled oscillator.
The output of the phase detector is the input of the voltage-controlled oscillator (VCO)
and the output of the VCO is connected to one of the inputs of a phase detector
which is shown below in the basic block diagram. When these two devices are feed
to each other the loop forms.

The phase-locked loop is one of the basic blocks in modern electronic systems [9-10].
It is generally used in multimedia, communication and in many other applications.
There are two different types of PLL’s – linear and nonlinear. The nonlinear is difficult
and complicated to design in the real world, but the linear control theory is well
modelled in analog PLL’s. The PLL has proved that a linear model is sufficient for
most of the electronic applications.

Fref Voltage N×Fref

Phase
Low Pass Filter Controlled
Detector
Oscillator

÷N
Counter

Fig. 1: Basic diagram of phase locked loop (PLL)

In above block diagram VCO stands for Voltage controlled oscillator.

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2.1.1 Working Principle of PLL

The phase-locked loop consists of a phase detector, a voltage controlled oscillator and,
in between them, a low pass filter is fixed. The input signal ‘Vi’ with an input
frequency ‘Fi’ is conceded by a phase detector. Basically the phase detector is a
comparator that compares the input frequency fi through the feedback frequency fo.
The output of the phase detector is (fi+fo) which is a DC voltage. The out of the
phase detector, i.e., DC voltage is input to the low pass filter (LPF); it removes the
high-frequency noise and produces a steady DC level, i.e., Fi-Fo. The Vf is also a
dynamic characteristic of the PLL.

The output of the low pass filter, i.e., DC level is passed on to the VCO. The input
signal is directly proportional to the output frequency of the VCO (fo). The input and
output frequencies are compared and adjusted through the feedback loop until the
output frequency is equal to the input frequency. Hence, the PLL works like free running,
capture, and phase lock.

When there is no input voltage applied, then it is said to be a free-running stage. As

soon as the input frequency applied to the VOC changes and produces an output
frequency for comparison, it is called a capture stage. The fig. 1 shows the block diagram
of the PLL.

2.1.2 Phase-Locked Loop Detector

The phase-locked loop detector compares the input frequency and the output frequency
of the VCO to produces a DC voltage which is directly proportional to the phase
distinction of the two frequencies. The analog and digital signals are used in the
phase-locked loop. Most of the monolithic PLL integrated circuits use an analog phase
detector and the majority of phase detectors are from the digital type. A double
balanced mixture circuit is used commonly in analog phase detectors. Some common
phase detectors are given below:

2.1.3 Exclusive OR Phase Detector

An exclusive OR phase detector is CMOS IC 4070 type. The input and output frequencies
are applied to the EX OR phase detector. To obtain the output high at least one
input should be low and the other conditions of output are low which is shown in the
below truth table. Let us consider the waveform, the input and output frequencies, i.e.
fi and fo have a phase difference of 0 degrees. Then the DC output voltage of the
comparator will be a function of the phase difference between the two inputs. The
functions of the phase difference between the fi and fo is as shown in the graph of
DC output voltage. If the phase detector is 180 degrees, then the output voltage is
maximum. If both the input and output frequencies are square wave these type of the
phase detectors are used.

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fi
Vdc
f0

fi f0 Output

Low Low Low

Low High High

High Low High

High High Low

Fig. 2: Table for EXOR detector

Fig. 3: Exclusive OR Phase Detector

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2.1.4 Edge Trigger Phase Detector
An edge trigger phase detector is used when the input and output frequencies are in
pulse waveform, which is less than 50% duty cycle. The R-S flip flop is used for the
phase detectors, which is shown in the below figure. From R-S flip flop , the two NOR
gates are cross-coupled. The output of the phase detector can change its logic state by
triggering the R-S flip flop. The positive edge of the input and output frequencies can
change the output of the phase detector.

Fig. 4: Edge Trigger Phase Detector

2.1.5 Monolithic Phase Detector

A monolithic phase detector is a CMOS type, i.e., IC 4044. It is highly compensated
from the harmonic sensitivity and the duty cycle problems are abandoned as the circuit
can respond only to the transition of the input signal. In critical applications, it is the
most fevered phase detector. The independent variations of the amplitude are free from the
phase error, output error voltage and duty cycle of the input waveforms.

2.1.6 Applications of Analog Phase-Locked Loop

● FM demodulation networks for FM operations.
● It is used in motor speed controls and tracking filters.
● It is used in frequency shifting decodes for demodulation carrier frequencies.
● It is used in time to digital converters.
● It is used for Jitter reduction, skew suppression, clock recovery.

2.1.7 Disadvantage of Analog PLL

Analog phase-locked loop has the disadvantages such as temperature drift and it’s susceptible
to the change of voltage. However this advantage is not present in Digital Phase lock loop.

2.2 Digital Phase Locked Loop (DPLL)

Digital PLLs are a type of PLL used to synchronize digital signals. While DPLLs input and
outputs are typically all digital, they do have internal functions which are dependent on analog
signals. There are four basic components of a DPLL.
 Phase Detector

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  Loop Filter
 Digital Controlled Oscillator (DCO)
 Divider

2.2.1 Working Principle of DPLL

There are various frequency synthesizers in which one among them is the phase locked loop
(PLL) where it plays a vital role in the wireless communications. The PLL has been
implemented on single chip which has become more economical and has been produced in
large scale in order to full fill the requirement of industry. These integrated chips have been
digitally integrated and it has been used as the mixed signals to minimize the power
consumption of the system such that they operate with low supply voltages. ADPLL which
operates all digitally. This provides the betterment over conventional analog PLL. They
overcome the issues of accuracy, skew tolerance due to the occurrence in the traditional VCO,
jitter and propagation delay. There is a fast locking system in the ADPLL due to the constant
operating voltage. Basically it uses the feedback loop in order to detect the lock in time and
scalability is achieved. In this proposed gating techniques have been used in order to optimize
the power efficiency of the system. The DCO plays a vital role in providing tuning range in
place of conventional charge pump. ADPLL which consists of three parts: digital phase
detector, digital loop filter and digitally controlled oscillator. DCO uses the gated ring oscillator
and the delay cells in order to compare the frequency range and the power consumption. This
digital Pll operates in the frequency range of 1.6KHz to 4.7GHz The fractional divider has been
placed in the feedback path to synthesize the frequency for the application of wireless
communication. All digital phase locked loop is used for generation of fast lock in time which
uses the technique called clock gating in order to reduce the power consumption of the system
where the leakage power get reduced. Here it consumes more dynamic power due to the
delaying time of the counter [11].

The local oscillator which is used in DCO occupies more space where they produce a very good
shape of sine wave and have frequency stability. The frequency is not changed whenever DC
supply voltage is changed where it occupies more space and the complexity gets increases. The
digital controlled oscillator with power amplifier uses the transformer of six ports where the
area of the chip is reduced. Time to digital converter basically consumes more time the
optimization of power is not managed properly. By using the fewer dithers in digital controlled
oscillator (LC oscillator) is coupled inductively to the varactor diode that maintains the tuning
range of the system.

The gated oscillator which uses five stage inverter rather than counters that reduces the leakage
power of the system. The capacitor based oscillator which produces better resolution and
occupies very less area but consumption of power is too high by using ladder based switched
capacitor . Injection based oscillator which is used in the generation of clock avoids the
accumulation of jitter due to rising edge of the clock. It improves the performance characteristic
of jitter. Though it reduces the jitter characteristic the robustness of spur is increased and the
overall efficiency of power is not optimized. Thus the scalability is reduced by the injection of
clock in the oscillator. The increment and decrement counter which has a
better hold and lock in range where the implementation in software is not highly possible . The
delay based digital controlled oscillator consumes less power but the period of locking is
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comparatively high than the ring oscillator. The Architecture consists of all digital parts such as
digital phase detector, digital loop filter and digitally controlled oscillator. It is feedback loop
where the reference signal is given as input to the phase detector and the v out is taken as output
from the DCO and it is feedback to the phase detector until the phase is locked.

2.2.2 Proposed Architecture

The block diagram of frequency synthesizer shown in fig. 5 has four components linear digital
phase detector, digital loop filter, digital controlled oscillator and programmable divider. These
blocks are implemented in transistor level using Cadence EDA tool in 180nm technology. Here
the digitally controlled oscillator has compared between ring oscillator and the delay cell,
where the delay cell has less operating frequency range and the locking period. So ring
oscillator is preferred. The feedback loop consists of programmable divider where the output of
the divider has been fed back as the input of the phase detector and it has been compared and
the output has taken.

Fig. 5: Block diagram of Proposed ADPLL

2.2.3 Digital Phase detector

(DPD) The linear phase detector shown in Fig. 6 composed of master and slave D flip-flop
which operates with the wide operating frequency. The input signal is of 1.2GHz and the clock
frequency is given as input where it produces the error voltage depending on the lead and lag
frequency of input signals. The clock frequency given is the negative edge triggered. Here the
up signal is produced which is given as input to the digital loop filter.
Error voltage = 2(s) 1(s)
= 200ns 155ns
= 45ns

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 Fig. 6: Block diagram of Linear Phase Detector

2.2.4 Digital Loop Filter (DLF)

The basic charge pump has been replaced with the digital loop filter. DLF consist of counter
using D flip-flop. It is composed of 3 bit synchronous counter where the clock frequency of
1.2GHz is given as input to the flip-flops. The function of the digital loop filter is that the phase
error produced by the phase detector reaches a constant value, so that it makes the transition
from unlocking state to locking state. The synchronous counter is used where the clock signals
have been fed in order to reduce the delay. This has been gated in order to reduce the leakage
current in order to maintain the power efficiency. The input frequency has been given for each
and every transition and there is a bit change for each and every transition of frequency.
Suppose the bit 2, bit 0, bit 1 are in high state then the bit 3 gets toggled and the transition
continues. This produces a stepwise increment and the phase detector and the counter produces
a stable DC voltage which has been fed as the input to the DCO.

2.2.5 Digital Controlled Oscillator (DCO)

The DCO is implemented by comparing the ring oscillator and the delay cell. The input to the
ring oscillator is from the loop filter. Basically ring oscillator is implemented using stage ratios
by changing the width and length where the ring delay cells consist of NMOS in series and
parallel architecture where the initial conditions have been set. Comparatively delay cell
consumes less power than the ring oscillator. Basically ring oscillator consists of chain of NOT
gates which is placed in the sequel of odd numbers where the width has 1u to 8u stage ratios.
The variation in the amplitude leads to jitter analysis. Delay cells have been finely suited for
the frequency synthesizer because of the low noise and the delay has been comparatively
reduced than the classic ring oscillator. The power consumed is also less of about 2.2mV. The
inputs to the delay cell have been given accordingly to the input frequency and the less power
consumption. Oscillator has performed by comparing 3 stages and 5 stage ring oscillator
between frequency and power. The 3 stage ring oscillator parametric constraints shows better
results than the 5 stage ring oscillator.

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 Fig. 7: Block diagram of digital control oscillator

2.2.6 Programmable Divider

Programmable divider used 2/3 cell divider which is in series connection. The prescalar logic
and control logic are the parts of the divider. It consists of D Flip flop and the control signal P
is given as input to the depending on the modin. Whenever the P=’0’ it divides the input
frequency by 2 and when the P=’1’ it divides the input frequency by 3. Depending on the
control signals it programmes the circuit and the output modout is taken. This uses less power
by the fast division and thus it provides the wide range of logic functions.

Fig. 8: Block diagram of programmable divider

2.2.7 Modulated hoping DFT (mHDFT)
The modulated hoping DFT algorithm in PLL eliminates stability issue and accumulation error
with reduced computation complexity [8]. The mHDFT algorithm is mainly derived from basic
structure of SDFT by employing frequency shift property in sliding DFT (SDFT). Even through
mHDFT requires more computation than HDFT but it has better accuracy as twiddle factor
term is removed. Hence this serves as an advantage for extraction of harmonics.

2.2.8 Modulated hoping DFT (mHDFT) Algorithm

The mHDFT algorithm is mainly derived from basic structure of SDFT by employing
frequency shift property in SDFT. The kth bin of M point SDFT is computed from normal DFT
as

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 M −1
Sm (k )= ∑ x ( p+n)W −kn
M for k =0 , 1… M −1 (0)
n=0

Where p = m−M +1, and W M is the twiddle factor term. The recurring structure of (1) can be
represented by

Sm ( k ) = W kM [ Sm−1(k) + d(m)] (0)

Where d(m) = x(m)−x(m−M). By introducing random time hop L in SDFT, the Hopping
DFT(HDFT) algorithm can be expressed as

Sm ( k ) = W Lk S L
M [ m− L(k)+ D m (k)] (0)

L
Where Dm(k) is updating vector transform (UV T) that can be computed from fast DFT
algorithm. The UV T is expressed in (4).
L−1
DmL(k) = ∑ d (m−t)W (Mt− L+1) k (0)
t =0

The structure of HDFT is shown in Fig. 9:

Fig. 9: Hoping-DFT structure for window length M and hopping length L

The transfer function of HDFT (4) is given in (5)

L−1
H HDFT (z) = W kM (1 – z− M ) ∑ ¿ ¿¿ (0)
t=0

From (5), it is shown that the location of zeros and poles is dependent on M. Theoretically
HDFT is stable, but practically, it isn’t stable due to presence of twiddle factor (W kM ). Twiddle
factor may moves the poles and zeros from the unit circle and causes the system unstable [21].
17
To get rid of this issue frequency shift property is introduced in DFT to shift the k th bin DFT to
bin index at k = 0 by multiplying the input signal x(m) with modulating sequence W km0 M . By
introducing frequency shifting property and utilizing DFT value at k = 0, HDFT structure can
be modified as
L−1
Sm(k) = Sm− L(0) + ∑ d (m−t) (0)
t =0

0k
The input sequence in (6) can be multiplied by factor W −m M to shift k th bin DFT to index k = 0.
Then, the phase correction term W −M(m 0+ L ) k is required to multiply at the output to correct the
accumulated phase due to the modulation in time sequence. Therefore, the mHDFT is derived
from standard SDFT algorithm without any phase error as

Sm (k ) = W (Mm 0+ L ) k[ Sm−l ( 0 ) +W −km

M
0
D Lk (m)] (0)

Basic structure of mHDFT (7) is shown in Fig.9

Fig. 10: mHDFT structure with phase correction

From Fig. 9, it is quite visible that there is no twiddle factor term in recursive part. Therefore,
quantization error can be eliminated in mHDFT structure. The computational workload
comparison for different DFT algorithms is given in Table I. The symbols CM and CA are the
number of complex multiplication and complex addition respectively, where M is window
length and L is hopping length.

The computation workload of DFT, SDFT and SFFT depends on the size of M, where as it
depends on size of M as well as L for both HDFT and mHDFT. Since L is smaller than M, first
three methods require larger CM and CA computations compared to last two methods. Both
algorithms HDFT and mHDFT need same CA, but mHDFT requires more CM. This is due to
the fact that phase correction modulation sequence is introduced in mHDFT. Even though
mHDFT requires more computation than HDFT , it gives better accuracy as the twiddle factor
term is removed from recursive part by utilizing the modulation in time sequence from bin k =
0. Therefore, it is more superior than remaining HDFT algorithms at the expanse of little more
computation.

2.2.9 Technique for mHDFT

The basic structure of Phase Locked Loop (PLL) for harmonic extraction is shown in Fig. 9. It
consists of mHDFT filter, Moving Average (MA), Proportional Integral (PI) controller and

18
Numerically Controlled Oscillator (NCO). The mHDFT filter is designed by cascading single
comb filter and multiple resonators for bin k = 1, 3, 5, 7, 9, 11, and 13. The resonator
corresponding to bin value k = 1 is selected in designing a band pass filter to pass the
fundamental frequency f1 = 50 Hz from the input signal x(m). In power system application, odd
harmonics are more significant compared to even harmonics.

Fig. 11: Proposed Phased-Locked Loop model for harmonics estimation

Therefore, an input signal having fundamental frequency of f1 = 50 Hz and its odd harmonics
up to 13th components is given in (8).

x(m) = sin(2π50m)+0.333sin(2π150m)+ 0.2sin(2π250m)+0.143sin(2π350m)

+ 0.111sin(2π450m)+0.09sin(2π550m) (0)
+ 0.077sin(2π650m)

The harmonic signal x(m) represents the current or voltage in the power system up to 13th
harmonic. The resonator output is segregated into in-phase yI (m) and quadrature phase yQ(m)
components. Since the resonator for bin k = 1 is selected, the quadrature phase component is
derived as yQ(m) = AQ cos(2π50m + φ) where AQ is the amplitude and φ is the phase
difference that appears at the mHDFT output. The quadrature signal yQ(m) is allowed to
multiply with input signal x(m) to generate the dc and harmonic components of 50 Hz. The
resultant signal is passed through moving averager filter which acted as lowpass filter.
Therefore, fundamental frequency and higher harmonics are normally removed through
averager filter. Due to the leakage effect while designing the mHDFT, the output signal may
not be in pure sinusoidal from. The leakage effect normally arises from finite-precision effects
in the implementation of the adaptive filter design. If coefficient drift appears due to twiddle
factor terms there will be leakage effect. In such condition, a proper tuning is required to
smoothen the output signal.

A. Low-Pass Filter
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 A low-pass filter is designed from the standard SDFT structure by selecting bin k = 0. The
transfer function is given in (9).

1 [1−z −M ]
H MA(z) =
M −[1−Z ]
−1 (0)

The system function contents M zeros and one pole at z = 1. A single pole at z = 0 is canceled
out by a zero and resulting all zero filter. Therefore, the system is just a moving averager filter
as the output is weight-sum of the input signal. If the input signal (i) is multiplied with the
quadrature components yQ(m), then the resultant signal yMA(m) contents different harmonic
components.

yMA(m)= yQ(m)x(m)= AQ cos(2π50m+φ)[sin(2π50m)

+ 0.333sin(2π150m)+0.2sin(2π250m)
+ 0.143sin(2π350m)+0.111sin(2π450m) (0)
+ 0.09sin(2π550m)+0.077sin(2π650m)]

When yMA(m) (10) is applied to the low-pass filter (9), it will block the fundamental frequency
( f1 = 50Hz) and harmonic components of the input signal (8). DC component and its nearby
frequencies passed through the averager filter. Further, proper tuning is required to remove the
low frequency terms at the output of low pass filter.

B. PI Controller
A discrete PI controller is introduced in the PLL loop which consists of proportional and
integral controllers. Even when the phase error is zero under steady state condition, PI
controller continuously sends the dc input to the NCO unit. It helps in smoothening the output
signal through the proper selection of proportional and integral gains. The recurring structure of
PI controller is defined in (iv).

KI
H PI(z) = K p +
(1−z −1)
(0)

where KP and KI are proportional and integral gains respectively. The output of PI controller is
limited to ±1 through a limiter and then fed as input signal to NCO.

C.Numerically Controlled Oscillator (NCO)

Numerically Controlled Oscillator (NCO) is a type of digital oscillator designed by cascading

digital logic R −S latch and zero crossing detector. The difference equation of NCO in matrix
form is given in eq(12)

x 1(k +1) β β−1 x 1( k )

x 2(k +1)
= [
β+1 ]
β x 2( k ) (0)

20
where β is the controller output, x1(k) and x2(k) are Latch outputs. The output x1(k) is selected
and compared with reference signal (yr = 0) which acted as zero-crossing detector. The output
of zero-crossing detector is applied to a pulse generator to generate variable pulses. Therefore,
sampling frequency is adjusted according to sampling pulses that is delivered by NCO output to
the other units. Finally, NCO unit is designed to generate sampling pulses based on the output
of PI controller.

2.3 White Noise

Fig. 12: White Noise

In signal processing [12], white noise is a random signal having equal intensity at different
frequencies, giving it a constant power spectral density. The term is used, with this or similar
meanings, in many scientific and technical disciplines, including physics, acoustical
engineering, telecommunications, and statistical forecasting. White noise refers to a statistical
model for signals and signal sources, rather than to any specific signal.
2.3.1 Application of Noise
Music

White noise is commonly used in the production of electronic music, usually either directly or
as an input for a filter to create other types of noise signal. It is used extensively in audio
synthesis, typically to recreate percussive instruments such as cymbals or snare drums which
have high noise content in their frequency domain. A simple example of white noise is a non-
existent radio station (static).

Electronics engineering
White noise is also used to obtain the impulse response of an electrical circuit, in particular of
amplifiers and other audio equipment. It is not used for testing loudspeakers as its spectrum
contains too great an amount of high frequency content.

21
Computing
White noise is used as the basis of some random number generators. For example,
Random.org uses a system of atmospheric antennae to generate random digit patterns from
white noise.

Tinnitus treatment
White noise is a common synthetic noise source used for sound masking by a tinnitus masker.
White noise machines and other white noise sources are sold as privacy enhancers and sleep
aids (see music and sleep) and to mask tinnitus.[9] Alternatively, the use of an FM radio tuned
to unused frequencies ("static") is a simpler and more cost-effective source of white noise.
However, white noise generated from a common commercial radio receiver tuned to an
unused frequency is extremely vulnerable to being contaminated with spurious signals, such as
adjacent radio stations, harmonics from non-adjacent radio stations, electrical equipment in the
vicinity of the receiving antenna causing interference, or even atmospheric events such as
solar flares and especially lightning.

Work environment
Noise upon cognitive function is mixed. Recently, a small study found that white noise
background stimulation improves cognitive functioning among secondary students with
discredit is (ADHD), while decreasing performance of non-ADHD students. Other work
indicates The effects of white effective in improving the mood and performance of workers by
masking background office noise, but decreases cognitive performance in complex card
sorting tasks.
NOISE SOURCES AND SPECTRAL DENSITY
The fourth consideration is the ADC clock aperture jitter. Its effect can be estimated by When
a signal is sampled with an ADC, the digitized signal contains the wanted signal, plus noise
which arises via four mechanisms. The noise degrades the SNR from infinity, to some finite
number expressed in decibel. First, all analog input circuitry introduces a level of unavoidable
white noise. Second, some applications apply ADC dithering techniques to improve linearity,
which deliberately add white noise to the analog signal. Third, the signal is quantized as it is
sampled by the ADC, and assigned a digital value. The ADC quantization is (in theory)
perfect, but in reality also exhibits some level of integral nonlinearity (INL) and differential
nonlinearity

SNR (dB) Jitter = −20 log(2π fC · trms) (0)

where tRMS is the ADC clock aperture jitter (which should be much smaller than, and
distinguished from, clock accuracy and wander). In most commercial power system
applications, noise due to jitter is acceptably low, since fC is low (50–60 Hz), and typically trms
< 1 ns. For example, the AD7863 ADC has an aperture jitter of 50 ps [14], equating to an SNR
of ∼156 dB which is high, so that its effect is insignificant compared to other noise
mechanisms. A sampling process with N bits will always have ENOB ≤ N, by a quantity
dependent on the analog noise, and ADC imperfections. Some ADCs provide a recalculated
estimate of inherent ENOB which account for several of the mechanisms, at least in part.

22
However, the ENOB may be further degraded in the final application, due to analog sensors,
cables, circuits or amplifiers in the signal chain.
By convention, quoted ENOB values assume that the measurement signal spans the full ADC
range. However, in a practical application this is often not the case. ADCs need to be scaled so
that they can capture signal amplitudes larger than nominal without clipping. At the same time,
the most challenging measurement conditions include those where the signal amplitude is
smaller than nominal. In these cases, the practical SNR is degraded, by
A FullScale
SNR practical dB = SNRdB − 20 log10 ( A ) dB (0)
Actual

A Full Scale Actual dB (10) where A Full Scale is the maximum amplitude which can be measured
without clipping, and AActual is the actual signal amplitude.
In a scenario with a known (or estimated) SNR, at a sampling frequency fS, the relative power
spectral density of noise LdBc( f ) can be evaluated as
fs
LdBc( f ) = −SNRdB − 10 log10 ( 2 ) dBc/Hz (0)

Noise Reduction
All real measurements are disturbed by noise. This includes electronic noise, but can also
include external events that affect the measured phenomenon — wind, vibrations, the
gravitational attraction of the moon, variations of temperature, variations of humidity, etc.,
depending on what is measured and of the sensitivity of the device. It is often possible to
reduce the noise by controlling the environment. Internal electronic noise of measurement
systems can be reduced through the use of low-noise amplifiers.
When the characteristics of the noise are known and are different from the signal, it is possible
to use a filter to reduce the noise. For example, a lock-in amplifier can extract a narrow
bandwidth signal from broadband noise a million times stronger.
When the signal is constant or periodic and the noise is random, it is possible to enhance the
SNR by averaging the measurements. In this case the noise goes down as the square root of
the number of averaged samples.

Disadvantage of white noise

PROCESS SIGNAL DISTORTION
The most common and obvious problem caused by signal noise is the distortion of the process
signal, causing incorrect interpretation or display of a process condition by the equipment. The
addition to and/or subtraction from the process signal translates into an incorrect process
variable.

Apparent signal loss

Though uncommon, extreme signal noise can lead to an apparent loss of signal. Most modern
electronic equipment have built in noise filtering. However, in extremely noisy environments,

23
this filter will not be enough, which can lead to the equipment not receiving a signal and no
communication taking place at all.

Improper Control of process

The signal noise caused a miscommunication between devices. A system experiencing signal
noise fluctuations could inadvertently turn relays and alarms on / off at irregular intervals
because the noisy signals are being misunderstood. A situation like this results in the improper
control of an industrial process
White noise is used as the basis of some random number generators. For example,
Random.org uses a system of atmospheric antennae to generate random digit patterns from
white noise.

2.3.2 Cramer Rao bound

Placing a lower bound on the variance of any unbiased estimators can be extremely useful in
practices. This bound can allow us to conclude that the given estimator is minimum variance
unbiased estimator. At worst it can provide a benchmark for comparing the performance of
unbiased estimator. Cramer rao lower bound (CRLB) is the easiest to determine. According to
CRLB, estimators whose values are closer to CRLB are considered superior. The CRLB for
voltage signal at PCC in case of white Gaussian noise is given as

2 σ2
CRLB=
M
(0)
here M is the sampled length and σ is the noise variance.

Cramer-Rao Lower Bound on Frequency Offset Estimation Error is reported in literature [13].

2.4 SDFT and Sliding Goertzel

The Goertzel algorithm [14], used in dual-tone multifrequency decoding and phase-shift
keing/frequency-shift keying modem implementations, is commonly used to compute DFT
Spectra. The algorithm is implemented in the form of a second-order infinite impulse
response(IIR) filter. This filter computes a single DFT output (the kth bin of an N-point DFT)
defined by
N −1 πkn
− j2
X(k)¿ ∑ x (n)e N
(17)
n=0

The filter’s y(n) output is equal to the DFT output frequency coefficient,X(k), at the time index
n = N. For emphasis, we remind the reader that the filter’s y(n) output is not equal to X(k) at
any time index when n ≠ N. The frequency-domain index k is an integer in the range 0 ≤ k ≤ N
− 1. The z-domain transfer function of the Goertzel filter is

1−e− j 2 πk /n z−1
Hg(Z)= 1−2 cos 2 πk z −1 + Z−2 (18)
n ( )

24
with a single z-domain zero located at z =e− j2 πk/ nand conjugate poles at z = e j 2 πk /n. The
pole/zero pair at z = e− j2 πk/N cancels each other. The frequency magnitude Response shows
resonance centred at a normalized frequency of 2πk/N, corresponding to a cyclic frequency k f
N s ⋅ / Hz (where f s is the signal sample rate). While the Goertzel algorithm is derived from the
standard DFT equation, it’s important to realize that the filter’s frequency magnitude response
is not the sin(x)/(x)-like response of a single-bin DFT. The Goertzel filter is a complex
resonator having an infinite- length unit impulse response, h(n) = e j 2 πk /n , and that’s why its
magnitude response is so narrow.

The sliding DFT (SDFT) algorithm [14] performs an N-point DFT on time samples within a
sliding-window. In this example the SDFT initially computes the DFT of the N = 16 time
samples in Figure 3(a). The time window is then advanced one sample, as in Figure 3(b), and a
new N-point DFT is calculated. The value of this process is that each new DFT is efficiently
computed directly from the results of the previous DFT. The incremental advance of the time
window for each output computation is what leads to the name sliding DFT or sliding-window
DFT. The principle used for the SDFT is known as the DFT shifting theorem or the circular
shift property. It states that if the DFT of a windowed (finite-length) time-domain sequence is X
k ( ), then the DFT of that sequence, circularly shifted by one sample, is X(k)e− j2 πk/ n. Thus the
spectral components of a shifted time sequence are the original (unshifted) spectral components
multiplied by e− j2 πk / n , where k is the DFT bin of interest.
We express this process by

Sk(n)=Sk(n-1)e− j2 πk/ n-x(n-N)+x(n)

Here Sk(n) is the new spectral component and Sk(n-1) is the previous spectral component. The k
is reminded as spectra associated with kth DFT bin. This Equation reveals the value of this
process in computing real-time spectra. We calculate Sk(n)by phase shifting the previous
components, subtract the x(n − N) sample, and add the current x(n)sample. Thus the SDFT
requires only one complex multiply and two real adds per output sample. The computational
complexity of each successive N-point output is then O(N) for the sliding DFT compared to
O(N 2 )
for the DFT and O[N log (N)] 2 for the FFT. Unlike the DFT or FFT, however, due to its
recursive nature the sliding DFT output must be computed for each new input sample. If a new
N-point DFT output is required only every N inputs, the sliding DFT requires O(N 2 )
computations and is equivalent to the DFT. When output computations are required every M
input. Samples, and M is less than log 2 (N), the sliding DFT can be computationally superior to
traditional FFT implementations even when all NDFT outputs are required. implemented as an
IIR filter with a comb filter followed by a complex resonator. (If we want to compute all N
DFT spectral components, N resonators with k = 0 to N − 1 will be needed, all driven by a
single comb filter.) The comb filter delay of N samples forces the filter’s transient response to
be N − 1samples in length, so the output will not reach steady state until S k(n) samples. In
practical applications the algorithm can be initialized with zero input and zero output. The
output will not be valid, or equivalent to (1)’s X(k) until N input samples have been processed.
The z-domain transfer function for the kth bin of the sliding DFT filter is

1−z −N
H(z)= − j2
πk
N −1
(19)
1−e z

25
This complex filter has N zeros equally spaced around the z-domain’s unit circle, due to the N-
delay comb filter, as well as a single pole cancelling the zero at z = e j 2 πk /n. Because of the comb
subfilter, the SDFT filter’s complex sinusoidal unit impulse response is finite in length,
truncated in time to N samples, and that property makes the frequency magnitude response of
the SDFT filter identical to the sin(Nx)/sin(x) response of a single DFT bin centered at a
normalized frequency of 2πk/N. One of the attributes of the SDFT is that once Sk(n-1) an is
obtained, the number of computations to calculates Sk(n) is fixed and independent of N. The
SDFT filter is only marginally stable because its pole resides on the z-domain’s unit circle. If
filter coefficient numerical rounding error is not severe, the SDFT is bounded-input,
bounded-output stable. Filter instability can be a problem, however, if numerical coefficient
rounding causes the filter’s pole to move outside the unit circle. We can use a damping factor r
to force the pole to be at a radius of r inside the unit circle and guarantee stability using a
transfer function of
1−r z−N
H(z)= −j2
πk
N −1
(20)
1−ℜ z

2.5 Complexity of different algorithms

Algorithm CM CA

DFT M2 M2 - M

SDFT 2M 4M

SFFT M 2M

HDFT M M(1+log 2L) + L

log 2L
2

mHDFT M L + M (1+log 2L)

M+ log L2
2

The computational workload comparison for different DFT algorithms is given in Table I. The
symbols CM and CA are the number of complex multiplication and complex addition
respectively, where M is window length and L is hopping length. The computation workload of
DFT, SDFT and SFFT depends on the size of M, where as it depends on size of M as well as L
for both HDFT and mHDFT. Since L is smaller than M, first three methods require larger CM
and CA computations compared to last two methods. Both algorithms HDFT and mHDFT need
same CA, but mHDFT requires more CM. This is due to the fact that phase correction
modulation sequence is introduced in mHDFT. Even though mHDFT requires more
computation than HDFT , it gives better accuracy as the twiddle factor term is removed from
recursive part by utilizing the modulation in time sequence from bin k = 0. Therefore, it is
more superior than remaining HDFT algorithms at the expanse of little more computation.

26
3. Result analysis
The performance of the proposed PLL model for harmonic extraction is verified through
simulation. The mHDFT is implemented with window length 128 and hopping length L = 4.
Sampling frequency is taken to be 4 times fundamental frequency multiplied by window
length. The discrete domain signal with harmonics component up to 13 th order is considered
as a signal from power system.

Input signal,
x(m)=sin(2π50m)+0.333sin(2π150m)+0.2sin(2π250m)+0.143sin(2π350m)+0.111
sin(2π450m)+0.09 sin(2π550m)+0.077 sin(2π650m) (21)

The input signal is plotted below:

Fig. 13: Input signal

27
 Fig 14: Extracted harmonic components

In fig 14 corresponds to fundamental frequency component and 3rd, 5th, 7th, 9th, 11th and
13th harmonic components.

From the figure it is evident that PLL starts tracking the input after 20ms which is
fundamental time period. This means that the proposed phase-locked loop has the locking
time of 20 ms. The amplitude and frequency are accurately been tracked by the PLL. The
PLL thus works good.

3.1 With Noise

The Signal is added with white noise to test the noise handling capacity of the filter, the noise
power 0.00001969 is added to the input signal. The variance calculated is, σv = 0.5. The SNR
can be calculated as,

A2 (22)
SNR=10log 2
2σ

28
Here A2 is power of input signal.

The input signal added with SNR 0 dB is shown in Fig 15(a) and the extracted components is
shown in Fig 15(b). The harmonics components have clearly no frequency error but there is
amplitude error as clearly visible. The amplitude error is measured in terms of means square
amplitude error (MSAE) and the graph is plotted for MSAE vs. SNR of noise added. The
graph is compared with CRLB. The comparison plot is shown in fig 17. The input signal
added with SNR 10 dB is shown in Fig 16(a) and the extracted components is shown in Fig
16(b). The harmonics components have clearly no frequency error but there is amplitude
error as clearly visible. The amplitude error is less that SNR 0 dB.

Fig. 15: (a) White noise added signal with SNR 0dB

29
Fig. 15: (b) Extracted harmonic components with noise SNR 0dB

Fig. 16: (a) White noise added signal with SNR 10dB

30
 Fig. 16: (b) Extracted harmonic components with noise SNR 10dB

3.1.1 CRLB analysis

The Mean Square Amplitude Error (MSAE) is computed by adding white noise for SNR range
from −40 dB to 40 dB. The MSAE error (dB) of the amplitude measurement is compared with
CRLB in Fig. 17. The comparison plot shows that MSAE is quite approached to CRLB for
frequency range from −20 dB to 0 dB, and then it starts slowly deviating beyond this range.
The MSAE decreases as the SNR increases up to −20 dB. The value approaches to a constant
value of MSAE = −25 dB for SNR greater than 20 dB. The threshold value is found at SNR
=−20 dB.

Fig. 17 MSAE and CRLB for amplitude measurement (MSAE vs. SNR (dB))

31
3.2 Dc shift applied to input signal
The input sign in eqn 20 is added with dc signal of 5V and the plot is obtained in Fig 18. The
extracted components are perfect in frequency and amplitude and there is no error. Thus the
filter works for dc shift also.

Fig. 18: (a) Input signal with Dc shift of 5v

Fig. 18: (b) Extracted harmonic components for Dc shift 5v

3.3 Testing of signal with higher amplitude

Now the input signal with higher amplitudes in harmonic components is added to check
whether the filter works properly for higher amplitude or not.

Input signal,

32
 x(m)=100sin(2π50m)+40sin(2π150m)+30sin(2π250m)+20sin(2π350m)+
10sin(2π450m)+5 sin(2π550m)+ 4sin(2π650m)
(23)

The input signal is show in Fig 19(a) and harmonic components extracted are shown in Fig
19(b). The extracted components are having no error in amplitude measurement and
frequency measurement. Thus the filter works for higher amplitude also.

Fig. 19: (a) Input signal with fundamental harmonic amplitude 100v

Fig. 19: (b) Extracted harmonics component with new amplitude

33
3.4 Stability of low pass filter
From the pole zero plot of low pass filter there are 128 zeros for M=128 on unit circle and
and one pole on unit circle. The filter is thus marginally stable. The frequency response is
plotted in figure 16 (b). Clearly from frequency response we can say the filter work as low
pass filter. The transfer function used is,

1−z−M
HMA(z)= M [1−Z−1 ]
(24)

Fig. 20(a): pole zero plot of low pass filter

34
 Fig 20(b): frequency of low pass filter

Pole zero plot of SDFT filter with N=20 and k=1 is show in 21(a). The SDFT filter is only
marginally stable because its pole resides on the z-domain’s unit circle. If filter coefficient
numerical rounding error is not severe, the SDFT is bounded-input, bounded-output stable.
Filter instability can be a problem, however, if numerical coefficient rounding causes the
filter’s pole to move outside the unit circle. We can use a damping factor r to force the pole to
be at a radius of r inside the unit circle and guarantee stability. The frequency response is
plotted in fig 21(b) and clearly one can see the filter work for passing fundamental frequency
as k=1.

Transfer function of SDFT filter is,

1−z −N
H(z)= − j2
πk
N −1
1−e z (25)

35
Fig 21(a): pole zero plot of SDFT filter with n=20 and k=1

Fig 21(b): frequency response of SDFT filter

36
Pole zero plot of Sliding Goertzel filter with N=20 and k=1 is show in 21(c). Clearly this is
marginally stable but computation is less than SDFT. The frequency maginitude response
shown in fig 21(d) show resonance centred at normalised frequency 2πk/n (=0.314 for n=1
k=20).

The transfer function of sliding goertzel used is,

1−e− j 2 πk /n z−1
H(z)= 1−2 cos 2 πk z−1 + Z−2
n ( ) (26)

Fig 21(c): pole zero plot of Sliding Goertzel with n=20, k=1

37
 Fig 21(d): frequency response of Sliding Goertzel

Conclusion
From the various literature we have find the current problems in power quality in modern
power system. The major problem we find is that of harmonic. The digital PLL with certain
algorithm like mHDFT can be also used to extract harmonic which has better accuracy than
HDFT or SDFT. By simulation we have successfully implemented mHDFT technique in
phase lock loop and found that it can be applied in power system for harmonic estimation.
Also noise handling capacity is tested of filter. The algorithm gives less computation and
higher accuracy compared with other DFT algorithms. The capability of the harmonic
measurement has been verified for odd harmonic range from 50 Hz to 650 Hz. The filter is
checked with noise of different SNR. The MSAE is compared with CRLB and as a result we
get the estimator can work best with SNR upto -20 dB. The filter is also checked with high
amplitude input signal and the result shows it works well for higher amplitude. The dc shift
of input signal is also checked and we again found it work’s good. Finally we can conclude
the technique works well and can be applied to analyse harmonic components in power
system.

38
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