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IEEE TRANSACTIONS ON PLASMA SCIENCE
Design Considerations for a Fast
Stacked-MOSFET Switch
Martin Sack, Sebastian Keipert, Martin Hochberg, Mario Greule, and Georg Mueller
Abstract— For fast pulse generators using pulse-forming lines
for energy storage, a fast MOSFET is employed as switch.
It needs to have the capability of switching on the current
within a short rise time. Fast switching of MOSFET requires
the gate driver next to MOSFET in order to minimize the
inductance. To increase the voltage switching capability of a
MOSFET switch, several MOSFETs are switched in series. For
such a configuration, a synchronous switching of MOSFETs is
crucial. Hence, the gate drive circuitry needs to be designed to
have equal propagation delay for each MOSFET. The circuitry
for two stages of a stacked MOSFET switch including power
supply and trigger circuit is designed, set up, and tested. The
paper describes some design considerations and shows the results
of some first tests.
Index Terms— MOSFET switch, pulse generator.
I. I NTRODUCTION
F OR investigations on the influence of high pulsed electric
fields on fast rise time and pulse lengths in the 10-ns
range on biological cells, the use of a semiconductor-based
Blumlein-type pulse generator is of advantage. Short and fast
rising pulses of appropriate amplitude have an influence on
the inner organelles of biological cells. This is a difference
to slowly rising pulses which charge rather the outer cell
membrane and may cause their permeabilisation [1]. In com-
parison to pulse generators equipped with spark gaps, the
use of semiconductor switches enables a more precise control
of the pulse amplitude and a low jitter of the switching
moment. For fast pulse generators using pulse-forming lines
for energy storage, a fast MOSFET might be employed as
switch. Discrete MOSFETs are capable of fast switching with
a rise time in the order 2–5 ns [2], [3].
To increase the voltage switching capability of a MOSFET
switch beyond the maximum allowed drain–source voltage of
a single MOSFET, several MOSFETs might be switched in
series. When stacking MOSFETs, an equal voltage distribution
between the stages in OFF state and a fast and synchronized
switching of the stack is important in order to avoid excessive
voltage stress to single stages.
Fast switching of a MOSFET requires the appropriate
power for charging the total gate capacitance, i.e., the gate–
Manuscript received December 21, 2012; revised April 29, 2013; accepted
May 26, 2013.
The authors are with Karlsruhe Institute of Technology, Institute
for Pulsed Power and Microwave Technology, Eggenstein-Leopoldshafen
76344, Germany (e-mail: martin.sack@kit.edu; sebastiankeipert@web.de;
martin@hochberg.de; mario.greule@gmail.com; georg.mueller@kit.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPS.2013.2267395
0093-3813/$31.00 © 2013 IEEE
1
source capacitance and the drain–gate capacitance increased
according to the Miller effect [4]. Hence, a low inductance
of the gate drive circuit is crucial. Both the magnetic and
electric coupling enable a transfer of the energy required for
gate driving from one single gate driver to all MOSFETs. But
due to the considerable inductance of such a loop, a fast rise of
the gate signal requires some circuitry for pulse shaping next to
the MOSFETs. Alternatively, only a low-power trigger signal
is distributed to the stages requiring the power for gate driving
to be transferred to the stages separately. This solution has the
advantage that commercially available fast low-side drivers
can be employed for gate driving, but additional circuitry
for supplying energy to the stages of the MOSFET switch
is required.
II. D ESIGN OF THE S WITCH
A. Architecture and Component Selection
For a pulse generator design, based on pulse-forming lines,
only the switch needs to have the capability of switching on.
The pulse length is determined by length of the pulse-forming
lines. Hence, a semiconductor switch with a low fall time
of the drain–source voltage is required. The rise time is not
important. Two different devices are considered alternatively.
The MOSFET DE475-102N21A [2] is capable of switching a
maximum drain–source voltage, Vds of up to 1 kV and a peak
current of up to 144 A. According to its data sheet [2], a fall
time of Vds of ∼5 ns is achieved at Vds = 800 V and a pulsed
drain current of 72 A. An appropriate driver for this MOSFET
(DEIC420) is available [5]. The IGBT STGD6NC60H is as
well capable of switching on in ∼5 ns, but has a maximum
allowed gate–source voltage of 600 V only and a switching
capability of a pulsed collector current of 19 A according
to the data sheet [6]. The lower switching power of this
IGBT is compensated by its lower price. One design goal
is the capability of switching a pulsed current of at least
100 A in order to drive the resistive 50  load of a Blumlein
generator up to a voltage of 5 kV. To achieve a compact
design of the switch, a parallel configuration of two MOSFETs
DE475-102N21A are implemented instead of combining a
larger number of IGBTs. Fig. 1 gives an overview over the
system components. To use the MOSFET in combination with
its appropriate driver, an additional power supply via ferrite
core transformers driven by an ac current source is foreseen.
Transformers are chosen for the distribution of trigger signal
to the stages also.
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2 IEEE TRANSACTIONS ON PLASMA SCIENCE
Fig. 1. Overview of components for a stacked MOSFET switch.
Fig. 2. Trigger pulse generator with fast IGBT and avalanche transistor.
B. Trigger Circuit
The trigger circuit generates a pulse for switching on the
stacked MOSFETs. Each stage is equipped with a timer circuit
for switching OFF the MOSFET well after the discharge of
the pulse forming line (PFL). A low jitter of the switching
time and, hence, a good synchronisation of the stages can
be achieved by a fast rising trigger signal. To achieve a
steeper rise of the trigger signal than the fall time of Vds
of the employed MOSFETs, a combination of the fast IGBT
STGD6NC60H and a bipolar transistor 2N5550 in avalanche
mode are used. Fig. 2 shows a simplified schematic of this trig-
ger circuit, and Fig. 3 shows the measurements of collector–
emitter voltages of Q1 and Q2 and the load current through
R1. C1 is charged to a dc voltage of ∼400–500 V via R3
and R4. For pulse generation, Q1 is switched on grounding
the positively charged terminal of C1. As a consequence,
negative voltage with respect to ground is applied to the
emitter terminal of Q2. The voltage across Q1 falls within
∼6 ns applying the voltage with the same rise time to Q2.
Because of over-voltage, the collector–base diode of Q2 suffers
a reversible avalanche breakdown causing fast switching of
Q2. The voltage across Q2 falls within ∼3 ns.
A loop of high-voltage cable which is fed through a sec-
ondary winding at each stage of the MOSFET switch is used to
Fig. 3. Test of trigger pulse generator. Collector–emitter voltages of Q1 and
Q2 and load current through R1.
Fig. 4. Transformer for trigger pulse transmission.
transfer the trigger signal to the stages (Fig. 4). The secondary
winding might be designed either in the way of a Rogowski
coil, i.e., with an integrating element, or as a Ḃ-probe without
integration. The first approach requires a low inductance of the
cable loop for the trigger signal distribution such that it does
not limit significantly the rise of the trigger pulse. Employing
a Ḃ-probe has the advantage that the inductance of the cable
loop can be used as integrating element. The pulse length of
the trigger pulse induced in the secondary winding corresponds
to the rise of the current in the loop. Hence, for a constant
rise of the current independent of the loop inductance, the
inductance of the loop can be compensated by increasing the
applied trigger voltage according to
dI U
= . (1)
dt L
To lower disturbance because of capacitive coupling, the
secondary winding is shielded by means of an inner cylinder
made of copper forming an enclosure together with the copper
layers of the stage’s printed circuit board and an additional
covering board. The shield is connected to the local ground
potential via a connection of low impedance.
At each stage, the length of the trigger signal is expanded by
means of a monoflop to a length sufficient for fully discharging
the generator’s pulse forming transmission line. The output
signal of the monoflop is used as an input signal for the gate
drivers of both MOSFETs.
C. MOSFET and Driver
After assembly, the switching delay of the stages can be
matched by means of a RC delay stage in the signal chain
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SACK et al.: DESIGN CONSIDERATIONS FOR A FAST STACKED-MOSFET SWITCH
Fig. 5. Temperature-dependent signal propagation delay of delay stage,
driver, and MOSFET, as well as total delay time.
Fig. 6. Simplified schematic of one stage of the switch comprising the
winding for receiving the trigger signal (L1), a timer stage, MOSFET switches
(T1, T2) and gate drivers (GD), a heating system for both gate drivers
(H1, H2), and the power supply.
of each switching stage. For reliable long-term operation, a
constant propagation delay over time is important. MOSFETs
are known to have constant switching delays as the capac-
itances do not vary significantly with temperature or time.
Nevertheless, a test shows a slight temperature dependence
of the driver DEIC420. The diagram in Fig. 5 shows the
propagation delays of the delay stage, the driver DEIC420, and
the MOSFET DE475-102N21A at 25 ◦ C and ∼55 ◦ C. While
the propagation delay of the delay stage decreases by <1 ns
and one of the MOSFET stays nearly constant, the propagation
delay of the driver decreases by 3.1 ns with the rise in
temperature. The total propagation delay varies by 4 ns. Hence,
for a precise synchronization of the stages, it is of advantage
to keep all the drivers at an equal temperature. Therefore, a
heating system for the drivers is implemented. Fig. 6 shows the
simplified schematic of one stage of the switch comprising
the secondary winding for receiving the trigger pulse (L1),
the timer including the delay stage for matching switching
delays, and two MOSFET switches (T1, T2) together with
its drivers. Additional MOSFETs serving as heaters at both
sides of the drivers (H1, H2) are operated in linear regime
and supply heat to the drivers via the circuit board’s copper
layer. A feedback control loop keeps the temperature constant
even because of heat transfer from neighbored devices, such as
3
Fig. 7. One stage of MOSFET switch.
Fig. 8. Simplified schematic of the ac current source for supplying the
MOSFET switch.
power MOSFETs. A photo of one stage is shown in Fig. 7. The
power supply needs to be capable of supplying the required
heating power.
D. Power Supply
Fig. 8 shows a simplified schematic of ac current source
for supplying power to the stages of the switch. The ac
current source comprises a MOSFET half bridge (T1, T2)
driving an LC series circuit (CRes , L Res ). The inductance
consists of a discrete coil in series with a loop made of high-
voltage cable. This loop is fed through ferrite cores at each
stage carrying the secondary winding. The switching of the
MOSFETs is controlled in such a way that the LC circuit
is operated at its resonance frequency, and the MOSFETs
are switched when the current is near-zero only in order to
minimize losses (soft switching). The current through the loop
is sensed. A simple way of current regulation is implemented;
if the current amplitude exceeds a predefined limit, switching
of the upper MOSFET of the bridge is paused for one or more
cycles until the current amplitude falls below this limit. This
simple current regulation works fine as long as the resonance
circuit is damped only weakly, which can be guaranteed easily
by design. Each stage of the MOSFET switch is equipped
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4 IEEE TRANSACTIONS ON PLASMA SCIENCE
Fig. 9. AC supply current for the stages, output voltage of the half bridge,
and the voltage at the capacitor of the resonance circuit to ground.
with voltage regulation for the required supply voltages. All
stages are switched in series as well with respect to the power
supply. As they are all supplied with the same current, but their
power consumption may differ significantly due to the heating
of the drivers, the power flow to each stage is controlled by
temporarily shorting the stage’s transformer. For this feature, a
third winding is applied to the transformer instead of directly
shorting the transformer. So the current in the path for shorting
the stage can be lowered by an increased number of turns in
order to reduce losses.
III. T ESTING OF O NE S TAGE AND
A S TACK OF T WO S TAGES
So far, the power supply, the trigger circuit, and two stages
are assembled and tested.
A. Power Supply and Trigger Circuit
Fig. 9 shows the ac supply current for the stages (ISupply )
together with the output voltage of the half bridge (VHalfbridge)
and the voltage at the capacitor of the resonance circuit (VCres )
to ground. For supplying two stages, only the half bridge is
supplied by a dc-link voltage of 15 V. The supply current
ISupply is kept constant at 2.1 Aeff resulting in a voltage of
VCres = 163 Veff across the capacitor. The resonance frequency
is chosen to ∼100 kHz.
The generation of the trigger pulse is shown in Fig. 10.
Vloop is the mainly inductive voltage drop across the cable loop
caused by the rise of the trigger current. The loop inductance is
measured to L 1 = 0.22 μH. The inductance of the secondary
winding is L 2 = 0.52 μH. The coupling inductance L 12 is
determined to 0.02 μH. According to
L 12
k12 = √ (2)
L1 L2
the coupling factor between primary and secondary winding
is calculated to k12 = 7%, based on the measurements.
The trigger voltage across the secondary winding is limited
by diodes to get a rectangular shape.
Fig. 10. Generation of trigger pulse. Voltage across IGBT Q1 (according
to Fig. 2), voltage across loop measured at the terminals of the main trigger
circuit, and trigger voltage (VTrg in Fig. 6).
Fig. 11. Signal propagation within one stage of the MOSFET switch. Trigger
signal (VTrigger ) triggers the delay stage (VDelay ) delivering its signal to both
drivers. The signals VGate1 and VGate2 are the gate signals for both MOSFETs
(measurement at Vds = 0).
B. Switching Behaviour of One Single Stage
The signal propagation within one stage of the MOSFET
switch is shown in Fig. 11. The output signal of the delay
stage Vdelay is adjusted to a delay of 13 ns with respect to the
trigger signal. It triggers the two MOSFET drivers. Both driver
output signals VGate1 and VGate2 exhibit a difference in time
of 2 ns, which might be further reduced in a future design.
One stage of the switch is tested with an applied voltage
of between 200 and 1000 V. Fig. 12 shows the circuit of the
test setup. A 100-nF capacitor bank (Cs ) is discharged into
a load resistor with low inductance (RL ) via the switch. The
value of the load resistor is selected to 10  resulting in a
current of 100 A at 1 kV across the resistor. Fig. 13 shows
the applied voltages together with the voltages across the load
resistor and the trigger signal. In Fig. 14, the falling slope of
the voltage across the switch (Vds ) is magnified. The fall time
of Vds varies between 2.3 ns for the 200 V step to 6.1 ns for
the 1000-V step, both measured between the signal levels 10%
and 90%.
In addition to the tests with RC circuit, a set of coax-
ial cables in parallel configuration, each terminated with a
matched load is connected to the single stage of the switch.
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SACK et al.: DESIGN CONSIDERATIONS FOR A FAST STACKED-MOSFET SWITCH
Fig. 12. Schematic of the RC test circuit with measurement of drain–source
voltage, VDS , (Ch1) and voltage across the load resistor RL VR (Ch2).
Fig. 13. Drain–source voltage and voltage across load resistor R = 10 
during switching at different voltage levels together with the trigger signal.
Fig. 14. Drain–source voltage and voltage across load resistor R = 10 
during switching at different voltage levels, detail of switching moments.
Figs. 15 and 16 show the schematic and a photo of the test
setup. The PFL are charged via a decoupling resistor Rch
(Fig. 16A). Terminating resistors Rt (Fig. 16B) are placed
between the plugs for connecting the cables (Fig. 16C) and
5
Fig. 15. Schematic of test circuit with PFLs and measurement of drain–
source voltage (Ch1) and current by means of a shunt (RSh , Ch2).
Fig. 16. Test circuit with PFLs connected to a single stage of the MOSFET
switch.
a copper plane (Fig. 16D), which is connected to the stage
of the switch under test. A 50 m shunt Rsh (Fig. 16E) is
used for measuring the current through the switch. The drain–
source voltage is decoupled via a fast high-voltage probe. The
measurement signals are acquired by means of an oscilloscope.
For the photo the probe for measuring drain–source voltage is
removed. The load impedance can be varied by the number of
connected cables. For the test RG58 cables with a characteris-
tic impedance of 50  is used. Hence, each cable contributes
together with its terminating resistor Rt (Fig. 16B), a total
impedance of 100  to the parallel configuration. To achieve
a current of 100 A at a charging voltage of the cables of 800 V,
13 coaxial cables are employed resulting in a total impedance
of 8 . This current corresponds to the current required for
driving a 50  load at a voltage of 5 kV, as required for
the intended electroporation experiments. As the switch is
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6 IEEE TRANSACTIONS ON PLASMA SCIENCE

Fig. 19. Synchronized triggering of two stages. Trigger voltages and drain–
Fig. 17. Pulse currents for varying charging voltage V 0 between 200 and source voltages measured at two stages at VDS = 0.
800 V for the test setup according to Fig. 15.

Fig. 20. Stack of two stages switching a voltage of 1.6 kV into a 20  load
(C = 50 nF).

Fig. 18. Drain–source voltage and pulse currents for varying charging voltage
V0 between 200 and 800 V for the test setup accorrding to Fig. 15, detail of
switching moments.

operated as a closing switch, the pulse length is equivalent

to twice the travelling time of the pulse along the cable.
Fig. 17 shows the measured currents for a charging voltage V0
between 200 and 800 V. For 800 V charging voltage, a peak
current of 99 A is achieved. The pulse length is th = 43 ns,
measured between the rising and falling edge at half amplitude.
Fig. 18 shows the voltage across the switch together with the
current during switching for a charging voltage between 200
and 800 V. The fall time of the voltage, measured between
10% and 90% of V , varies between 6.3 ns for V0 = 200 V Fig. 21. Stack of two stages switching a voltage of 1.6 kV (RLoad = 20 ,
C = 100 nF). Trigger signal VTrigger , voltages VStage1 and VStage2 measured
and 7.1 ns for V0 = 800 V. The rise time of the current, also at the drains of each stage to ground, voltage across the load VLoad .
measured between 10% and 90% of I , varies between 6.0
and 7.6 ns accordingly.
The stack is tested by switching an RC circuit according
C. Stack of Two Stages to Fig. 12 with a capacitor of 50 nF, initially charged to a
A stack of two stages are assembled. For this test, the stages voltage of 1.6 kV and a resistor of 20 . So the load per
are mounted at a distance of 6 cm and 800-V-avalanche diodes stage is equivalent to 10  at a stage voltage of 800 V. The
are switched in parallel to each stage in order to protect the discharge time constant τ is equal to 1 μs. Fig. 20 shows
MOSFETs in case of malfunction. the voltages across the MOSFET stack and the load resistor.
Fig. 19 shows the trigger signals measured across the trigger A detailed view of the switching moment is shown in Fig. 21.
transformer’s secondary windings at each stage, and the gate– The voltages VStage1 and VStage2 are measured at the drains
source voltage of one MOSFET per stage. A delay of <1 ns of each stage to ground. The diagram shows an equal voltage
between both trigger signals are determined. Both gate signals distribution between the stages before and during switching.
exhibit a delay of ∼2 ns. The slight delay of the signal VStage2 is caused by an inductive
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SACK et al.: DESIGN CONSIDERATIONS FOR A FAST STACKED-MOSFET SWITCH 7

voltage drop across the connecting leads between stage 1 and
stage 2. For the final assembly of the switch, the stages will be
put closer together, and the connecting wires will be replaced
by stripes of copper in order to reduce the inductance.
IV. C ONCLUSION
For synchronized switching of stacked MOSFETs, a fast
rising trigger signal and an equal propagation delay in all
stages is required. The fast rising trigger signal was generated
by the combination of a fast IGBT and an avalanche transistor.
Trigger signal generation, power supply, and two stages of the
switch were set up and tested successfully. The next step will
be set up and testing of a larger stack of switch stages.
[3] (2012, Oct.). IXYS RF: Datasheet for MOSFET 275-
102N21A-00, Doc #9200-0247 [Online]. Available:
http://www.ixyscolorado.com/index.php/product?support/doc_download/
79-275x2-102n06a-00-datasheet
[4] U. Tietze and C. Schenk, Halbleiterschaltungstechnik. Berlin, Germany:
Springer-Verlag, 1990.
[5] (2012, Oct.). IXYS RF: DE-Series MOSFET, DEIC420 And SOP-28 IC
Device Installation & Mounting Instructions [Online]. Available:
http://www.ixyscolorado.com/index.php/product?support/ixysrf/
datasheets/doc_download/5-de-series-mosfet-deic420-and-sop-28-ic
[6] (2012, Oct.). ST Semiconductor: Datasheet for IGBT STGD6NC60HD
[Online]. Available: http://www.st.com/internet/com/TECHNICAL_
RESOURCES/TECHNICAL_LITERATURE/DATASHEET/
CD00058419.pdf

R EFERENCES
[1] K. H. Schoenbach, B. Hargrave, R. P. Joshi, J. Kolb, R. Nuccitelli,
C. Osgood, A. Pakhomov, M. Stacey, R. J. Swanson, J. A. White,
S. Xiao, J. Zhang, S. J. Beebe, P. F. Blackmore, and E. S. Buescher,
“Bioelectric effects of intense nanosecond pulses,” IEEE Trans. Dielectr.
Electr. Insul., vol. 14, no. 5, pp. 1088–1109, Oct. 2007.
[2] (2009, Oct.). IXYS RF: Datasheet for MOSFET 475-
102N21A-00, Doc #9200-0247 [Online]. Avilable:
http://www.ixyscolorado.com/index.php/product?support/doc_download/
77-475-102n21a-00-datasheet Authors’ biographies and photographs not available at the time of publication.