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Experiment No.: 8

AIM: To Implement Interrupt Programming for AVR ATmega32.

Apparatus - Atmel Studio, Easy AVR7

Objectives:
 To learn the difference between polling and interrupt based programming
 To use the timer interrupt
 To use external hardware interrupt
Theory:
There are two methods by which a microcontroller can serve a device
1- Interrupt: In interrupt method, a device sends an interrupt signal to
microcontroller. Upon reception of interrupt, microcontroller stops its working
and serves the device. Program executed after receiving an interrupt is called
Interrupt Service Routine (ISR).

2- Polling: In polling, microcontroller continuously monitors the status of

device, if the status is met, microcontroller serves the device. In polling method,
microcontroller can only check single device at a time.

Interrupt Vectors in ATmega32:

Vector
Address Source Interrupt Definition
No.
External Pin, Power-on Reset, Brown-out
1 $000 Reset Reset, Watchdog Reset, and JTAG AVR
Reset
2 $002 INT0 External Interrupt Request 0
3 $004 INT1 External Interrupt Request 1
4 $006 TIMER2 COMP Timer/Counter2 Compare Match
5 $008 TIMER2 OVF Timer/Counter2 Overflow
6 $00A TIMER1 CAPT Timer/Counter1 Capture Event
7 $00C TIMER1 COMPA Timer/Counter1 Compare Match A
8 $00E TIMER1 COMPB Timer/Counter1 Compare Match B
9 $010 TIMER1 OVF TIMER1 OVF Timer/Counter1 Overflow
10 $012 TIMER0 OVF Timer/Counter0 Overflow
11 $014 SPI, STC Serial Transfer Complete
12 $016 USART, RXC Rx Complete
13 $018 USART, UDRE USART Data Register Empty
14 $01A USART, TXC USART, Tx Complete
15 $01C ADC ADC Conversion Complete
16 $01E EE_RDY EEPROM Ready

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17 $020 ANA_COMP Analog Comparator

18 $022 TWI Two-wire Serial Interface
19 $024 INT2 External Interrupt Request 2
20 $026 TIMER0 COMP Timer/Counter0 Compare Match
21 $028 SPM_RDY Store Program Memory Ready

Above table shows the interrupt sources and their interrupt vectors for AVR ATmega16.
Memory locations from 0002 to 0028 locations are reserve for interrupt vectors. Each
interrupt has 2 words (4 bytes) of memory space for its ISR. For example, 0012 to 0014
memory space is set aside for Timer0 overflow ISR.
Usually ISR cannot fit into 4-bytes memory space. So a JMP instruction is kept at the
vector address from where ISR jumps to another location where rest of the code of ISR
can be written.
At the end of each ISR, RETI (Return from Interrupt) instruction is placed which gives
the control back to the location from where it was interrupted.
Steps to enable an Interrupt:
To enable any interrupt of AVR, we need to take the following steps:
1 Bit D7 (I) of SREG (Status Register) must be set in order to enable the global
interrupt. Without enabling global interrupt, no interrupt can happen. This can
be done by using SEI (assembly instruction) or sei(); (C instruction).
2 After enabling global interrupt, by setting the IE (Interrupt Enable) bit of each
interrupt, that specific interrupt can be enabled. For example, to enable Timer0
overflow interrupt, we need to set TOIE0 (Bit0 of TIMSK Register).

When interrupt is executed, Bit D7 of SREG is cleared by the microcontroller to avoid

the occurrence of another interrupt. Moreover, if Timer0 overflow interrupt is enabled,
TOV0 (Timer0 Overflow flag) is automatically cleared when microcontroller jumps to
the Timer0 overflow interrupt vector table.
TIMER INTERRUPTS:
Timer Interrupt Mask Register (TIMSK) holds the different interrupt enable bits related
to timers.

Bit # 7 6 5 4 3 2 1 0
Bit OCIE1
OCIE2 TOIE2 TICIE1 OCIE1A TOIE1 OCIE0 TOIE0
Name B

TOIE0 Timer0 overflow interrupt enable

OCIE0 Timer0 output compare match interrupt enable
TOIE1 Timer1 overflow interrupt enable
OCIE1 Timer1 output compare B match interrupt enable

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B
OCIE1
Timer1 output compare A match interrupt enable
A
TICIE1 Timer1 input compare interrupt enable
TOIE2 Timer2 overflow interrupt enable
OCIE2 Timer2 output compare match interrupt enable
These bits, along with D7 of SREG, when set, enable the corresponding interrupt.
Upon execution of interrupt, each flag is cleared by AVR itself and D7 of SREG is
also disabled to avoid further interrupt when ISR of an interrupt is being executed.

TIMSK (Timer Interrupt Mask Register)

EXTERNAL HARDWARE INTERRUPTS:
There are three external hardware interrupts are INT0, INT1 and INT2 located on pins
PD2, PD3 and PB2 respectively.

Bit # 7 6 5 4 3 2 1 0
Bit
INT1 INT0 INT2 - - - IVSEL IVCE
Name

INT0 External hardware interrupt request 0 enable

INT1 External hardware interrupt request 1 enable
INT2 External hardware interrupt request 2 enable

GICR (General Interrupt Control Register)

INT0 and INT1 can be programmed to trigger on low level, rising edge, falling edge or
both edges through MCUCR (MCU Control Register). Whereas, INT2 can only be
programmed to trigger on falling or rising edge through MCUCSR (MCU Control and
Status Register).
If an interrupt is programmed for edge trigger mode, the pulse must be 1 instruction
cycle to ensure that the transition is seen by microcontroller. If an interrupt is
programmed for level trigger, the pin must be held low for at least 5 machine cycles to
cause an interrupt.

Bit # 7 6 5 4 3 2 1 0
Bit
SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00
Name

ISC01 ISC00 Description

0 0 Low level of INT0 generates an interrupt request
0 1 Any logic change on INT0 generates an interrupt request
1 0 Falling edge of INT0 generates an interrupt request
1 1 Rising edge of INT0 generates an interrupt request

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ISC11 ISC10 Description

0 0 Low level of INT1 generates an interrupt request
0 1 Any logic change on INT1 generates an interrupt request
1 0 Falling edge of INT1 generates an interrupt request
1 1 Rising edge of INT1 generates an interrupt request

MCUCR (MCU Control Register)

Bit # 7 6 5 4 3 2 1 0
Bit
JTD ISC2 - JTRF WDRF BORF EXTRF PORF
Name

ISC2 Description
0 The falling edge of INT2 generates an interrupt request
1 The rising edge of INT2 generates an interrupt request

MCUCSR (MCU Control and Status Register)

GIFR (General Interrupt Flag Register) has external interrupt flags. When an external
interrupt is occurs, corresponding flag of that external interrupt is raised. When
microcontroller jumps of the interrupt vector table, flag is automatically cleared or we
can clear the flag by writing high on it.

Bit # 7 6 5 4 3 2 1 0
Bit
INTF1 INTF0 INTF2 - - - - -
Name

INTF1 When an external interrupt occurs, its corresponding flag bit in GIFR
INTF0 is set. When AVR jumps to its ISR, this flag is cleared by AVR. For level
triggering, pin must be hold for at least 5 instruction cycles to be
INTF2
recognized.

GIFR (General Interrupt Flag Register)

/***********************************************************************
This program generates a square wave of 5Hz (200ms) on PortA, Bit 0
using Timer0 CTC interrupt. Moreover, at the same time, using External
Hardware Interrupt INT2 is configured on falling edge. Upon each INT2
falling edge interrupt, value of PortD is incremented.
***********************************************************************/
// Calculations
// Crystal Frequency = XTAL = 4 MHz
// Frequncy to Generate = 5 Hz
// So its Time Pariod = 1/5 = 200 ms
// Using 50% duty cycle
// desired delay to generate = 200 ms / 2 = 100 ms
// for 100 ms delay

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// Scalar Timer Clock Time Period Total Counts

// none 1 MHz 1 usec 100000
// 8 0.125 MHz 8 usec 12500
// 64 15.625 KHz 64 usec 1562.5
// 256 3.90625 KHz 256 usec 390.625
// 1024 0.9765625 KHz 1024 usec 97.65625 <---
/////////////////////////////////////////////////////////////////////////

#define F_CPU 1000000UL

#include<avr/io.h>
#include<avr/interrupt.h>
int main(void)
{
DDRD = 0xFF; //Make PortD output
DDRA |= (1<<0); //Make PA0 output
DDRA &= ~(1<<2); //Make PB2 as input for INT2
PORTB |= (1<<2); //Internally pull-up PB2
TIMSK = 1 << OCIE0; //Enable OCIE0 bit to enable Timer0 Compare Mode
interrupt
GICR = 1 << INT2; //Enable INT2 bit to enable External Interrupt 2
MCUCSR = 1 << ISC2; //Configure Falling edge triggered INT2 interrupt
sei(); //Enable Global Interrupt
OCR0 = 98-1; //97.7 calculated for 0.1 seconds time
TCCR0 = 0x0D; //0000 1101, CTC Mode, Crystal Clock, 1024
prescaler
while(1); //Stay here forever
return 0;
}

//Interrupt Service Routine (ISR) for Timer0 Compare Match Interrupt

ISR (TIMER0_COMP_vect){
PORTA ^= 1<<0; //Toggle PA0
}

//Interrupt Service Routine (ISR) for External Interrupt INT2

ISR (INT2_vect) //ISR for External Interrupt INT2
{
PORTD++; //At every falling edge of INT2, increment PortD
}

Simulation:

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U1
9 22
RESET PC0/SCL
23
PC1/SDA
13 24
XTAL1 PC2/TCK
12 25
XTAL2 PC3/TMS
26
PC4/TDO
40 27
A PA0/ADC0 PC5/TDI
39 28
PA1/ADC1 PC6/TOSC1
38 29
B PA2/ADC2 PC7/TOSC2
37
PA3/ADC3
36 14
C PA4/ADC4 PD0/RXD
35 15
PA5/ADC5 PD1/TXD
34 16
D PA6/ADC6 PD2/INT0
33 17
PA7/ADC7 PD3/INT1
18
PD4/OC1B
1 19
PB0/T0/XCK PD5/OC1A
2 20
PB1/T1 PD6/ICP1
3 21
PB2/AIN0/INT2 PD7/OC2
4
PB3/AIN1/OC0
5
PB4/SS
6
PB5/MOSI
7 32
PB6/MISO AREF
8 30
PB7/SCK AVCC
ATMEGA32

Exercise: LOAD ABOVE PROGRAM IN EASY AVR 7 AND VERIFY THE OUTPUT.
HOMEWORK
1. Using Timer0, Write a Program that toggles pin PORTB.5 every 40us ,while at the
same time transferring data from PORTC TO PORTD. Assume XTAL-1 MHz.
Solution :

.ORG 0x0 ; location for reset

JMP MAIN
.ORG 0x14 ; ISR location for timer0 compare match
JMP T0_CM_ISR

Microprocessor and Microcontroller Subject Code: 3141008

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; main program for initialization and keeping CPU busy

.ORG 0X100
MAIN : LDI R20 , HIGH (RAMEND)
OUT SPH , R20
LDI R20 , LOW (RAMEND)
OUT SPL , R20 ; set up stack
SBI DDRB , 5 ; PB5 as output
LDI R20 , (1<<OCIE0)
OUT TIMSK , R20 ; enable Timer0 compare match interrupt
SEI ; Set I
LDI R20 , 39 ; Load R20 with 39
OUT OCRO , R20 ; load Timer0 with 39
LDI R20 , 0x09
OUT TCCR0 , R20 ; start Timer0 , CTC mode , int clk , no prescaler
LDI R20 , 0x00
OUT DDRC , R20 ; make PORTC input
LDI R20 , 0xFF
OUT DDRD , R20 ; make PORTD output
HERE : IN R20 , PINC ; read from PORTC
OUT PORTD , R20 ; send it to PORTD
JMP HERE ; Keep CPU busy
………..For Timer 1
T1_CM_ISR :
IN R16 , PORTB ; read PORTB
LDI R17 , 0x20 ; 00100000 for toggling PB5
EOR R16 , R17
OUT PORTB , R16 ; toggle PB5
RET ; return from interrupt

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2. Implement Project in Proteus, Assume that the INT0 pin is connected to a switch that
is normally high. Write a Program that toggles PORTC.3 whenever the INT0 pin goes
low.
Solution :

.INCLUDE "M32DEF.INC"
.ORG 0 ; location for reset
JMP MAIN
.ORG 0x02 ; vector location for external interrupt
JMP EX0_ISR
MAIN: LDI R20,HIGH(RAMEND)
OUT SPH,R20
LDI R20,LOW(RAMEND)
OUT SPL,R20 ; initialize stack
SBI DDRC,3 ; PORTC.3 = output
SBI PORTD,2 ; pull up activated
LDI R20,1<<INT0 ; enable INT0
OUT GICR,R20
SEI ; enable interrupts
HERE: JMP HERE ; stay here forever
EX0_ISR:
IN R21,PINC ; read PINC
LDI R22,0x08 ; 00001000
EOR R21,R22
OUT PORTC,R21
RET

Conclusion : Commonly used DC motors requires 12V supply and 300 mA current ,
moreover interfacing DC motors directly with Microcontrollers may affect the working
of Microcontroller due to the back EMF of the DC motor. Thus it is clear that it ‘s not a
good idea to interface DC motor directly with Microcontrollers.

Microprocessor and Microcontroller Subject Code: 3141008