EXPERIMENT-1

AIM- Design and implement a controlled CMOS inverter

Apparatus required- Probe

(2.5V),digital interactive constants,74136N
XOR gate

Theory - A CMOS inverter contains a PMOS and a NMOS

transistor connected at the drain and gate terminals, a
supply voltage VDD at the PMOS source terminal, and a
ground connected at the NMOS source terminal, were VIN is
connected to the gate terminals and VOUT is connected to
the drain terminals.

Here in the experiment we are using XOR gate to design a

CMOS inverter the output in XOR gate is asserted when odd
number of inputs are there thus it can be called the “odd
detector”.

Circuit diagram-
 OBSERVATIONS

In the above circuit diagram it can be seen that when

input is 0,1 then the probe lights up and similarly when
the input is 1,0 then also the probe lights up ,but it will
not light up for 1,1 or 0,0.
RESULT :

A B A ⊕B

0 0 0

0 1 1

1 0 1

1 1 0
The circuit diagram shown in the figure satisfies the
truth table of XOR gate shown above. Hence we have
designed a controlled CMOS inverter.
 EXPERIMENT-2

AIM- To study and verify the truth table of NAND and XOR gate
using IC7400

Apparatus required- Probe (2.5V), constants,IC7400

Theory -The NAND gate or “NotAND” gate is the

combination of two basic logic gates, the AND gate and the
NOT gate connected in series. The NAND gate and NOR gate
can be called the universal gates since the combination of
these gates can be used to accomplish any of the basic
operations. Hence, NAND gate and NOR gate combination can
produce an inverter, an OR gate or an AND gate.

The output of a NAND gate is high when either of the inputs

is high or if both the inputs are low.

XOR gate is a digital logic gate that gives a true output

when the number of true inputs is odd. An XOR gate
implements an exclusive or; that is, a true output
results if one, and only one, of the inputs to the gate is
true. If both inputs are false or both are true, a false
output results.
Circuit diagram-
OBSERVATIONS
 A B A ⊕B A B Y

0 0 0 0 0 1

0 1 1 0 1 1

1 0 1 1 0 1

The circuit diagram shown in the figure are of the

NAND gate and XOR gate respectively and from the
diagram we can verify the truth table.
RESULT

From the circuit diagram we have verified the truth

table of the NAND gate and the XOR gate using
IC7400.
 EXPERIMENT-3

AIM- Design and implement seven segment display unit.

Apparatus required- Seven segment display,
interactive key constants,IC7447

Theory - A seven-segment display is a form of

electronic display device for displaying decimal
numerals that is an alternative to the more complex
dot matrix displays. Seven-segment displays are
widely used in digital clocks, electronic meters, basic
calculators, and other electronic devices
that display numerical information.
Circuit diagram-

OBSERVATIONS
In the above circuit we can see that as we change the
binary input the number in the seven segment display
changes.
RESULT

The circuit diagram shown in the figure obeys the truth

table shown below-

a b c d e f g 7 SEGMENT OUTPUT

0 0 0 0 0 0 1 0

1 0 0 1 1 1 1 1

0 0 1 0 0 1 0 2

0 0 0 0 1 1 0 3

1 0 0 1 1 0 0 4

0 1 0 0 1 0 0 5

0 1 0 0 0 0 0 6

0 0 0 1 1 1 1 7

0 0 0 0 0 0 0 8

0 0 0 0 1 1 0 9

Hence we have created a seven segment display unit.

 EXPERIMENT-4

AIM- Design and verify half adder and full adder circuits
using gates and IC7483

Apparatus required- Interactive key

constants,IC7483,probe

Theory - Full Adder is the adder which adds three inputs

and produces two outputs. The first two inputs are A and B
and the third input is an input carry as C-IN. The output carry
is designated as C-OUT and the normal output is designated as
S which is SUM. But in this experiment we are using 4-bit
adder .
The addition of 2 bits is done using a combination circuit
called Half adder. The input variables are addend as bits and
output variables are sum & carry bits. A and B are the two
input bits.
Circuit diagram-
 OBSERVATIONS
In the above circuits we can see that the full adder
and half adders are obeying there respective truth
tables.
RESULT

The circuit diagrams shown in the figure obey the truth

table shown below-

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

INPUT DATA A INPUT B ADDITION

 DATA

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1

1 0 0 0 0 0 1 0 0 1 0 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0

1 0 1 0 1 0 1 1 1 0 0 1 0

1 1 1 0 1 1 1 1 1 1 0 1 0

1 0 1 0 1 1 0 1 1 0 1 1 1
Hence we have designed a full adder and a half adder.
 EXPERIMENT-5

AIM- Design and implement a 3:8 decoder.

Apparatus required- Interactive key
constants,IC74138,probe

Theory - A decoder is a combinational logic circuit that

is used to change the code into a set of signals. It is
the reverse process of an encoder. A decoder circuit
takes multiple inputs and gives multiple outputs.
We can also use two 2:4 decoders to make a
3:8 decoder.
Circuit diagram-

OBSERVATIONS
In the above circuit we can see that the circuit
obeys the truth table of a 3:8 decoder .
RESULT

The circuit diagram shown in the figure obeys the truth

table shown below-

INPUTS OUTPUTS

EN A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 x x x 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 0

1 0 1 0 0 0 0 0 0 1 0 0

1 0 1 1 0 0 0 0 1 0 0 0

1 1 0 0 0 0 0 1 0 0 0 0

1 1 0 1 0 0 1 0 0 0 0 0

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

Hence we have designed a 3:8 decoder

 EXPERIMENT-6

AIM- Design and implement a 8:3 priority encoder .

Apparatus required- Interactive key
constants,IC74148,probe

Theory - A priority encoder is a circuit or algorithm that

compresses multiple binary inputs into a smaller
number of outputs. The output of a priority encoder is
the binary representation of the original number starting
from zero of the most significant input bit.
Circuit diagram-

OBSERVATIONS
In the above circuit we can see that the circuit
obeys the truth table of a 8:3 priority encoder .
RESULT
 The circuit diagram shown in the figure obeys the truth
table shown below-

OUTPUTS INPUTS

EN Q2 Q1 Q0 D7 D6 D5 D4 D3 D2 D1 D0

0 x x x 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 x

1 0 1 0 0 0 0 0 0 1 x x

1 0 1 1 0 0 0 0 1 x x x

1 1 0 0 0 0 0 1 x x x x

1 1 0 1 0 0 1 x x x x x

1 1 1 0 0 1 x x x x x x

1 1 1 1 1 x x x x x x x

Hence we have designed a 8:3 encoder .