Ultra-Low Standby Power SRAM with Adaptive
Data-Retention-Voltage-Regulating Scheme
Chi-Ray Huang, Kuan-Lin Wu, Chung-Han Wu and Lih-Yih Chiou
Dept. Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Email: {n28981264, n26981828, n26040020, lihyih}@mail.ncku.edu.tw
Abstract—Leakage power dissipation has become a major
problem in advanced process technologies, especially in
large SRAM designs. The use of adaptive techniques is a
promising approach to decreasing power consumption
through dynamic scaling of the supply voltage of integrated
circuits. To obtain maximum reduction in leakage power,
an adaptive data retention voltage (DRV)–regulating
scheme is proposed to achieve substantial saving of SRAM
standby power. The proposed design supports DRV
operation from the above-threshold to subthreshold regions
and self-adapts to process, voltage, and temperature
variations by using the proposed DRV monitor. According
to the measurement results, the proposed design using 90
nm CMOS technology exhibits maximum leakage savings of
71.5%.
Keywords-SRAM; Data retention voltage (DRV); Standby
power
I. INTRODUCTION
With the advancements in semiconductor technology,
an integrated circuit (IC) may comprise millions of
transistors with versatile and complex functions.
Currently, SRAM is one of the major sources of power
consumption in a system-on-a-chip [1]. Moreover, the
leakage power dissipation of ICs has become a major
problem in advanced technology nodes. The techniques
for reducing SRAM standby power can be classified into
three categories: 1) reverse body bias [2], 2) negative
word-line [3], and 3) lowered VDD [4][5] or raised VSS
[6] (VDD scaling). Among these techniques, VDD
scaling is very effective because it can exponentially
reduce the subthreshold and gate leakage current when
the supply voltage is scaled down.
VDD scaling has the advantage of reducing standby
power; however, it also degrades the stability of SRAM
cells. This is because the scaling reduces the static noise
margin (SNM) of SRAM cells, which represents the
strength of noise immunity. VDD scaling cannot be
arbitrary and is limited by a minimum voltage called the
data retention voltage (DRV) [7]. The DRV is defined as
the minimum supply voltage at which all cells of a
SRAM can retain their states. Therefore, reducing the
supply voltage to the DRV during standby mode not only
results in maximum reduction of the SRAM standby
power but also ensures the safety of the data stored in
SRAM cells.
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In this paper, we propose an adaptive DRV–regulating
scheme (ADRVRS) to substantially reduce the SRAM
standby power by using three key features. 1) Voltage
converters are not used as the standby VDD under light
loads to avoid overhead. Instead, a power gating
technique is adopted to scale down the SRAM voltage. 2)
A closed-loop approach is adopted to solve the DRV
variability problem due to process, voltage, and
temperature (PVT) variations, and the data are kept safe.
3) By using a dynamic bias technique, the reaction time
of the DRV monitor in the ADRVRS can be reduced.
Therefore, the proposed scheme can effectively support
DRV operation in the subthreshold region.
The remainder of the paper is organized as follows.
Section II discusses the overall architecture of the
proposed ADRVRS, while Section III describes its
circuitry. Section IV discusses the simulation results.
Section V shows the measurement results, and finally,
Section VI presents the conclusions.
II. PROPOSED ADRVRS SYSTEM ARCHITECTURE
The overall architecture of the proposed ADRVRS is
shown in Fig. 1. It mainly comprises two parts: the
current controller for the active mode and adaptive
controller for the standby mode.
The current controller for the active mode is located on
the right-hand side of Fig. 1, where two PMOSs (main
header and subheader) are used to regulate the current to
the SRAM. The main header is switched on when the
SRAM operates in the active mode, while the subheader
is used to charge the Varray when the Varray drops to a
near-DRV level in the standby mode.
The adaptive controller for the standby mode is located
on the left-hand side of Fig. 1. It is used to adaptively
regulate the DRV of SRAM. The adaptive controller part
is composed of five blocks (subheader, DRV monitor,
data-loss detector, regulating controller, and dynamic bias
generator), which are detailed in Section III. The supply
voltage of the blocks filled with slashes (from upper right
to lower left) is set to VDDL (0.6 V), and that of the block
filled with backslashes is set to VDDH (1.2 V).
 drops because of power gating in the standby mode. As
the Varray drops to a near-DRV level, the subheader is
designed to increase Varray. The subheader is 512 times
smaller than the main header.

Fig. 1. System architecture of the proposed ADRVRS scheme.

Q → "1"
step 1 : system setting
QB → "0"
standby mode

main-header : off
step 2 : power gating sub-header : off
Varray ↓ (SRAM leakage)
Varray → near-DRV

Q & QB flip
step 3 : data -loss
DRV monitor : data-loss
Fig. 3. (a) Waveform of ADRVRS operation flow. (b) Waveform of
step 3 to step 6 in detail.
controller : charge
step 4 : start charging sub-header : on B. DRV monitor
Varray ↑ The value of the SRAM’s DRV must be adaptable to
Varray → safe voltage various situations when the SRAM voltage is lowered to a
near-DRV level. The DRV monitor cell is designed to
step 5 : stop charging controller : reset
&
monitor the voltage of the Varray. The states of Q and
sub-header : off
start resetting QB in the DRV monitor cell flip if Varray drops to the
DRV monitor : reset
DRV. Therefore, the DRV monitor generate a warning if
Q & QB reset done the supply voltage of the SRAM drops to a near-DRV
Q → "1" level. We propose maintaining the monitor’s DRV higher
step 6 : stop resetting
& QB → "0"
than the SRAM’s by adding a process-skew bias to the
process done sub-header : off
DRV monitor for preserving the data stored in the
SRAM. Fig. 4 shows the circuit diagram of the DRV
Fig. 2. Operation flow of the ADRVRS. monitor. It comprises three subblocks: the DRV monitor
cell, reset, and the process-skew injector.

Fig. 2 and Fig. 3 illustrate the operation flow and
waveform of the ADRVRS, respectively. The operational
flow comprises six steps. First, the values of nodes Q and
QB in the DRV monitor are set to “1” and “0,”
respectively. Steps 2 through 6 involve increasing Varray
to ensure the safety of the data. The Varray may drop
again because of SRAM leakage at some time point after
Step 6. When this occurs, the operation returns to Step 2.
III. PROPOSED ADRVRS CIRCUIT DESIGN
The proposed ADRVRS is used to adaptively regulate
the supply voltage of the SRAM to a near-DRV level
while maintaining the stored data safely in the standby
mode. It comprises five blocks (subheader, DRV monitor,
data-loss detector, regulating controller, and dynamic bias
generator), which are detailed as follows:
A. Subheader
The subheader is used to charge the Varray when the
Varray drops to a near-DRV level. The Varray gradually
As shown in the upper part of Fig. 4, the DRV monitor
cell is a duplicate column of the SRAM and comprises a
precharge circuit and 128 SRAM cells, which operate in
an unselected mode. All Q nodes are connected to
average out the random variations in the replica SRAM
cells, as for node QB. As shown in the middle of Fig. 4,
the signal Refresh is generated by regulating the
controller after the states of Q and QB flip. The DRV
monitor cell is reset if the signal Refresh or RST (the
system reset signal) is generated.
As shown in the bottom part of Fig. 4, the process-
skew injector is designed to adjust the stability of the
DRV monitor cell by connecting node Q to the ground
and node QB to the VDDL with a process-skew bias. In
addition, the process-skew bias, generated from the
dynamic bias generator, is adaptive to variations in the
DRV due to PVT variations.

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 proposed design reduces standby power by 62% in the
Varray
worst case (FF corner, 100°C). Fig. 6 shows the DRV of
the DRV monitor and SRAM cell at different corners and
temperatures. Fig. 7 shows the safe margin
(DRV_monitor – SRAM_cell) at different corners and
Varray
temperatures.
DRV Monitor Cell

BL BLB

GND

Q 128 QB

Varray

BL BLB

GND

DRV
Monitor
Varray
RST Reset
Refresh
ResetB
Q Reset QB Reset Fig. 5. Standby power reduction at different corners and temperatures.
GND
Reset

Sbias
Dbias
Process-
RST
From
Dynamic ResetB skew VDDL
Bias
Generator
Injector

Fig. 4. Circuit diagram of the DRV monitor.

C. Data-loss detector
The data-loss detector is used to identify when the
states of Q and QB in the DRV monitor flip. The
voltages of nodes Q and QB in the DRV monitor are (a)
very low because of power gating. Thus, the data-loss
detector not only senses the difference between the
voltages of Q and QB but also raises the voltage level
through level shifting internally.
D. Regulating controller
The regulating controller is used to generate the signal
Refresh, which is used to indicate the reset timing of the
DRV monitor, and the Pswitch signal, which is used to
indicate the open or close time of the subheader.
E. Dynamic bias generator
The dynamic bias generator is used to adaptively
generate the process-skew bias. It consists of leakage (b)
sources and a current mirror circuit. The leakage sources
Fig. 6. DRV at different corners and temperatures. (a) DRV monitor. (b)
comprise a precharge circuit and 128 SRAM cells, which SRAM cell.
monitor the chip leakage based on PVT variations. Thus,
the Dbias signal is proportional to the leakage from the
leakage source, and it passes to the DRV monitor to
adjust the reaction time of the DRV monitor.
IV. SIMULATION RESULTS
A 32 kb SRAM with the proposed ADRVRS was
fabricated using 90 nm CMOS technology, and
simulations were performed on the basis of a post-layout
netlist. Fig. 5 illustrates the SRAM standby power
reduction at different corners and temperatures in
comparison with a baseline SRAM of the same capacity
without any compensation scheme operated at a fixed
voltage of 1.2 V. The simulation results indicate that the Fig. 7. Safe margin = DRV_monitor – SRAM_cell.

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 Table I provides comparisons between the ADRVRS
and other schemes. The proposed scheme does not use
the scaled voltage generated by the voltage converters.
Instead, the power-gating technique is adopted to scale
the supply voltage of the SRAM.
TABLE I. Comparison of the proposed ADRVRS and other designs
* According to [13], the efficiency of the voltage converter is below 65% as long as the load
power is below 1 μW. The DRV of [7,8,9] is in the subthreshold region; therefore, the output
voltage of the voltage converter is below 0.5 V. Thus, the voltage converter in [7,8,9] must
waste >35% of power.
V. MEASUREMENT RESULTS
Fig. 8(a) shows a micrograph of the test chip. The area
overhead of the proposed ADRVRS accounts for only
2% of the SRAM area. When the SRAM enters the
standby mode, Varray drops to the DRV (VDRV) and then
periodically remains above the DRV. Fig. 8(b) shows the
measured operation results for the proposed ADRVRS,
where the cycle period is the ADRVRS cycle interval.
ΔV is the voltage range for charging and discharging the
Varray. TDRV is the time interval from the normal
operating voltage to the DRV. Table II shows the
measurement results for the proposed design, which
indicate that the proposed design achieves 64%–71.5%
leakage power saving for different chips.
TABLE II. Measurement results for the proposed ADRVRS
TDRV
Decoupling Capacitor
Main Header Cycle
& SRAM period
ADRVRS BIST & InputMux
Decoupling Capacitor VDRV
(a) (b)
Fig. 8. Proposed ADRVRS design using 90 nm CMOS technology. (a)
Chip micrograph. (b) Measured operation results.
VI. CONCLUSIONS
In this paper, an adaptive DRV–regulating scheme is
proposed to reduce SRAM leakage power. This scheme
not only has no extra power overhead of voltage
converters but also can adapt to DRV changes due to
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PVT variations by using the proposed DRV monitor.
Moreover, the proposed design supports DRV operation
from the above-threshold to subthreshold regions.
Furthermore, the SRAM measurement results with the
proposed ADRVRS design using 90 nm CMOS
technology indicate maximum leakage power savings of
71.5%.
ACKNOWLEDGEMENT
The authors would like to thank the Ministry of
Science and Technology of Taiwan for grants supports
(MOST 106-2221-E-006-239 and MOST 105-2218-E-
006-024) and National Chip Implementation Center for
their support through facilities for design, fabrication,
and measurement.
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