ELECTRONICS LABORATORY

FET AMPLIFIER

FET Amplifier

Course-Section : ECE20L-2

Group Number :

Group Members :

Date : April 26,2021

Course Instructor : Engr. Julius Sese

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 Figure 1.1. Circuit Board of JFET Device.

Part 1: Characteristics of JFET Device

Schematic Diagram:

1.1 Draw in LTSPICE the schematic diagram of JFET circuit shown in Figure 1.1. Use the
following components: VGG (dc voltage source at gate circuit), R1, Q1, R2, R3, and VDD
(dc voltage source at drain circuit). Do not connect in the circuit the CR1 and GEN. The
student or group should use different their own component values for the dc voltage sources
(VGG, VDD), resistors (R1, R2, R3), and JFET (Q1).

Here is a link about ‘Getting Started with LTSPICE’:

https://learn.sparkfun.com/tutorials/getting-started-with-ltspice/all

1.2 Take the photo of your circuit diagram drawn in LTSPICE tool, and place it as Figure 1.2.

One way to capture the screen in LTSPICE is: View > Paste Bitmap.
 Figure 1.2. Schematic Diagram of JFET circuit using LTSPICE Tool.

ID-VGS Characteristic Curve:

1.3 Set the VDD to a certain value. Sweep the value of VGG. Run a DC simulation in LTSPICE,
and plot the gate-to-source voltage (VGS) of JFET Q1 in x-axis and the drain current (ID) of
JFET Q1 in y-axis. Take a snapshot of the simulation results, and place it as Figure 1.3.

Figure 1.3. ID-VGS Characteristics of JFET.

 ELECTRONICS LABORATORY
FET AMPLIFIER

1.4 Record the details of simulation.

Part number of JFET= 2N3819

VDD= 0
VDS = -99.834983V_ (Drain-to-source voltage)
VGG(minimum) = -200V
VGG(maximum) = 100V
VGS(minimum) = -200V
VGS(maximum) = 100V
ID(minimum) = -6.4962068e-009fA
ID(maximum) = 5.8910587e-027fA

1.5 Based on the ID-VGS graph in Figure 1.3, briefly describe the effect of input gate-to-source
voltage (VGS) on the output drain current (ID), or the transfer characteristics, of
JEFT device.
● We were able to see the JFET's properties as a result of this. We were able to demonstrate that
when the gate diode is reverse biased, a depletion area forms on both sides of the PN Junction, extending
until the JFET channelA area that allows current to flow from the source to the drain. (Note that the drain
restricts current flow by narrowing the channel). The current that could flow would be reduced depending on
the input voltage. Since VGS is negative, only a limited amount of current flow was permitted.
ID-VDS Characteristic Curve:

1.6 Set the VGG to a certain value. Sweep the value of VDD. Run a DC simulation in LTSPICE,
and plot the drain-to-source voltage (VDS) of JFET Q1 in x-axis and the drain current (ID) of
JFET Q1 in y-axis. Take a snapshot of the simulation results, and place it as Figure 1.4.

Figure 1.4. ID-VDS Characteristics of JFET.

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 ELECTRONICS LABORATORY
FET AMPLIFIER

1.7 Record the details of simulation.

Part number of JFET = 2N3819

VGG = 0
VGS = 100 V
VDD(minimum) = -200V
VDD(maximum) = 100V
VDS(minimum) = -200V
VDS(maximum) = 100V
ID(minimum) = -36.22763 m
ID(maximum) = 12.46190 m

1.8 Based on the ID-VDS graph in Figure 1.4, briefly describe the output characteristics of JEFT
device.
We can see that the ID has reached its highest value and will remain there for the remainder
of the sweep. The drain current saturates, and increasing VDS will only make a minor difference in
the ID..

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 Figure 2.1. Circuit Board of JFET Amplifier.

Part 2: JFET Amplifier

Schematic Diagram:

2.1 Draw in LTSPICE the schematic diagram of JFET Amplifier shown in Figure 2.1. The
student or group should use different their own component values for input sine wave
generator GEN, gate resistor R1, source resistor R2, drain resistor R3, input coupling
capacitor C1, bypass capacitor C2, transistor Q1, and dc supply VDD.

Here is a link about ‘LTSPICE: Simple Steps for Simulating Transformers’:

https://www.analog.com/en/technical-articles/ltspice-basic-steps-for-simulating-transformers.html

2.2 Take the photo of your circuit diagram drawn in LTSPICE tool, and place it as Figure 2.2.

One way to capture the screen in LTSPICE is: View > Paste Bitmap.
 Figure 2.2. Schematic Diagram of JFET Amplifier using LTSPICE Tool.

DC Operating Condition:

2.3 Run a DC simulation in LTSPICE, and determine the terminal voltages of transistors at dc
supply VDD voltage.

Terminal Voltages of Transistor Q1:

VG = 24.288309µV
VD = 24.100527V
VS = 167.84419mV

2.4 Based on the measured terminal voltages, identify the bias condition of gate-source junction
of transistor Q1. Briefly explain you answer.
The gate-source junction of transistor Q1 is in a state of reverse bias since VG<VS,concludes that VGS is
equal to zero (VGS<0). The depletion region acts as it is when the effect of the negative-biased VGS is
applied, as to when VGS = 0V, lowering the VDS values.
2.5 Based on the measured terminal voltages, identify the bias condition of gate-drain junction
of transistor Q1. Briefly explain you answer.
Since VGVD, the gate-drain junction of transistor Q1 has been in reverse bias, resulting in
VGD0. This now creates a greater depletion field, which will eventually offset the rise in VDS and
keep ID stable.
2.6 Based on the measured terminal voltages, identify the operating condition of transistor Q1.
Briefly explain you answer.
Based on the experiment, to be able to operate to have the expected results where having VDD
will supply for the output, the operation condition for transistor Q1 is a very small amount of
voltage from G.
2.7 Take a snapshot of DC simulation waveforms, and place it in Figure 2.3.

Figure 2.3. DC Simulation of JFET Amplifier using LTSPICE Tool.

AC Operation:

2.8 Run transient simulations in LTSPICE. Adjust the amplitude of input sine wave generator
voltage and rerun the transient simulation until the voltage at the drain of Q1 becomes
undistorted. Determine the maximum amplitude of its input voltage that will result to an
undistorted output voltage.

Vin = -988.18242mV
Vo(undistorted) = 23.162784V
2.9 Based on the measured input and output voltages, calculate the amplification in terms of
voltage gain.

Av = -23.4397
 2.10 Take a snapshot of Transient simulation waveforms, and place it in Figure 2.4.

Figure 2.4. Transient Simulation of JFET Amplifier using LTSPICE Tool.

2.11 Based on the simulation results, explain the operation of JFET Amplifier.
As seen in the waveform of the experiment, it shows that the operation of JFET Amplifier in
the experiment, while there is a drop in voltage, the peak to peak of the input signal is amplified.
By this, the amplified signal is still amplified, so even if there was a noticeable drop in voltage,
the signal is still amplified, keeping the original goal of amplifying a signal without changing much
on the frequency.

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 Conclusion:

We were able to observe the JFET's characteristics. We were able to demonstrate that when the
gate diode is reverse biased, a depletion area forms on both sides of the PN Junction, stretching
until the JFET tube, allowing current to pass between the source and the drain. The JFET's
properties were visible. We were able to demonstrate that when the gate diode is reverse biased, a
depletion area is formed on both sides of the PN Junction, stretching until the JFET tube, allowing
current to pass between the source and the drain.