co intel’ 2101A 256 x 4 RAM WITH SEPARATE I/O 2101A-2 250 ns 2101A 350 ns Max. 2101A: 450 ns Max. = 256 x 4 Organization to Meet = Inputs Protected: All Inputs Needs for Small System Have Protection Against Memories Static Charge = Single +5V Supply Voltage = Low Cost Packaging: 22 Pin = Directly TTL Compatible: Plastic Dual In-Line All Inputs and Output Configuration = Statis MOS: No Clocks or = Low Power: Typically 150mW Refreshing Required « Three-State Output: OR-Tie = Simple Memory Expansion: Capability Chip Enable Input = Output Disable Provided for Ease of Use in Common Data Bus Systems. The Intel® 2101A is a 256 word by 4-bit static random access memory element using N-channel MOS devices integrated on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the input data The 2101A is designed for memory applications where high performance, low cost, large bitstorage, andsimpleinterfacing are important design objectives Itis directly TTL compatible in all respects: inputs, outputs, and a single *5V supply. Two chip-enables allow easy selection of an individual package when outputs are OR-tied. An output disable s provided so that data inputs and outputs can be tied for common 1/0 systems, The output disable function eliminates the need for bi-directional logic in a common 1/0 system The Intel® 2101A is fabricated with N-channel silicon gate technology. This technoiogy allows the design and production of high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip than elther conventional MOS technology or P-channel silicon gate technology. Intel's silicon gate technology also provides excellent protection against contamination, This permits the use of low cost plastic packaging PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM a S| anwar | 2-20 : nD oft, wee : nes x 2p a ——_ = erie ere “= wogeaee) THE late e oo Sp oa) {;2-00, | ag B00, =-8e50 -——stae Rea meee é 2:302101A FAMILY Absolute Maximum Ratings* 10°C to 80°C -88°C 10 +180°C ‘Ambient Temperature Under Bias . Storage Temperature Voltage On Any Pin With Respect to Ground -0.5V to +7V 1 Watt Power Dissipation “COMMENT: Stresses above those listed under “Absolute Maximum Raving" may cause permanent damage to the device. This is a stress rating only and functional operation of the de- vice at these or at any other condition above those indi cated in the operational sections of this specification is not implied. Exposure,to absolute maximum rating con- ditions for extended periods may affect device reliability. D.C. and Operating Characteristics Ta =0°C to 70°C, Veo = SV #5% unless otherwise specified Symbol Parameter Min.) Typ!"!| Max. | Unit | Test Conditions om Input Current a 10 Vi = 0 10 5.25V. Mow | WO Leakage Current!2] - 1 | 10 GE\=2.2V, Vour=4.0V Tro, 1/0 Leakage Current(2] Ei 10) CE, =2.2V, Your =0.45V__ Tecr | Power Supply 2101, 2101-4 35_| 55 Vin = 5.28V, lo = OmA Current DOA? 45 | 65 Ta = 25°C Tecs | Power Supply 21010, 210184 60_| mA | Vin =5.25V, I = OmA Current BIOTA mle Rete We Input “Low Voltage “05 v0.8 | Vv Vie Input “High” Voltage 2.0 Veco | V Vou | Output “Low” Voltage 4045 | Vf lous20mA Von | Output High” —2101A, 2101A2| 24 V_} Ton = -2000A Voltage 2a | 24 v Typical D. C. Characteristics ‘OUTPUT SOURCE CURRENT Vs. ‘OUTPUT VOLTAGE NOTES: 1, Typical values ae for Ta = 25°C and nominal supply voltage. (OUTPUT SINK CURRENT vs, OUTPUT VOLTAGE eoeseale Te i” ea i (SirePlow rma] 7 ry 231 cS2101A FAMILY 2 PEL tie: Mate OTT Fn, are Ol poet Subject eg iON. Soy A.C. Characteristics for 2101A-2 (250 ns Access Time) READ CYCLE Ta = 0°C to 70°C, Voc = SV 46%, unless otherwise specified. Symbol Parameter min. | Tye] Max. | Unit Test Conditions tre Read Cycle 250 08 ta, Recess Time 250] ns] tr. = 20ns co Chip Enable To Output 180_| ns top Output Disable To Output T30_|_ns_] Timing Reference = 1.5V Torll | Date Output to High Z State 0 180 ons] Load= 1 TTL Gate Previous Read Data Valid = and C, = 100pF. ton after change of Address a : WRITE CYCLE Symbol Parameter Min, Max. | unit | Test Con twe__| Write Gyele 170 ns Taw | Write Delay 20 ns | te, t¢= 20ns tow Chip Enable To Write 150 ns tow Data Setup 150 as__| Timing Reference = 1.5V Data Hold 0 fe | boad= 1 TTL Gate Write Pulse 150 8 ‘and C, = 100pF. Write Recovery 0 ns Tps | Output Disable Setup 20 7s fa A. C. CONDITIONS OF TEST Capacitance” 1, rr Input Pulse Levels: 40.8 Volt and 2.0 Volts —— CaF Gel Input Pulse Rise and Fall Times: 20nsee Symbol ca HFyp.ttl] Max, Timing Measurement Reference Level: 1.5 Volt Gv | Input Capacitance lee Output Load: 1 TTL Gate and C, = 100pF {All Input Pins) Vy = OV Tour | Output Capacitance Vour = @ [a2 Waveforms READ CYCLE WRITE CYCLE ADDRESS x X AODRESS x et x a | ie mn | /|_ : PAL __| ~ NOTES: 1. Typical values are for Ta = 25°C and nominal supply voltae, 2. Thisparameterisperiodically sampled and isnot 100% tested. 4. OD should be tied lov for separate 1/0 operation, 3. tp iswith respect to the trailing edge of CEy, CE, (0F 00, whichever occurs firs.2101A FAMILY 2101A (350 ns Access Time) A.C. Characteristics READ CYCLE Ta =0°C to 70°C, Voc = SV 5%, unless otherwise specitied. Symbo! Parameter Min. | Tys!| ax. | Unit | Test Conditions tac | Read Cyete 350 18 ta ‘Access Time 350 testy = 20ns te | Chip Enable To Output 240 Teo | Outart Disable To Output - 760 Timing Reference = 1.6 tor | Data Output to High Z State 0 150 | ns Load = 1 TTL Gate Previous Read Data Valid and Cy = 100pF. ton after change of Address om - WRITE CYCLE Symbol | ___ Parameter win | tvA"| aon, | Unit_[ Test Conditions we | Wate Cycle 220 18 Taw Write Delay ~ 20 ns te ty = 2005 tow | Ship Enable To Write 200 7 tow. Data Setup 200 ns ‘Timing Referencs tou | Data Hota ° ts | Load 1 TTL Gate tae | Wirt Puss 200 1 and Cy, = 100pF. wa | Write Recovery ° | Tos __ | Output Disable Setup 2 15 2101A-4 (450 ns Access Time) A.C. Characteristics READ CYCLE Ta = 0°C to 70°C, Voc SV 45%, unless otherwise specified \ 7] Symbol Parameter min | Tye] Max. | Unit | Test Conditions tac Read Cycle 450 ns ta Access Time BOs] te 20s too. Chip Enable To Output “310 ns 190 | Output Disable To Output 250 [ns] Timing Reference = 1.5V ‘orl | Data Output to High Z State o 200 [ns] Loed = 1 TTL Gate von | Previous Reed Data Vai 0 | and Cy = 1000F after change of Address | WRITE CYCLE Symbol Parameter Min Max. | Unit_| Test Conditions two Write Cycle 7 270 ns ta. Write Delay 20 ns ty, ty = 20ns ‘tcw | Chip Enable To Write 250 8 tow | Date Setup 260 ns] Timing Reference = 1.5 tou | Data ota 0 ts] Lood=1 TTL Gate twe | Write Pulse 250 1 and C, = 100pF. ‘twa | Write Recovery 0 1 Tos | Ontput Disable Setup 20 78 NOTES: 1. Typical velue are for Ta = 25°C and nominal supply voltage, 2. tpg ls with respect to the trailing edge of CE, CEz, oF OD, whichever occurs first. 2.33