CSCI3420 Computer System Architectures

Project Phase 2
Due date: 23:59:59 (GMT +08:00), 19 March, 2011

1. Introduction
This course project is intended to let you have a more in depth understanding of CPU architecture, by writing an
assembler of an assembly language, a single-cycle simulator and a multi-cycle pipelined simulator of a simplified
Single Instruction, Multiple Data (SIMD) CPU (but no floating-point operation). The project is divided into three
related phases. In phase 2, you have to write a single-cycle simulator in Very-High-Speed Integrated Circuit
Hardware Description Language (VHDL), so that you gain experience in understanding the datapath design and
how instructions are executed in a single cycle machine.

2. Architecture
Figure 1 in this specification show the datapath you need to simulate. The architecture you are simulating
is exactly the same with phase 1:
 each machine word has 32 bits
 memory size is exactly 1 MiB (20 bits are sufficient to specify an address)
 every instruction takes one machine word
 the machine is big-endian, i.e. the most significant byte come first
 the starting address of the main function is 0x4014 (the value is preloaded into $gp register, therefore you
don’t have to handle .globl directive in this project)
 the starting address of the stack memory is 0x4000 (the value is pre-loaded into $sp register)
 the registers available, instruction sets you have to implement, instruction encoding layout, opcode, format
code and function code are listed in the Phase 1 Specification and the Project Appendix

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Project Phase 2 Specification Revision 1.2 (Last Update:15 March 2011)
3. Single-cycle Simulator
You are required to write the core part of your MIPS processor (a simulator). The simulator is a single-cycle
datapath and has a simplified MIPS instruction set. The simulation tool that we will use is ModelSim PE10.

3.1 Processor_core Ports

Port Direction Meaning
clk In Clock signal
rst In Asynchronous active-high reset signal
run In Trigger the simulator to run
instaddr Out Instruction memory read address
inst In Instruction memory data
memwen Out Memory write enable
memaddr Out Memory address
memdw Out Memory write data
memdr In Memory read data
fin Out Indicate execution finish
PCout Out PC value when finish
regaddr In Register read address
regdout Out Register read data
FPaddr In FPR register read address
FPdour Out FPR register read data
When run is positive-triggered, the simulator would start executing the program loaded in the memory. When the
execution finishes, the fin should be set to “1” and the PCout should have the same value as the latest PC.

3.2 Register Files

3.2.1 GPR Registers to be handled
Port Direction Meaning
clk In Clock signal
rst In Asynchronous active-high reset signal
raddrA In Register read address 1
raddrB In Register read address 2
wen In Register write enable
wddr In Register write address
din In Register write data
doutA Out Register read data 1
doutB Out Register read data 2
extaddr In External register read address
extdout Out External register read data
Notice that read access to the register file is asynchronous while write access is synchronous, positive-edge
triggered. The extaddr and extdout signal in the regtable must be connected the regaddr and regdout in
the processor_core.

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Project Phase 2 Specification Revision 1.2 (Last Update:15 March 2011)
3.2.2 Special Registers ($hi and $lo) to be handled
Port Direction Meaning
clk In Clock signal
rst In Asynchronous active-high reset signal
rmode In Register read mode
wen In Register write enable
wmode In Register write mode
din In Register write data
doutA Out Register read data 32-bit
doutB Out Register read data 64-bit

3.2.3 FPR Registers to be handled

Port Direction Meaning
clk In Clock signal
rst In Asynchronous active-high reset signal
raddrA In Register read address 1
raddrB In Register read address 2
raddrC In Register read address 3
rmode In Register read mode
wen In Register write enable
wddr In Register write address
wmode In Register write mode
din In Register write data
doutA Out Register read data 1
doutB Out Register read data 2
doutC Out Register read data 3
extaddr In External register read address
extdout Out External register read data
Notice that read access to the register file is asynchronous while write access is synchronous, positive-edge
triggered. The extaddr and extdout signal in the regtable must be connected the regaddr and regdout in
the processor_core.

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Project Phase 2 Specification Revision 1.2 (Last Update:15 March 2011)
3.3 Memory Usage
An external memory model memtable described in VHDL code is given. The entity models the behavior of both
instruction memory and data memory. The ports and their meanings are tabulated below.
Port Direction Meaning
clk In Clock signal
rst In Asynchronous active-high reset signal
instaddr In Instruction memory read address
instdout Out Instruction memory data
wen In Data memory write enable
wmode In Date memory write mode
addr In Data memory address
din In Data memory write data
dout Out Data memory read data
extwen Out External memory write enable
extaddr In External memory address
extdin Out External memory write data
extdout In External memory read data
The instruction memory and data memory shares the same set of memory contents. Before the simulator starts
execution, the machine codes of the program to be executed will first be loaded into the memory through the
external memory port (extwen, extaddr, extdin and extdout). And after the execution is finished, the
memory contents and the registers contents would be read out. A testbench file called processor_tb.vhd is given to
use for program loading and result writing.

In processor_tb.vhd:
 “infile” is the machine codes file.
 “addrfile” is the memory address for reading results after execution.
 “resultfile” is the result file for writing the memory and registers contents.

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Project Phase 2 Specification Revision 1.2 (Last Update:15 March 2011)
4. Marking Scheme
There are n testcases and each testcase may carry different marks (marks are defined by the complexity of the
testcases). Your submitted program would be compiled and simulated using GHDL, so please make sure your have
used the correct ieee.numeric_std library for arithmetic calculations. A sample simulator runs in LINUX (same as
the sample simulator provided in Project Phase 1) will also be provided for you to test the behavior of your
simulator.

5. Assignment Submission
Zip the following with filename as “Phase2.zip”:
- Source code of your processor core
- A readme file that explain the features, possible bugs and limitations of your simulator
You MUST submit the ZIP file to the submission system on our course homepage (within CUHK network),
otherwise, we will NOT mark your assignment.

6. Important Points
You MUST STRICTLY follow these points:
- You MUST strictly follow the submission guidelines
- Late submission will NOT be entertained according to our submission system settings
- You can submit your project to our submission system more than once without any penalty, and only the
record with the highest mark will be recorded
- Plagiarism will be seriously punished

7. Late Submission
According to the course homepage, late submission will lead to marks deduction.

No. of Days Late Marks Deduction

1 10%
2 30%
3 60%
Will be marked,
4 or above but no marks will
be rewarded

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Project Phase 2 Specification Revision 1.2 (Last Update:15 March 2011)
 MUX
Add
Instr[25..0] Branch 32
Jump PC[31..28]
Shift
MUX imm[27..0]
left 2
Add Instr[31..26] WBctrl
Control
MEMop
4

writeSrc
regDst GPRctrl ALUsrc
ex
GPR1
Instr[25..21] Read Read MUX
Read FPR2[127..96] zero Read
Address register 1 data 1
ALUop Address
PC Read
ALU3 32
Instruction Instr[20..16] Read GPR2 [127..96] Read data
register 2 data 2 specialSrc
[31..0] [63..0] MUX
FPR3[127..96] 64
MUX
Instruction General Registers HI/LO Data
Memory imm Write Memory
Instr[15..11] Write Data
MUX
register {HI,LO}
31 MUX
GPR2
FPR2 MUX
Write data FPR3 FPR2[95..64]
128 128
MUX
FPR1[127..96] FPR2[63..32] ALU2
[95..64] 96
Special Registers FPR3[95..64]
64 MUX
Legend FPRctrl FPR3[31..0]
Solid - GPR Instr[25..21] Read Read FPR1[95..64]
register 1 data 1 Add
Dashed - FPR 128
Instr[20..16] Read Read FPR2[63..32]
Black - <=32bit register 2 data 2
Instr[15..11] 128 96 96 MUX
Orange - ctrl Read Read MUX
register 3 data 3 FPR2[31..0]
Blue - 64bit 128 96 96 ALU1 64
Green - 96bit Floating-point Registers [63..32]
ALU0[63..32]
Purple - 128bit Write FPR3[63..32]
Instr[10..6] MUX
Grey - .QS register SRctrl
format FPR1[63..32]
Write data
128 MADD.D
Instr[5..0] ALU
FPR2[31..0]
control
ALUop ALU0
MUX
[31..0]
Instr[15..0] Sign/zero ALU0[31..0]
extend 64
FPR3[31..0]
16 32
FPR1[31..0]

Figure 1. The single-cycle datapath to be implemented

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Project Phase 2 Specification Revision 1.2 (Last Update: 15 March 2011)