ADSP-2100 Family Core

Architecture 1
Introduction
 The ADSP-2100 Family processors are single-chip microcomputers
– optimized for digital signal processing (DSP)
– and other high speed numeric processing applications.
 They are all built upon a common core.
 Each processor combines the core DSP architecture:
– Computation units,
– data address generators
– program sequencer
 With differentiating features-
– on-chip program and data memory RAM
– a programmable timer
– one or two serial ports,
 ADSP-2111 with a host interface port.
ADSP-2100 Family Core Features
 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
 Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses
 Independent Computation Units: ALU,
Multiplier/Accumulator, and Shifter
 Single-Cycle Instruction Execution & Multifunction
Instructions
 On-Chip Program Memory RAM or ROM & Data
Memory RAM
 Integrated I/O Peripherals: Serial Ports, Timer,
 Host Interface Port (ADSP-2111 Only)
 Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
 Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
ADSP-21xx
 Fabricated in a high speed, submicron, double-layer metal CMOS process.
 the highest-performance ADSP-21xx processors operate at 25 MHz with a 40 ns
instruction cycle time.
 Every instruction can execute in a single cycle.
 Fabrication in CMOS results in low power dissipation.
 support a high degree of parallelism.
 In one cycle the ADSP-21xx can perform all of the following operations:
 Generate the next program address

–• Fetch the next instruction

–• Perform one or two data moves
–• Update one or two data address pointers
–• Perform a computation
Computational unit
ADSP-2100 contains three independent, full-function computational units:
A. an arithmetic/logic unit (ALU):performs a standard set of
 arithmetic and logic operations
 division primitives.
B. A multiplier/accumulator (MAC): performs
 single-cycle multiply,
 multiply / add and
 multiply/subtract operations.
C. a barrel shifter: Performs
 logical and arithmetic shifts,
 normalization,
 denormalization, and
 derive exponent operations.
 All three units contain input and output registers
which are accessible from the internal data
memory data (DMD) bus.
 Computational operations generally take their
operands from input registers and load the result
into an output register.
Address Generators :

Two dedicated data address generators and a

powerful program sequencer.
 The data address generators (DAGs) provide
memory addresses when memory data is
transferred to or from the input or output
registers.
 DAGl can supply addresses to data memory only;
 DAG2 can supply addresses to either data
memory or program memory.
Program sequencer:

 The program sequencer supplies instruction

addresses to the program memory.
 The sequencer is driven by the instruction register
which holds the currently executing instruction.
 the sequencer supports conditional jumps, subroutine
calls and returns in a single cycle.
 With an internal loop counter and loop stack, the
processor executes looped code with zero overhead.
 No explicit jump instructions are required to loop.
ALU block diagram
 The ALU is 16 bits wide with two 16-bit input ports, X and Y and one output port,
R.
 The ALU generates six status signals:
– the zero (AZ) status
– the negative (AN) status
– the carry (AC) status
– the overflow (A V) status
– the X-input sign (AS) status
– and the quotient (AQ) status.
 The X input port of the ALU can accept data from two sources:
– the AX register file or
– the result (R) bus.
 The Y input port of the ALU can also accept data from two sources:
– The AY register file and
– the ALU feedback (AF) register.
 The output of the ALU is loaded into either
–the ALU feedback (AF) register or
–the ALU result (AR) register
 ALU Input/Output Registers

The sources of ALU input and output registers are shown

below.

Source for X input port Source for Destination for

Y input port R output port
AXO,AX1 AYO,AY1 AR
AR AF AF
MRO, MR1, MR2
SRO, SRI

MRO, MR1 and MR2 are multiplier / accumulator result registers; SRO
and SRI are shifter result registers.
Standard Functions
ALU Status
 The ALU status bits in the ASTAT register are
defined below.
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 ALU Instructions
[IF condition] dest = xop + yop ; /* Add */
[IF condition] dest = xop + C ; /* Add with carry*/
[IF condition] dest = xop + yop + C ; /* Add with carry*/
[IF condition] dest = xop - yop ; /* Subtract */
[IF condition] dest = xop - yop + C - 1 ; /* Subtract with borrow*/
[IF condition] dest = yop - xop ; /* Subtract */
[IF condition] dest = yop - xop + C - 1; /* Subtract with borrow*/

[IF condition] dest = xop AND yop;

[IF condition]
[IF condition]
dest = xop OR yop;
dest = xop XOR yop; } Logical
Operations

[IF condition] dest = PASS xop ; /*Pass XOP through ALU, set flags*/
[IF condition] dest = PASS yop ; /*Pass XOP through ALU, set flags*/
[IF condition] dest = PASS 0; /*Pass 0 through ALU, set zeros */
[IF condition] dest = PASS 1; /*Pass 1 through ALU, clear all flags*/

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 ALU Instructions
[IF condition] dest = - xop ;
[IF condition] dest = - yop ;
[IF condition] dest = NOT xop ;
[IF condition] dest = NOT yop ;
[IF condition] dest = ABS xop ;
[IF condition] dest = yop +/- 1 ;

DIVS yop , xop ;

DIVQ xop ;
dest = [AR, AF]
xop = [AR, MR0, MR1, MR2, SR0, SR1, AX0, AX1]
yop = [AY0, AY1, AF]

Examples: AR = AX0 + AY0;

AF = NOT AR;
AF = AX1 + AY0 + C;
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 ALU Instructions
(ADSP-2171, ADSP-218x only)

[IF condition] dest = xop function constant;

[IF condition] dest = PASS constant;

[IF condition] dest = TSTBIT n of xop;

[IF condition] dest = SETBIT n of xop;
[IF condition] dest = CLRBIT n of xop;
[IF condition] dest = TGLBIT n of xop;
condition = arithmetic conditions
dest = [AR, AF]
xop = [AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1]
function = [+, -, AND, OR, XOR, NOT, ABS]
constant = [0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767, -2,
-3, -5, -9, -17, -33, -65, -129, -257, -513, -1025, -2049, -4097, -8193, -16385, -32768]
n = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]

NONE = <ALU>; (ADSP-218x only)

<ALU> = Any “standard” instruction (except DIVS and DIVQ)

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 ALU Status Flags
Flag Name Definition

AZ Zero Logical NOR of all bits in ALU result reg. True if

ALU output equals 0

AN Negative Sign bit of ALU result. True if ALU output

negative

AV Overflow X-OR of carry outputs of 2 most significant

adder stages. True if ALU overflows

AC Carry Carry output from most significant adder stage

AS Sign Sign of ALU X input port. Affected only by ABS

instruction

AQ Quotient Quotient bit generated only by DIVS and DIVQ

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 Arithmetic conditions
Syntax Status condition
EQ: ALU result = 0
NE: ALU Result 0
LT: ALU Result < 0
GE: ALU Result  0
LE: ALU Result  0
GT: ALU Result > 0
AC: ALU Carry Bit Set
NOT AC: ALU Carry Bit Not Set
AV: ALU Overflow Bit Set
NOT AV: ALU Overflow Bit Not Set
MV: MAC Overflow Bit Set
NOT MV: MAC Overflow Bit Not Set
NEG: XOP Input Negative (absolute value instruction only)
POS: XOP Input Positive (absolute value instruction only)
NOT CE: Not Counter Expired

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 ALU Saturation
• Sets ALU result to full scale positive or full scale
negative if overflow or underflow occurs
• Feature enabled by executing ‘ena ar_sat’ (bit 3 of
MSTAT)
• Once enabled, affects every ALU operation
• Only affects results sent to AR (AF - flags still get set)
• Overflow or underflow determined by the following
conditions
Overflow (AV) Carry (AC) AR Contents
0 0 ALU Output
0 1 ALU Output
1 0 0x7FFF full-scale positive
1 1 0x8000 full-scale negative

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 ALU Overflow Latch Mode
• Causes AV status flag to become “sticky”. Need to
explicitly clear.

• Feature enable by executing ‘ena av_latch’ (bit 2 of

MSTAT)

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 ALU Mini-Quiz
Write the ADSP-2100 Family code to perform the
following operations:

1) Add 0x0030 to 0x0070 and store result in AF.

Hint:
= 0x0070 ;
= 0x0030 ;
AF = + ;

2) Find the logical AND of 0x1234 and 0xF00F. Store the

result in AR.
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MULTIPLIER/ACCUMULATOR
(MAC)
MAC
 It provides
– high-speed multiplication,
– multiplication with cumulative addition
– multiplication with cumulative subtraction
– saturation and
– clear-to-zero functions
 A feedback function allows
part of the accumulator output to be directly used as
one of the multiplicands on the next cycle.
ADSP-2100 Family Multiply Accumulator
Instruction
Register

Data Address Data Address

Program
Generator #1 Generator #2
Sequencer

14
PMA Bus

14
DMA Bus

24
PMD Bus

Bus Exchange
16
DMD Bus

Input Registers Input Registers Input Registers

ALU MAC SHIFTER

Output Registers Output Registers Output Registers

16
R Bus

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MAC Block Diagram
 The multiplier has
– two 16-bit input ports X and Y,
– a 32-bit product output port P.
 The 32-bit product is
– passed to a 40-bit adder / subtracter which adds or
subtracts the new product from the content of the
multiplier result (MR) register, or
passes the new product directly to MR.
 The MR register is 40 bits wide.
 MR consists of three smaller registers:
I. MRO (16 bits wide)
II. MR1 (16 bits wide)
III. MR2 (8 bits wide)
 The adder/subtracter is greater than 32 bits to
allow for intermediate overflow in a series of
multiply/accumulate operations.
 The multiply overflow (MV) status bit is set when
the accumulator has overflowed beyond the 32-bit
boundary.
 i. e. when there are significant (non-sign) bits in
the top nine bits of the MR register (based on
twos-complement arithmetic).
 The input/ output registers of the MAC are similar
to the ALD.
Source for X input port Source for Y input port Destination for R
output port
MXO,MXl MYO,MYI MR (MR2, MRl, MRO)
MRO, MRl, MR2 MF MF
SRO, SRI
 The output of the adder / subtracter goes to either
the MF register or the MR register.
 The MF register is a feedback register which
allows bits 16-31 of the result to be used directly
as the multiplier Y input on a subsequent cycle.
MAC Operations
 Standard Functions:
 The functions performed by the MAC are:

X*Y Multiply X and Y operands.

MR+X*Y Multiply X and Y operands and add result
to MR register.
MR-X*Y Multiply X and Y operands and subtract
result from MR register.
0 Clear result (MR) to zero.
 MAC Instruction Examples
MR = MX1 * MY0 (SS); /* Multiply the value in MX1 */
/* and in MY0. Store the result */
/* in the MR register. */
/* (SS) = signed * signed */
MF = AR * MY1 (SS); /* Multiply the value in AR and */
/* MY1. Store the result in the */
/* MF register. */

MR = MR + AR * MY1 (SS); /* Multiply the value in AR and */

/* MY1 and add this result to */
/* the previous value in MR. */
/* Store the final result in MR. */

MR = 0; /* Clear the MR register */

IF MV SAT MR; /* Saturate MR if overflow */

/* flag was set. */

IF EQ MR = MX0 * MY0 (UU); /* Conditional Instruction. If */

/* zero flag set, then perform the */
/* multiply */

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 MAC Instructions
[IF condition] dest = xop * yop (format);
[IF condition] dest = MR + xop * yop (format);
-
[IF condition] dest = 0;
[IF condition] dest = MR [ (RND)];
*[IF condition] dest = xop * xop (format);
*[IF condition] dest = MR +- xop * xop (format);

condition = arithmetic conditions

dest = {MR, MF}
xop = {MX0, MX1, MR2, MR1, MR0, AR, SR0, SR1}
yop = {MY0, MY1, MF}
format = {SS, US, SU, UU, RND}
*ADSP-2171, ADSP-218x, ADSP-21msp5x only

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 Placement of Binary Point in
Multiplication
• Binary Integer Multiplication

M Bits

x P Bits Example: 16.0 x 16.0 => 32.0

M+P Bits

• Mixed/Fractional Multiplication

M.N Bits
Example: 1.15 x 1.15 => 2.30**
x P.Q Bits
4.12 x 1.15 => 5.27

(M+P).(N+Q) Bits

** In fractional mode the result of a multiplication will be automatically left shifted by 1 bit resulting in a 1.31 format

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 Placement of Binary Point in MR
Sign Bit
MR2 MR1 MR0

S . Fractional
Mode

OVERFLOW Most Significant Least Significant

16 Bits 16 Bits
Sign Bit
MR2 MR1 MR0
Integer
S . Mode

OVERFLOW Most Significant Least Significant

16 Bits 16 Bits

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Multiplication Modes --Fractional Mode

 In the fractional mode, the 32-bit P output is

format adjusted.
 i.e. sign extended and shifted one bit to the left
before being added to MR.
Multiplication Modes -- Fractional Mode
Mode 1: Fractional Mode
• Multiplier assumes all numbers in a 1.15 format
• Multiplier automatically shifts product 1-bit left before accumulation
(result forced to 1.31 format)
• Example: MR = MX0 * MY1 (SS);

MX0 MY1

0x4000 =0.5 0x4000 =0.5

MR2 MR1 MR0

0x00 2000 0000 =0.25

MR1

overflow 0x2000 underflow

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Multiplication Modes --Integer Mode
 In the integer mode, the 32-bit P register is not
shifted before being added to MR.
 Multiplication Modes -- Integer Mode
Mode 2: Integer Mode
• Multiplier assumes all numbers in a 16.0 format
• No automatic left-shift necessary
• Example: MR = MX0 * MY1 (SS);

MX0 MY1
14 14
0x4000 =2 0x4000 =2

MR2 MR1 MR0

28
0x00 1000 0000 =2
MR0

overflow overflow 0x0000

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Input Formats
The multiplier accepts X and Y inputs represented in any
combination of signed twos-complement format and unsigned
format.
 Multiplication on ADSP-2100 Family
Devices
To Switch Modes: ENA M_MODE; {Select Integer Mode} *
DIS M_MODE; {Select Fractional Mode}

MSTAT Register holds value

Fractional Mode the Default on Reset/Power-up

* Integer Mode Not Available on ADSP-2100A

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 Rounding in the MAC
• Rounding can be specified as part of multiply instruction (RND)
• Rounding only applies to fixed-point signed fractional results
• 40-bit results "rounded to nearest" 16 bit value.
• Rounded result can be placed in MR1 or MF register
Input: MX0 = 0x7FF9, MY0 = 0xEEEE
Command MR2 MR1 MR0
MR = MX0 * MY0 (SS); FF EEEE EEFC
MR = MX0 * MY0 (RND); FF EEEF 6EFC
• ADSP-217x / 218x / msp5x Support a “Biased” Rounding
– When MR0 = 0x8000, will always round up
– Enabled by setting BIASRND bit (bit12 of dm(0x3FF3))
– Useful for GSM speech coding where biased rounding is specified

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 Rounding in the MAC (contd…)

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 MAC Overflow And Saturation

 The adder/subtracter generates an overflow status

signal (MV) which is loaded into the processor
arithmetic status (ASTAT) every time a MAC operation
is executed.
 The MV bit is set when the accumulator result,
interpreted as a twos-complement number, crosses
the 32-bit (MR1/MR2) boundary.
 That is, MV is set if the upper nine bits of MR are not
all ones or all zeros.
 The MR register has a saturation capability which sets
MR to the maximum positive or negative value if an
overflow or underflow has occurred.

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 MV MSB of MR contents after saturation
MR2
0 0 or 1 No change
1 0 00000000 0111111111111111 1111111111111111 (full-scale
positive)
1 1 11111111 1000000000000000 0000000000000000 (full-scale
negative)

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 Saturation and Overflow
• Overflow occurs when sign bit is corrupted during accumulation
• Overflow Status (MV) is updated everytime a MAC operation is
executed
• MV is set when any bits of significance cross into MR2
– This occurs when the bits in MR2 do not equal the MSB of MR1
• Saturation is performed by following instruction:
– IF MV SAT MR
Input: MX0 = 0x7FFF, MY0 = 0x7FFF, MR = 00 7FFE 0002
Command MR2 MR1 MR0
MR = MR + MX0 * MY0 (SS); 00 FFFC 0004
IF MV SAT MR; 00 7FFF FFFF

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 MAC Mini-Quiz
Write the ADSP-2100 Family program to add the values in
AX0 and AY0 and then multiply the result by 0x0020.

AX0 = 0x0020;
AY0 = 0x0010;
AR = _______________
___ = _______________
____=_______ * _________

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 Binary Multiply Mini-Quiz

What is the ADSP-2100 Family MAC

output?
(Hint: The output is 32 bits wide)

Fractional Mode Integer Mode

0x1240 * 0x0001

0x4000 * 0x4000

0x4000 * 0x0002

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Shifter
 ADSP-2100 Family Shifter
Instruction
Register

Data Address Data Address

Program
Generator #1 Generator #2
Sequencer

14
PMA Bus

14
DMA Bus

24
PMD Bus

Bus Exchange
16
DMD Bus

Input Registers Input Registers Input Registers

ALU MAC SHIFTER

Output Registers Output Registers Output Registers

16
R Bus

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 Shifter Block Diagram
DMD BUS 16

SI
REGISTER

BLOCK
EXPONENT MUX
LOGIC
EXPONENT
DETECTOR 16
I
SHIFTER
ARRAY
C
8 32 O
MUX MUX
32
OR / PASS
SE
REGISTER 16
NEGATE 16
8 MUX MUX
From
Instruction
SR1 SR0
REGISTER REGISTER

16 MUX
16

R - BUS 16

a 4 - 54
 The shifter can be divided into the following
components:
– the shifter array
– the OR/PASS logic
– The exponent detector, and
– the exponent compare logic.
 The shifter array is a 16x32 barrel shifter.
 It accepts a 16-bit input and can place it anywhere
in the 32-bit output field, from off-scale right to off-
scale left, in a single cycle.
 The placement of the 16 input bits is determined
by a control code (C) and a HI/LO reference signal.
 The shifter array and its associated logic are
surrounded by a set of registers.
 The shifter input (SI) register provides input to the
shifter array and the exponent detector.
 The SI register is 16 bits wide and is readable and
writable from the DMD bus.
 Also take as inputs AR, SR or MR via the R bus
 The shifter result (SR) register is 32 bits wide and
is divided into two 16-bit sections, SRO and SRI
 The SR register is also fed back to the OR/PASS
logic to allow double-precision shift operations.
 The SE register (shifter exponent") is 8 bits wide
and holds the exponent
 during the normalize and denormalize operations.
 Shifter Features
• 16 Bit Input Value gets shifted and stored anywhere in
a 32 Bit output field

• All Shift Instructions execute in a single instruction

cycle

• Shift value can be specified immediately within the

instruction or indirectly using the SE register

• Normalize, Denormalize, and Exponent Detect

Instructions Used For Block Floating Point and
Floating Point Operations

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 Shifter Instruction Examples
SR = ASHIFT SI BY -3 (LO); /* Perform an ARITHMETIC */
/* shift of the value in SI by */
/* three places to the right. */

SR = LSHIFT AR BY 6 (HI); /* Perform a LOGICAL shift of */

/* the value in AR by the value */
/* specified in the SE register. */

SE=5;
SR = LSHIFT SI (HI); /* Perform a logical shift of the value */
/* in SI by the value specified in the */
/* SE register. */

SR = SR OR LSHIFT SR1 (LO); /*Perform a LOGICAL shift of

/* the value in SRI, OR this
/* with the value in SR and
/* store the result in SR.

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a 4 - 60
 Shift Immediate Instructions

SR = [SR OR] ASHIFT xop BY <data> (alignment);

SR = [SR OR] LSHIFT xop BY <data> (alignment);

xop = [SI, SR0, SR1, MR2, MR1, MR0, AR]

<data> = [-32 ... 32]
alignment = [HI, LO]

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 Shift By Value in SE Register
Instructions

[IF condition] SR = [SR OR] ASHIFT xop (alignment);

[IF condition] SR = [SR OR] LSHIFT xop (alignment);

condition = Arithmetic condition

xop = [SI, SR0, SR1, MR2, MR1, MR0, AR]
alignment = [HI, LO]

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 Shifter Instructions
• Arithmetic Shift Sign Extends Right Shifts
• Logical Shift Zero fills Right Shifts
• Left Shifts Are Always Zero Filled
• Positive SE or <data> Values Shift Left
• Negative SE or <data> Values Shift Right
• NO "+" for Positive Shifts
• Placement of Output Depends on HI/LO Modifier,
SE Register and <data> Value

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 Immediate Shift Instructions
• Example 1: SR = LSHIFT SI BY -1210 (LO);

SI 1110 1010 0011 0101

SE xxxx xxxx

Before: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

SR1 SR0

SI 1110 1010 0011 0101

SE xxxx xxxx

After:
0000 0000 0000 0000 0000 0000 0000 1110
SR1 SR0

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 Immediate Shift Instructions
• Example 2: SR = LSHIFT SI BY -1210 (HI);

SI 1110 1010 0011 0101

SE xxxx xxxx

Before: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

SR1 SR0

SI 1110 1010 0011 0101

SE xxxx xxxx

After:
0000 0000 0000 1110 1010 0011 0101 0000
SR1 SR0

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 Shift Instructions with SE Register
• Example 3: SE = -12;
SR = LSHIFT SI (HI);

SI 1110 1010 0011 0101

SE 1111 0100 (-12)

Before: xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

SR1 SR0

SI 1110 1010 0011 0101

SE 1111 0100 (-12)

After: 0000 0000 0000 1110 1010 0011 0101 0000

SR1 SR0

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Shift Instructions with OR Functionality
• Example 4: SE = -12;
SR = SR OR LSHIFT SI (HI);
SI 1110 1010 0011 0101

SE 1111 0100 (-12)

Before: 0000 0000 0000 0000 0000 0000 0000 0101

SR1 SR0

SI 1110 1010 0011 0101

SE 1111 0100 (-12)

After: 0000 0000 0000 1110 1010 0011 0101 0101

SR1 SR0

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 Shifter Mini-Quiz
Write the ADSP-2100 Family Assembly program to:

• Write 0x0034 into the AR register

• Write 0x0012 into the SI register
• Shift AR into the MS bits of SR0 (SR0 = 0x3400)
• Shift SI into the LS bits of SR0

Hint: You should be able to do this in 4 Instructions

When you are finished, SR1 = 0x0000, SR0 = 0x3412

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