Cache Memory

Sheet and model answer

Given the 16-bit memory address references below, as BYTE addresses in hex format:

0020, 0022, 00C8, 00C9, 0032, 0023, 004A, 0062, 0020, 0021

a) For each of these references, identify the binary address.

b) Given a cache with a total of 16 words organized as 1 word/block, identify the tag, and the index
for each reference using direct mapping. List if each reference is a hit or miss. How many bits in
total does the cache has?

c) Repeat (b), but with 2 words/block for a cache with a total of 16 words.

d) Repeat (b) for a two-way set associative cache with 2 words/block, and a total size of 16 words.

e) Repeat (b) for a fully associative cache with 1 word/block, and a total size of 16 words.

f) Assume the given memory references are called in a loop of 100 times. Recalculate the number
of hits and misses for all cases: (b), (c), (d) and (e).

For set associative and fully associative caches, use Least Recently Used (LRU) replacement.

Solution:

a) For each of these references, identify the binary address

0020 0000000000100000 0023 0000000000100011

0022 0000000000100010 004A 0000000001001010
00C8 0000000011001000 0062 0000000001100010
00C9 0000000011001001 0020 0000000000100000
0032 0000000000110010 0021 0000000000100001

b) Given a cache with a total of 16 words organized as 1 word/block, identify the tag, and the index
for each reference using direct mapping. List if each reference is a hit or miss

Byte Word Tag index hit/ Replacing

address
0020 address
0008 00…0000 1000 Miss WORD
none address
(10 bits) (4 bits) miss
0022 0008 00…0000 1000 Hit none
00C8 0032 00…0011 0010 miss none
00C9 0032 00…0011 0010 Hit none
 0032 000C 00…0000 1100 miss none
0023 0008 00…0000 1000 Hit none 6 misses, 4 hits
004A 0012 00…0001 0010 miss 0032 , and show the final
0062 0018 00…0001 1000 miss 0008 cache content.
0020 0008 00…0000 1000 miss 0018
0021 0008 00…0000 1000 hit none
Index Valid Tag Contents
0000 bit
0 (10 bits) M(WORD Address)
0001 0
0010 1 00…0001 M(0012)
0011 0
0100 0
0101 0
0110 0
0111 0
1000 1 00…0000 M(0008)
1001 0
1010 0
1011 0
1100 1 00…0000 M(000C)
1101 0
1110 0
1111 0

How many bits in total does the cache has?

Total bits in the Cache = 16 *(1 + 10+ 32) = 16 * 43 = 688 bits

c) Repeat (b), but with 2 words/block for a cache with a total of 16 words.

Byte Word Tag index word/ hit/ Accompanying Replacing word

address
0020 address
0008 00…0000 100 0 Miss word
0009 address address
none
(10 bits) (3 bits) block miss
0022 0008 00…0000 100 0 Hit none
00C8 0032 00…0011 001 0 miss 0033 none
00C9 0032 00…0011 001 0 Hit none
0032 000C 00…0000 110 0 miss 000D none
0023 0008 00…0000 100 0 Hit none
004A 0012 00…0001 001 0 miss 0013 0032, 0033
 0062 0018 00…0001 100 0 miss 0019 0008, 0009
0020 0008 00…0000 100 0 miss 0009 0018, 0019
0021 0008 00…0000 100 0 hit none
6 misses, 4 hits

, and show the final cache content.

Index Valid Tag Contents Contents

000 bit
0 (10 bits) WORD (1) WORD (0)
001 1 00…0001 M(0013) M(0012)
010 0
011 0
100 1 00…0000 M(0009) M(0008)
101 0
110 1 00…0000 M(000D) M(000C)
111 0

Total bits in the Cache = 8 *(1 + 10+ 32*2) = 8*75 = 600 bits

d) Repeat (b) for a two-way set associative cache with 2 words/block, and a total size of 16 words

Byte Word Tag index word/ Way hit/ Accompanying Replacing

address address word address word address
(11 bits) (2 bits) set(block) miss
0020 0008 00…00001 00 0 0 Miss none
0022 0008 00…00001 00 0 0 Hit none
00C8 0032 00…00110 01 0 0 miss none
00C9 0032 00…00110 01 0 0 Hit none
0032 000C 00…00001 10 0 0 miss none
0023 0008 00…00001 00 0 0 Hit
004A 0012 00…00010 01 0 1 miss none none
0062 0018 00…00011 00 0 1 miss none
0020 0008 00…00001 00 0 0 hit none
0021 0008 00…00001 00 0 0 hit none
5 misses, 5 hits

The final cache content.

Index Valid Tag Contents Contents

bit
(11 bits) WORD (1) WORD (0)
 Way 0
00 1 00…00001 M(0009) M(0008)
01 1 00…00001 M(0033) M(0032)
10 1 00…00001 M(000D) M(000C)
11 0
Way 1
00 1 00…00011 M(0019) M(0018)
01 1 00…00010 M(0013) M(0012)
10 0
11 0

Total bits in the Cache = 8 *(1 + 11+ 32*2) = 8*76 = 608 bits

e) Repeat (b) for a fully associative cache with 1 word/block, and a total size of 16 words.

No index. A word is written into the first available space in the cache.

Tag hit/miss Tag hit/miss

0020 00000000001000 miss 0023 00000000001000 hit
(14 bits) (14 bits)
0022 00000000001000 hit 004A 00000000010010 miss
00C8 00000000110010 miss 0062 00000000011000 miss
00C9 00000000110010 hit 0020 00000000001000 hit
0032 00000000001100 miss 0021 00000000001000 hit
5 misses, 5 hits

, and show the final cache content.

Valid Tag Contents

1
bit 00000000001000 M(0008)
(14 bits) M(WORD Address)
1 00000000110010 M(0032)
1 00000000001100 M(000C)
1 00000000010010 M(0012)
1 00000000011000 M(0018)
0
0
0
0
0
0
0
0
0
0
 0

Total bits in the Cache = 16 *(1 + 14+ 32) = 16*47 = 752 bits

f) Assume the given memory references are called in a loop of 100 times. Recalculate the number
of hits and misses for all cases: (b), (c), (d) and (e).

Misses Hits
For case b: 6+99*4= 402 4+99*6=598
For case c: 6+99*6= 402 4+99*4=598
For case d: 5+99*0= 5 5+99*10=995
For case e: 5+99*0= 5 5+99*10=995