A Modular Multilevel DC-DC Converter with Self
Voltage Balancing and Soft Switching
Changjiang Sun, Xu Cai, Jianwen Zhang, and Gang Shi
Wind Power Research Centre, Shanghai Jiao Tong University, Shanghai, China
Abstract—Evolving from the popular modular multilevel
ac-dc converter, modular multilevel dc-dc converter (MMDC)
is attractive for medium-and high-voltage applications.
However, exploiting ac circulating power to balance the
submodule energy, the existing MMDC topologies inevitably
suffer from high circulating current through the arms, large
filter inductor at the low voltage side and complex submodule
voltage balancing algorithms. For overcoming these issues, this
paper presents a new power transfer mechanism to balance the
submodule energy automatically by reconstructing the half-
bridge submodule into a circuit quasi-resonant. Based on this
submodule structure, a novel MMDC topology for step-up
applications is proposed. Compared with the prior-art MMDC,
this topology offers the following merits: 1) common-mode
circulating current through the lower and upper arms is
avoided. 2) self-balancing of the capacitor voltages is ensured
by the proposed modulation method to insert and bypass the
adjacent submodules in a complementary manner. 3) soft-
switching operation is achieved for the majority of switches to
alleviate the switching losses and electromagnetic interference.
4) voltage stress across the low-voltage side inductor is limited
to the submodule voltage, thus reducing the size of the inductor
significantly. Experimental results verify the performance of
proposed MMDC.
Keywords—modular multilevel dc-dc converter, quasi-
resonant submodule, voltage self-balancing, soft Switching
I. INTRODUCTION
High-voltage direct current (HVDC) technology is a
promising solution for delivering large-scale renewable
energy with a long transmission distance because of the
reduced power losses and low reactive power requirements
[1]. Extending dc scheme to the renewable energy collection
grids thereby to form an all-dc power system can further
spare extra conversion stages, reduce costs, and improve
system reliability [2].
High-power dc-dc converters are critical components in
the dc power system to match different voltage levels and
control power flow [3]. Taking dc collection grid of the
offshore wind farm as an example, high-power and high
step-up ratio dc-dc converters are essential in the wind
energy conversion system (WECS) for connecting wind
turbines with the medium-voltage dc bus [4]. The
conventional low voltage two-level dc-dc converter
topologies (e.g., buck circuit) cannot be directly scaled up
for the said grid-scale applications because the series
connection of IGBTs inevitably leads to the voltage sharing
and EMI issues [5].
The emerging Modular multilevel converter (MMC) is
an attractive topology for medium-and high-voltage ac-dc
conversion applications because of its modularity and high
reliability [6]. Connecting ac terminals of two MMCs via a
transformer for realizing dc-ac-dc conversion, Reference [7]
propose the isolated modular multilevel dc-dc converter
topology (IMMDC). Improved operating methods and high-
efficiency control strategies of the IMMDC have been
developed in [8-11]. Although IMMDC reaps benefits from
the MMC topology, two ac-dc conversion stages in IMMDC
This work was supported by National Natural Science Foundation of China
(51677117) and Shanghai Science and Technology Committee Fund
(16DZ1203402).
978-1-5386-6054-6/18/$31.00 ©2018 IEEE
leads to high losses. Moreover, cost and footprint of the
coupled transformer rated for the full transferred power are
considerable.
By operating the upper and lower arm of an MMC phase
leg asymmetrically to generate voltage with dc bias at the
midpoint, the single-stage modular multilevel dc-dc
converter (MMDC) is proposed in [12, 13]. The most
critical issue for MMDC is energy balance of the submodule
capacitors since its upper and lower arms absorb different
amount of power from the dc stage. A balance power
transfer loop should, therefore, be built up between the arms
for ensuring the stability of the submodule voltages. Based
on the orthogonality of power flow at different frequencies,
the transfer of balance power in [12, 13] is realized by
injecting common-mode ac current through the arms.
Exploiting this mechanism to balance submodule energy,
many variant versions of MMDC have been developed in
the literature [14]. However, this principle of balance power
transfer suffers from drawbacks especially when the MMDC
is employed for high step-ratio application scenarios. Firstly,
the injected circulating current and reactive power through
the arms is considerable [15], which increases both
conducting and switching losses of the hard-switched
devices. Meanwhile, bidirectional switches are needed in the
submodules to provide circulating path for the alternating
current even for un-directional applications, reducing the
device utilization ratio. Secondly, large filter inductors are
required to prevent the injected ac voltages and currents
from propagating to the dc sides. Moreover, submodule
voltage and arm current sampling circuits along with the
voltage balancing algorithms render the control system
rather complex.
This paper presents a new power transfer mechanism to
balance the submodule energy automatically by
reconstructing the half-bridge submodule (HBSM) into a
circuit quasi-resonant submodule (QRSM). Based on this
submodule structure, a novel step-up MMDC topology for
WECS application to connect wind turbines with the
medium-voltage grid is proposed. In the new submodule
circuit, a subcircuit consisting of a diode in series with a
small resonant inductor, which can be realized by the stray
inductance, is added to link positive poles of the adjacent
submodule capacitors. This subcircuit provides the balance
power transfer loops between the submodules in the form of
half-wave sinusoid current without reactive component,
avoiding the common-mode ac current through the arms.
Some bidirectional switches in the original half-bridge
submodule can, therefore, be replaced by single-quadrant
switches when the converter is employed for unidirectional
applications, leading to fewer switch devices than
conventional MMDC. The resonance operation facilitates
zero-current-switching (ZCS), and zero-voltage-switching
(ZVS) features for the majority switches. Distinct from the
modulation schemes of MMC where the lower and upper
arms are modulated in a complementary manner, this paper
presents a novel modulation scheme for the new MMDC to
insert and bypass every two adjacent submodules in a
complementary manner. By utilizing this modulation
method, balance power is transferred in arms automatically,
and self-balancing of the submodule voltages is achieved. Cn+1
Since the amplitude of the square-wave voltage applied on D3
the low-voltage side inductor is limited to the submodule
voltage level in this modulation method, a small inductor is
sufficient to suppress the current ripples at the input stage. T2 Lr
SMn

II. PROPOSED MMDC TOPOLOGY T2 T2

T1 D1
For achieving the automatic power transfer between D2 D2
submodules, the conventional half-bridge submodule T1
D1 T1 D1
(HBSM) circuit is reconstructed into a quasi-resonant Cn+1 Cn
submodule (QRSM) circuit in this paper.
Fig. 1(a) depicts derivation process of the QRSM D3
Cn+1 Upper arm SM
circuit. Firstly, a subcircuit consisting of a diode in series
SMn
with a small resonant inductor Lr (which can be realized by T2 T2 Lr
the stray inductance or an auxiliary air-core inductor if D2 D2
Cn+1
necessary) is added to link positive poles of the adjacent
D3
capacitors. In the obtained QRSM SMn as shown in Fig. 1 T1 D1 T1 D1
(a), Cn, Cn+1, and Lr forms a resonant loop when T1 and D3 SMn
are conducting. Cn can release charge to Cn+1 in this circuit, Lr
realizing the upward power transfer in the cascaded Cn Cn D2
submodules. Since the common-mode alternating current T1
through the lower and upper arms no longer exists in the
proposed MMDC, bidirectional switches are not needed Half-Bridge SM Quasi-Resonant SM
when the converter is utilized for step-up application in SMn
Cn
WECS. Therefore, some switching devices from the original
HBSM can be omitted, obtaining the upper arm and lower Lower arm SM
arm QRSMs as shown in Fig.1 (a).
(a) Derivation of QRSM.
Fig. 1(b) shows topology of the proposed step-up
MMDC with the QRSMs cascaded in a string to withstand Ls idc2
the dc voltage. The string is composed of lower and upper CM+N+1
arms where different QRSM circuits are employed in
accordance with Fig 1.(a). A filtering inductor Lf is installed
at the low-voltage side to attenuate current ripples. A small SMN+M
choke is necessary at the high-voltage side to accommodate
CM+N
the switching action as well as voltage variation of the
capacitors. Though one-string architecture of MMDC is
drawn here, a multiphase topology can be easily formed by upper arm
connecting more strings in parallel to increase the power vU
capacity.
III. OPERATING PRINCIPLE
The proposed balance power transfer mechanism along SMN+1
with the operating principles of the QRSM-based MMDC is
illustrated in this suction. For simplification purpose, the
theoretical developments are based the following Vdc2
assumptions: 1) the converter is losses, 2) the QRSMs are idc1 Lf
identical, 3) the capacitor voltages are well balanced in SMN
steady state, 4) the capacitor voltage ripples are negligible
compared with the average capacitor voltage.
CN
A. Basic Operating Principle and Modulation Strategy
As the QRSM circuit shown in Fig.1 (a), the capacitor lower arm
in SMn is inserted in the power circuit when T2 or D2 is Vdc1
conducting and bypassed when T2 or D2 is conducting. The
instantaneous voltages of the lower and upper arms can be vL
actively controlled by adjusting the number of capacitors
that are inserted. Fig. 2 shows the equivalent model of SM1
MMDC with the arms represented by two controllable
voltage sources vL and vU, respectively.
C1
According to Kirchhoff’s voltage and current Laws, we
have
(b) Schematic of the converter.
Fig. 1 Topology of proposed converter
 According to (3), and current waveform in Fig 3,
Vdc1  vL  Lf  didc1 dt adjusting d can realize the dynamic control of the low-side

Vdc2  vL  vU  Ls  didc2 dt (1) voltage or current. Besides, the amplitude of the square-
i  i  i wave voltage applied across the input filter inductor (i.e., Lf)
 dc1 dc2 L is limited to the submodule capacitor voltage, which reduces
Based on the volt-second balance principle of the inductor, the filter inductance dramatically when compared with the
the input voltage Vdc1 is equal to the average of vL (i.e., VL), conventional operating of MMDC.
and the output voltage is equal to the average of vL+vU (i.e., (1-d)Ts dTs
VL+VU).
Seven t
idc2 Ls
1
Sodd 0 t

+
vU Vc
vU
-
vL Vc

idc1 Lf idc2 (N+1)Vc/2 Vdc1

Pbalance Vdc2 (N-1)Vc/2

iL t
0
+ ΔIdc1
Vdc1 vL idc1
t
- 0
Fig. 3. Modulating adjacent submodules of the proposed MMDC in a
complementary manner.
Fig. 2. Equivalent model of MMDC.
Neglecting power losses in MMDC, the input power is
For maintaining the high-side dc voltage, the existing equal to the output power, i.e.,
MMDCs are usually modulated in a complementary manner,
i.e., inserting (bypassing) a submodule in the lower arm if a P  Vdc1 I dc1  Vdc2 I dc2 (4)
submodule is to be bypassed (inserted) in the upper arm. Idc1 and Idc2 represent the average value of idc1 and idc2
Distinct from this, the adjacent submodules are modulated over one switching cycle, respectively. According to (1), (2),
in a complementary manner in the proposed MMDC, i.e., and (3), Idc1=IL+Idc2, Vdc1=VL, and Vdc2=VL+VU. Substituting
the switching signals of the even-numbered QRSMs and the them into (4) leads to
odd-numbered QRSMs are complementary. Fig. 3 shows the VL I L  VU I dc2 (5)
switching signals and key waveforms of the proposed
MMDC under this modulation manner. With 1 and 0 The left-hand side of (5) represents the absorbed dc power
indicating inserting and bypassing states, Seven and Sodd are of the lower arm while the right-hand side expresses the
switching signals for the even-numbered QRSMs and the released power of the upper arm. Eq.(5) reveals that an
odd-numbered QRSMs respectively. Vc represents the additional power transfer loop should be established
average capacitor voltage. M and N are the number of between the arms to maintain the stability of energy stored
submodules in the upper and lower arms. With the varying in the arms. For step-up MMDC with power flowing from
of switching signals, the inserted voltage in the lower arm the low-voltage side to the high-voltage side, the amount of
(i.e., vL) switches between (N-1)Vc/2 and (N+1)Vc/2, and the balance power that needs to be transferred from lower arm
inserted voltage in the upper arm (i.e., vU) switches between to upper arm is
(M+3)Vc/2 and (M+1)Vc/2. Pblance  VU I dc2  (1  1 k ) P (6)
In Fig. 3, vL and vU are square-wave voltages with dc
bias, and their ac components are complementary. Therefore, in which k is the step-up ratio of the converter.
the high-side dc voltage can be obtained as
( N  M  2)Vc B. Power Transfer and Capacitor Voltage Balancing Process
Vdc2  vL  vU  (2) The previous analysis reveals that an additional power
2 transfer loop from bottom to the top of the submodule string
Eq.(2) reveals that the total number of inserted submodules should be established to maintain voltage stability of the
is maintained, which ensures the stability of Vdc2. Therefore, capacitors. The QRSM topology together with the proposed
a quite small high-side inductor (i.e., Ls) is sufficient to limit modulation strategy in this paper achieves the automatic
current ripples caused by the switching actions and the power transfer between the adjacent submodule, realizing
variation of capacitor voltages. self-balancing of the capacitor voltages.
The low-side voltage Vdc1 is equal to the average of vL Taking the typical submodule SMn in the upper arm as
over one switching cycle. With d representing duty ratio of an example, this section illustrates the power transfer
switching signals for odd-numbered submodules, we have process between the submodules and self-balancing
mechanism of the capacitor voltages. Fig. 4 shows switching
( N  1)Vc
Vdc1  VL   dVc (3) states of the submodules SMn and SMn-1, and Fig. 5 shows
2 the corresponding switching signals and voltage and current
waveforms. To insert and bypass the adjacent submodules in (1-d)Ts dTs
a complementary manner, switches T1,n-1, and T2,n have
ST1,n-1
identical switching signals. Switching signals of T1,n, and ST2,n t
T2,n-1 are complementary with that of T2,n, and T1,n-1
respectively if neglecting the deadtime interval.
1
ST1,n
Cn+1 Cn+1 Cn+1
ST2,n-1 0 t
D3,n D3,n D3,n
idc2 idc2 idc2

T2,n T2,n T2,n vc,n-1 Vc_max,n Vc_max,n+1

Lr Lr Lr
vc,n+1
T1,n D1,n T1,n D1,n T1,n D1,n vc,n
SMn
Vc_min,n Vc_min,n+1
SMn Cn SMn Cn Cn
D3,n-1 D3,n-1 D3,n-1 0 t
iD3,n-1 iD3,n-1
T2,n-1 T2,n-1 T2,n-1
Lr Lr Lr
ID3,n-1 iD3,n-1
0 t
T1,n-1 D1,n-1 T1,n-1 D1,n-1 T1,n-1 D1,n-1
SMn-1 SMn-1 SMn-1
iT2,n-1 t
Cn-1 Cn-1 Cn-1 0
idc2 idc2 idc2
(a) State 1, 3 (b) State 2 (c) State 4 iT1,n-1
iD1,n-1
Cn+1 Cn+1 Cn+1 0 t
D3,n D3,n D3,n
idc2 idc2 idc2
iD3,n iD3,n
ID3,n iD3,n
T2,n T2,n T2,n
Lr Lr Lr
0 t
T1,n T1,n T1,n D1,n iT2,n
D1,n D1,n
SMn SMn SMn t
0
D3,n-1 D3,n-1 D3,n-1
Cn Cn Cn
iT1,n
T2,n-1 T2,n-1 T2,n-1 iD1,n
Lr Lr Lr
0 t
t0 t1 t2 t3 t4 t5 t6 t7 t8
T1,n-1 D1,n-1 T1,n-1 D1,n-1 T1,n-1 D1,n-1
Fig. 5. Key waveforms of SMn and SMn-1.
SMn-1 SMn-1 SMn-1
3) State 3 [t2,t3], Fig.4 (a): With the resonant current
Cn-1 Cn-1 Cn-1
iD3,n-1 dropping lower than the dc current idc2 at t2, T1,n-1 is
idc2 idc2 idc2 turned off naturally at zero current, and D1,n-1 begins to
(d) State 5, 7 (e) State 6 (f) State 8
conduct current again. The conduction states of the switches
return to Fig.4 (a).
Fig. 4. Operation states of SMn and SMn-1.
4) State 4 [t3,t4], Fig.4 (c): After Cn-1, Cn, and Lr
Operation states of SMn and SMn-1 in one switching resonate for half of the resonant cycle, the resonant current
period are illustrated as follows. iD3,n-1 falls back to zero and vc arrives at its maximum value
1) State 1 [t0,t1], Fig.4 (a): With T2,n turned on and T2,n-1 at t3. D3,n-1 is reversely biased since vc,n is higher than vc,n-1
turned off at t0, the dc current idc2 commutates from T2,n-1 to thereafter. Zero-current turn-off of D3,n-1 is achieved during
D1,n-1. D3,n-1 is forward biased since the voltage of Cn-1 (i.e., this procedure, avoiding the reverse recovery losses of the
vc,n-1) is larger than the voltage of Cn (i.e., vc,n). Cn-1, Cn, and diode.
Lr form a resonant tank with the resonant current iD3,n-1 5) State 5-8 [t4,t8], Fig.4 (d)-(f): For the subsequent half
gradually increasing from zero in a sinusoidal manner. of switching cycle, Cn, Cn+1, and Lr forms a resonant tank
Meanwhile, vc,n-1 begins to decrease from its maximum with T2,n-1 turned on and T2,n turned off at t4. Similar to the
value. Before iD3,n-1 goes higher than idc2, D1,n-1 keeps charge transfer process from Cn-1 to Cn during operation
conducting and the voltage across T1,n-1 is zero. Therefore, states 1-4, Cn releases charge to Cn+1 during operation states
zero-voltage turn-on of T1,n-1 can be achieved when it is 5-8. Similar to the soft-switching property of T1,n-1 and D1,n-1,
turned on a small dead-time delay after the turning off of zero-voltage turn-on and zero-current turn-off are achieved
T2,n-1. for T1,n, and zero-current turn-off is achieved for D1,n.
2) State 2 [t1,t2], Fig.4 (b): T1,n-1 begins to conduct Charging and discharging processes of capacitors in the
current at zero voltage when the resonant current iD3,n-1 typical QRSM are summarized as follows. During interval
becomes larger than idc2 at t1. iD3,n-1 keeps increasing and (t0,t3), SMn is inserted with the dc current flowing through
arrive at the peak value with vc,n equals to vc,n-1. Thereafter, its capacitor Cn. Meanwhile, SMn absorbs charge from the
vc,n-1<vc,n and iD3,n-1 begins to decrease. subjacent submodule SMn-1 via the resonant tank composed
of Cn-1, Cn, and Lr. During interval (t3,t4), with the resonant
current staying as zero the dc current itself discharges SMn.
During interval (t4,t7), SMn is bypassed. Meanwhile, SMn
releases charge to the upper submodule SMn+1 via the
resonant tank composed of Cn, Cn+1, and Lr. During interval
(t7,t8), with the resonant falling back to zero the capacitor
voltage of SMn remains constant.
According to the conservation of charge, the total charge
that SMn absorbs from SMn-1 is equal to that it releases to
SMn+1 plus the loss of charge caused by the dc current.
Energy variation of the capacitor in one switching cycle is
zero, ensuring the natural stability of the submodule
capacitor voltage.
By extending the above power transfer principle to an
arbitrary QRSM, the general conclusions can be drawn, i.e.,
the submodule absorbs power from the subjacent submodule
when it is inserted, and releases power to the upper (a) Submodule capacitor voltages.
submodule when it is bypassed both via the resonant tank.
By inserting and bypassing the adjacent submodules
alternatively, the balance power can be transferred from
bottom to the top of the submodule string. Charge transfer
between the top submodule of the lower arm (i.e., SMN in
Fig. 1) and the bottom submodule of the upper arm (i.e.,
SMN+1 in Fig. 1) realizes power transfer between the arms.
For maintaining stable operation, Pbalance calculated by (6)
should be transferred from SMN to SMN+1 via the resonant
tank consisting of CN, CN+1, and Lr.
IV. EXPERIMENTAL VERIFICATION
A scaled-down prototype of the QRSM-based MMDC
rated at 1kW has been built and tested. The input and output
voltages are 50V and 300V, respectively. There are 4
(b) Resonant currents.
QRSMs in the string with 1 in the lower arm and 3 in the
upper arm. The average capacitor voltage is 100V. The
switching frequency is 2 kHz. In the experiment, a dc power
supply, and an inverter both controlled to maintain their dc
voltages are employed to provide and absorb the transferred
power, respectively. The MMDC is controlled to maintain
the input current via a PI controller.
With the transferred power of the converter maintained
as 1kW via controlling the input current, Figs. 6 (a), (b), (c),
and (d) show the measured capacitor voltages, resonant
currents, voltage and current waveforms at the dc stage, and
waveforms of switches in the typical submodule of the
upper arm respectively.
In Fig. 6 (a), the capacitor voltages are self-balanced
without any control. Fig.6 (c) shows that by employing the
proposed modulation method, the generated voltage at the
output stage (i.e., vL+vU) is stable with acceptable ripples (c) Voltage and current waveforms at the dc stage.
small voltage sparks caused by switching actions. Besides,
the amplitude of square-wave lower-arm voltage vL is
limited to the submodule voltage level to reduce the size of
the input filter inductance. Fig 6 (d) shows that soft
switching is realized for the majority switches. T1 is turned
on after its voltage drops to zero with D1 conducting current.
T1 and D3 are naturally turned off with their currents fall
back to zero. These experimental results are in agreement
with the theoretical analysis results.
Fig. 7 shows dynamic responses of the capacitor
voltages as the transferred power steps from 500W to 1kW
by adjusting the input current command from 20A to 30A,
including the waveforms of input and output currents and
two typical submodule voltages. It can be seen that the input
current is controlled well to track the reference signal in less
than 20ms. Besides, the capacitor voltages are well balanced (d) Switching waveforms in the typical submodule (SM3).
without divergence regardless of the power variation. Fig. 6. Measured steady-state waveforms of proposed MMDC.
 Fig. 7. Measured waveforms of MMDC when the input current steps up from 10A to 20A.
V. CONCLUSION
By reconstructing the classical HBSM structure into a
quasi-resonant circuit, a novel MMDC for step-up
applications along with its modulation strategies is proposed
in this paper. By employing resonant currents to transfer
balance power among the submodules, the common-mode
circulating current existing in conventional HBSM-based
MMDCs which flows through the arms and dc stage is
avoided. Also, soft switching is realized for the majority of
switches with the remaining switches turned on and off with
only dc component, and self-balancing of the capacitor
voltages are achieved which simplifies the control system.
Moreover, comparing with conventional MMDCs, the
amplitude of the voltage applied to the input filter inductor
is limited to the submodule voltage level, reducing the size
and volume of the inductor significantly.
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