IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO.
10, OCTOBER 2020
A High Gain Multiport DC–DC Converter for
Integrating Energy Storage Devices to DC Microgrid
Triptendu Chaudhury and Debaprasad Kastha , Senior Member, IEEE
Abstract—Interfacing multiple low-voltage energy storage de-
vices with a high-voltage dc bus efficiently has always been a
challenge. In this article, a high gain multiport dc–dc converter is
proposed for low voltage battery-supercapacitor based hybrid en-
ergy storage systems. The proposed topology utilizes a current-fed
dual active bridge structure, thus providing galvanic isolation of the
battery from the dc bus, wide zero voltage switching (ZVS) range
of all the switches, and bidirectional power flow between any two
ports. The dc bus side bridge uses voltage multiplier cells to achieve
a high voltage conversion ratio between the supercapacitor (SC)
and the dc bus. Moreover, as the proposed topology employs only
one two-winding transformer to achieve a three-port interface, the
number of control variables are reduced, which decreases control
complexities. The operation of the proposed converter is analyzed in
detail, including the derivation of ZVS conditions for the switches
and transformer power flow equations. A decoupled closed-loop
control strategy is implemented for the dc bus voltage control
and energy management of the storage devices under different
operating conditions. A 1-kW laboratory prototype is built to verify
the effectiveness of the proposed converter, along with the control
scheme.
Index Terms—Dual active bridge (DAB), hybrid energy storage,
multiport converter, pulsewidth modulation (PWM) plus phase-
shift control, switched capacitor, soft switched.
I. INTRODUCTION
UE to recent developments in renewable energy source
D based distributed generation systems, integration of en-
ergy storage systems (ESSs) is gaining increasing attention.
These ESS can improve the overall system reliability against the
intermittent nature of renewable energy sources such as solar and
wind energy. However, energy storage using a single technology
such as batteries or supercapacitors (SCs) faces difficulties in
supplying large power and large energy demands simultane-
ously [1], [2]. For example, commercially available batteries
(BATs) have high energy density and decent lifespan, but low
specific power and slow dynamic response. On the other hand,
SCs have a higher specific power, short charging/discharging
times, and long life cycle, but low energy density. Hence, com-
Manuscript received September 19, 2019; revised January 9, 2020; ac-
cepted February 21, 2020. Date of publication March 3, 2020; date of current
version June 23, 2020. Recommended for publication by Associate Editor
M. Ferdowsi. (Corresponding author: Triptendu Chaudhury.)
The authors are with the Department of Electrical Engineering, Indian
Institute of Technology Kharagpur, Kharagpur 721302, India (e-mail:
triptendu14@gmail.com; kastha@ee.iitkgp.ernet.in).
Color versions of one or more of the figures in this article are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2020.2977909
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10501
bined battery and SC-based hybrid ESSs are very appealing for
loads that have moderate average power demand and relatively
high peak power demand [3]. Conventionally, separate dc–dc
converters are used to interface different sources or storage ele-
ments with a common dc bus. As a result, power transfer between
the sources and storage elements becomes a two-stage process,
which reduces the overall efficiency of the system. In contrast,
a multiport converter (MPC) [4], [5] provides an interface for
different energy sources or storage elements utilizing a single
dc–dc converter. MPCs, thus, cut down the redundant power
conversion stages, which increases the system efficiency and
provides a more compact structure.
MPCs [6]–[10] can be divided into two main categories:
nonisolated and isolated. Nonisolated MPCs [6] are simpler
in design and more compact due to the lack of a transformer;
however, voltage levels of the ports are not flexible, and soft-
switching cannot be realized easily. On the other hand, isolated
MPCs [7]–[9] provide buck or boost capability utilizing the
transformer turns ratio. Isolated MPCs remain the popular choice
owing to their flexibility in routing the power flow between
the different ports as well as their superior performance [9],
[10]. Most of the isolated MPCs described in the literature are
derived from the dual active bridge (DAB) [11] converter, as it
provides high-frequency galvanic isolation, bidirectional power
flow, and soft switching. Compared to the traditional voltage-fed
DABs [11], current-fed DABs [12], [13] provide benefits such
as wide zero voltage switching (ZVS) range with varying port
voltages and increased voltage conversion ratio, thus making
them suitable for application in ESS.
Isolated MPCs can be subdivided into two main groups based
on their construction. Fully isolated MPCs combine three or
more ports using a single multiwinding high-frequency trans-
former, which provides isolation for all ports [7]. Several three-
port converter topologies [7], [14]–[17] have been reported in
the literature that utilize a triple active bridge (TAB) structure
(either half-bridge or full-bridge). However, control of these
converters is complicated, since there are several coupled control
variables. Moreover, the fully isolated MPCs [7], [15]–[17] have
a higher device count, and the multiwinding transformer handles
the entire output power; thus efficiency and power density are
reduced [10]. Partially isolated MPCs, which are the main focus
of this article, utilize a single-core two-winding transformer,
and two or more ports are coupled either at the primary or the
secondary terminals of the transformer [8], [9]. They provide
galvanic isolation while reducing the component count, making
them cheaper and more efficient.
10502
Fig. 1. Topology of the multiport dc–dc converter proposed in [22].
Several partially isolated MPCs have been proposed and
demonstrated in various applications such as distributed power
systems, electric vehicles, and ESSs [9], [18]–[20]. Wu et al. [19]
introduced a family of partially isolated three-port converters
based on bridgeless boost rectifiers for photovoltaic (PV)-battery
based renewable power systems. However, this topology is not
suitable for battery-SC-based hybrid ESS as only one of the
input port is current-fed. A partially isolated three-port converter
with a wide input voltage variation range was proposed in [20],
which combines a solar PV cell and a battery on the primary
side of the transformer. Although bidirectional power flow can
be realized among all the ports (using bidirectional switches),
the output power associated with each port on the primary side
is restricted, as the power output of one port is affected by
the duty ratio of the other port. In [21], Chien et al. proposed
a high gain three-port converter for PV-battery based renew-
able power systems. The proposed converter topology allows
interfacing low voltage sources/storage devices. However, the
power devices operate under hard-switching condition, which
limits the maximum switching frequency and reduces the overall
power density. In [22], Ding et al. proposed a partially isolated
three-port converter for battery-SC-based hybrid ESS. In this
topology (see Fig 1), the dc voltages Vc and VDC (see Fig. 1)
can be regulated to remain constant against wide variation in the
battery and the SC voltages (as well as load power) by controlling
the duty ratios of the lower switches of the respective bridges.
On the other hand, the power flow between the primary side
and secondary side is controlled through the phase shift angle φ.
However, in applications where the SC voltage rating is much
lower than the dc bus voltage (around 6–10 times), the dc bus
side active bridge switches need to operate with extremely high
duty ratio. This significantly increases the conduction losses,
and in some cases, ZVS of the secondary side switches are
lost, which hampers the overall efficiency. Most of the partially
isolated topologies in literature pose severe limitations toward
application in battery-SC-based hybrid ESS, where the battery
and the SC voltages are much smaller compared to the dc bus
voltage.
Power converters with high voltage conversion ratios have
been studied and implemented for several applications such as
voltage regulation modules (VRM), solar PV energy conversion
systems, and ESSs, to name a few [23], [24]. Transformer
isolated dc–dc converters (example: Flyback converter) and
coupled inductor based converters can achieve high voltage
step-up (or step-down) utilizing the turns ratio of the coupled
inductors. However, their power density is low and requires a
clamp circuit to eliminate any voltage spike due to the energy
trapped in the leakage inductor [25], [26]. On the other hand,
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 10, OCTOBER 2020
several switched-capacitor based dc–dc converters have been
proposed for applications, such as dc power supplies, VRM,
and electric vehicles [23], [27], [28], that feature high power
density and high voltage gain that can be easily extended. The
inductor-less switched-capacitor converter topologies proposed
in [27] and [29] provide high voltage step-up (or step-down)
ratio; however, they are most efficient when operated at fixed
duty ratio, thus provide a fixed voltage conversion ratio. The
series capacitor buck converter proposed in [30] provides half
the voltage conversion ratio (in buck mode) as compared to
a standard buck converter for the same duty ratio. The con-
verter also has several advantages such as reduced voltage stress
across some of the power devices (compared to the conventional
two-phase buck converter) and automatic balancing of the fil-
ter inductor currents. Although interleaved operation helps to
reduce the size of the filter inductors, the topology can only
be extended to achieve a higher voltage conversion ratio by
adding more number of phases, which, in turn, reduces the power
density. Marvi et al. [31] integrated coupled inductors with the
series capacitor buck converter to extend the voltage conversion
ratio. Although the introduction of coupled inductors provides
ZVS turn-ON for the switches, the power density is reduced
and requires additional snubber capacitors. Derived from the
series capacitor buck converter, the extended duty ratio buck
converter [32] provides a symmetric structure by introducing a
switched capacitor cell (referred to as a voltage multiplier (VM)
module). This topology retains the major advantages of the series
capacitor buck converter, while the voltage conversion ratio can
be extended by adding more VM modules [32], making the
topology a suitable candidate for applications that require a high
voltage conversion ratio. However, these switched-capacitor
converter topologies are hard-switched and do not provide a
multiport interface. Special attention is required for integrating
these topologies with a DAB/TAB structure to synthesize an
MPC. To the best of the author’s knowledge, no such topologies
have been reported in the literature, which integrates switched-
capacitor converters with the existing DABs/TABs to obtain a
multiport interface.
The major contribution of this article is to propose a par-
tially isolated MPC by combining the extended duty ratio buck
converter [32] and the two-phase buck/boost converter, using a
high-frequency transformer. The topological modification facil-
itates interfacing low-voltage energy sources/storage elements
with a high-voltage dc bus. The high-frequency transformer also
helps to realize zero voltage turn-ON for every switch, over the
entire operating range. Furthermore, the inclusion of the VM
module on the dc bus side helps to reduce the peak voltage stress
across some of the power semiconductors as compared to the
existing partially isolated MPCs [18], [20]–[22]. A pulsewidth
modulation (PWM) plus phase-shift control scheme is proposed,
which helps to realize decoupled power flow control, and, thus,
significantly reduce the control complexities. The proposed
control philosophy, along with the energy management scheme,
is also applicable for the existing MPCs in battery-SC-based
hybrid ESS [22].
The article is organized as follows. In Section II, the topol-
ogy and its operating modes are investigated along with the
CHAUDHURY AND KASTHA: HIGH GAIN MULTIPORT DC–DC CONVERTER FOR INTEGRATING ENERGY STORAGE DEVICES 10503

Fig. 2. Topology of the proposed high gain multiport dc–dc converter.

Fig. 3. Sketch of the drive signals for the power switches and the operational waveforms: (a) Primary side; (b) Secondary side; (c) Transformer winding voltages
and the leakage inductor current.

derivation of the power flow equations and the soft-switching
conditions. Section III provides a detailed small-signal model
of the converter. A decoupled closed-loop control scheme is
proposed for the dc-link voltage control and energy manage-
ment of the storage elements. The feasibility of the proposed
topology and the effectiveness of various controllers are verified
by experimental results in Section IV. Finally, the conclusion is
drawn in Section V.
II. PROPOSED TOPOLOGY AND ITS OPERATION
A. Topology Description
The power circuit of the proposed high gain MPC is shown
in Fig. 2. The converter on each side of the transformer is called
a unit. For the primary unit, switches Q1 –Q4 form a two-phase
interleaved buck/boost converter, with L1 and L2 as the filter
inductors, and Cp as the clamp capacitor. On the secondary unit,
inductors L3 , L4 and switches Q5 –Q10 constitute a two-phase
buck/boost converter (similar to the primary unit) with a VM
module, in which the high-voltage port is connected to the dc
bus, and the low-voltage port is connected to the SC. The gate
drive signals along with the predicted theoretical waveforms are
depicted in Fig. 3.
In the proposed high gain MPC, Dp represents the duty ratio
of the primary side bottom switches (Q3 or Q4 ). Similarly, Ds
is the duty ratio of the secondary side bottom switches (Q7 or
Q8 ). Therefore, although the battery and the SC voltages may
vary, Vc and VDC can be kept constant employing PWM control.
Power transfer between the primary and secondary depends on
the phase shift angle φ and the ac inductor LLk (combination of
external inductance and leakage inductance of the transformer,
referred to the primary side). The transformer also helps to
achieve proper voltage matching between the primary and the
secondary, i.e., Vc = nVDC /2 (where Np : Ns = n), which, in
turn, reduces the RMS current of the transformer and reduce the
conduction losses [33]. The detailed operation of the primary
and secondary units of the proposed high gain MPC is discussed
next.
B. Detailed Operation of the Converter Units
To simplify the analysis, all semiconductor devices are treated
as ideal, and deadtime durations are neglected. Also the ca-
pacitors Cp , Cs1 , Cs2 , and CDC are assumed to be large, so
that their voltage ripples may be neglected. Fig. 4(a) shows the
circuit diagram of the primary unit of the proposed high gain

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10504 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 10, OCTOBER 2020

Fig. 4. (a) Schematic of the multiphase buck/boost converter. (b) Mode AI (τα0 < t ≤ τα1 ). (c) Mode AII (τα1 < t ≤ τα2 ) and Mode AIV (τα3 < t ≤ τα4 ).
(d) Mode AIII (τα2 < t ≤ τα3 ).

TABLE I TABLE II
OPERATION OF THE MULTIPHASE BUCK/BOOST CONVERTER OPERATION OF THE EXTENDED DUTY RATIO MULTIPHASE
BUCK/BOOST CONVERTER

MPC, which is a bidirectional two-phase buck/boost converter.

Operation of the two-phase buck/boost converter in a switching
period can be divided into four modes, as described briefly in
Table I. Circuit configurations during each of these operational
modes are shown in Fig. 4(b)–(d). The gate drive signals along
with the important system variables are shown in Fig. 3(a), with
bottom switch duty ratio Dp greater than 0.5, and assuming
L1 = L2 = Lp .
At steady-state, the voltage across the clamp capacitor Cp
(Vc ) can be determined by applying volt-second balance across
the inductors L1 or L2 and is given by open, and a high-frequency transformer winding is connected
between the switch nodes “a” and “b.” It is to be noted that
VBAT Dp Ts = (Vc − VBAT ) (1 − Dp ) Ts although the load terminal is kept open here, it can be utilized
VBAT to connect other sources or storage elements (example: PV).
Vc = . (1) Fig 5(a) shows the circuit diagram of the secondary unit of
1 − Dp
the proposed high gain MPC (without the high-frequency trans-
The battery current is given as iBAT = iL1 + iL2 . As the gate former), which is a bidirectional two-phase buck/boost converter
pulses of Q1 and Q2 are 180◦ phase-shifted (interleaving PWM with a single VM module [32]. Switches Q5 and Q10 are gated
control), the battery current ripple is greatly reduced. Due to together, and so are Q6 and Q9 ; however, their gate pulses are
interleaving PWM control, the voltage vab is purely ac, having 180◦ out of phase, as shown in Fig 3(b). With this gate pulse
voltage levels Vc , 0 and −Vc [see Fig. 3(a)]. The primary unit pattern, the secondary unit also has four operational modes,
of the proposed high gain MPC is somewhat different from the which are described in Table II. The circuit configurations in
converter shown in Fig. 4(a). Here, the load terminal is kept each of these modes are shown in Fig. 5(b)–(d), and the key

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CHAUDHURY AND KASTHA: HIGH GAIN MULTIPORT DC–DC CONVERTER FOR INTEGRATING ENERGY STORAGE DEVICES 10505

Fig. 5. (a) Schematic of the extended duty ratio multiphase buck/boost converter. (b) Mode BI (τβ0 < t ≤ τβ1 ). (c) Mode BII (τβ1 < t ≤ τβ2 ) and Mode BIV
(τβ3 < t ≤ τβ4 ). (d) Mode BIII (τβ2 < t ≤ τβ3 ).

waveforms assuming L3 = L4 = Ls are shown in Fig. 3(b). At

steady state, applying volt-second balance across inductor L3
VSC Ds Ts + (VSC − Vcs2 ) (1 − Ds ) Ts = 0
VSC
Vcs2 = . (2)
1 − Ds
Similarly applying volt-second balance across inductor L4
VSC
Vcs1 = . (3)
1 − Ds
Also from Fig. 5(b) and (d), VDC = Vcs1 + Vcs2 . Thus
VSC VDC
Vcs1 = Vcs2 = = . (4)
1 − Ds 2
Therefore, the voltage gain of the extended duty ratio buck/boost
converter is given by
2 VSC
VDC = . (5)
1 − Ds
It should be noted that the feasible range of duty ratio for the
extended duty ratio buck/boost converter is Ds > 0.5. Under
steady-state conditions, during OFFstate, the voltage blocked by
the switches Q5 − Q8 is only VDC /2. Only switches Q9 and
Q10 block a maximum voltage of VDC during OFFstate. One
very desirable feature of the extended duty ratio buck/boost
converter is the inherent filter inductor current balancing [32].
This eliminates the requirement of individual inductor current
sensing and their current control. The voltage vcd has three lev-
Fig. 6. High-frequency power flow modes with different phase shift
els, i.e., VDC /2, 0 and −VDC /2 [see Fig. 3(b)]. A high-frequency φ. (a) Mode I (0 ≤ φ ≤ π (Dp − Ds )). (b) Mode II (π (Dp − Ds ) ≤
transformer winding can, thus, be connected between the switch φ ≤ π (Dp + Ds − 1)). (c) Mode III (π (Dp + Ds − 1) ≤ φ ≤ π/2). (d)
nodes “c” and “d” (see Fig. 2), which facilitates power flow at Mode IV (π (Ds − Dp ) ≤ φ ≤ 0). (e) Mode V (π (1 − Dp − Ds ) ≤ φ ≤
π (Ds − Dp )). (f) Mode VI (− π/2 ≤ φ ≤ π (1 − Dp − Ds )).
high frequency.
The extended duty ratio buck/boost converter can be general-
ized for “N” VM modules, as in [32]. The generalized voltage
gain expression is given as the secondary unit switches to achieve ZVS [34] (with proper
N +1 voltage matching). In order to simplify the power expressions,
VDC = VSC . (6) define Dp = 1 − Dp , Ds = 1 − Ds . For Mode I [see Fig. 6(a)],
1 − Ds
the following relations are obtained:
C. Transformer Power Flow Equations
 
Depending on the phase-shift angle φ, the power flow between n VDC 0.5 − Dp 0.5 − Ds φ
Iv − Iw = − −
the primary and the secondary units can be classified into several 2 fs LLK 2 2 2π
modes for both φ > 0 and φ < 0. These modes are defined  
based on the profile of the leakage inductor current as shown in n VDC 0.5 − Dp 0.5 − Ds φ
Iv + Iw = − + . (7)
Fig. 6(a)–(f). The waveforms are shown for Dp > Ds , as it helps 2 fs LLK 2 2 2π

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10506 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 10, OCTOBER 2020

TABLE III D. ZVS Analysis

iLK AT DIFFERENT SWITCHING INSTANTS
TABLE IV
TRANSFORMER POWER FLOW EXPRESSIONS
In order to realize zero voltage turn ON for any switch, the
switch current at the turn-ON instant must be negative, so that the
switch current at the instant of turn-ON actually flows through the
body diode. To ensure this for all switches in the proposed topol-
ogy, certain conditions need to be satisfied, which are analyzed
in this section. The primary unit of the proposed high gain MPC
is shown in Fig. 2. Let us analyze the switching transition for the
switch leg containing the switches Q1 and Q3 , assuming L1 =
L2 = Lp . The transition for the other leg is exactly similar. When
the switch Q1 turns OFF, then the current through the inductor
L1 is minimum (since it has been discharging into the clamp
capacitor Cp till then) and is given by ILp(min) [see Fig. 3(a)].
Then, the current flowing through the switch Q3 at the instant of
its turn-ON is ILp(min) − iLk |Q3 → ON (iLk |Q3 → ON indicates the
value of leakage inductor current iLk at the instant when switch
Q3 turns ON). Consequently, the necessary condition for Q3 to
turn-ON under ZVS is

iLk |Q3 → ON > ILp(min) . (11)

Similarly when switch Q3 turns OFF, the current through the

inductor L1 is maximum (as it was being charged by the battery
till then) and is given by ILp(max) [see Fig. 3(a)]. Then, the
Solving for Iv and Iw necessary condition for Q1 to turn-ON under ZVS is

n VDC   iLk |Q1 → ON < ILp(max) . (12)

Iv = π Ds − Dp
2 XLK
The value of iLk at the switching instant is a function of phase
n VDC
Iw = φ (8) shift angle φ, whereas ILp(max) or ILp(min) depend on the value
2 XLK of the filter inductance Lp . Thus, the appropriate choice of the
where XLK represents the leakage reactance, i.e., filter inductors ensures ZVS turn-ON for all the switches over
the entire operating range. Similarly, for the secondary unit,
ZVS condition of the switches Q5 –Q10 depend on the reflected
XLK = 2 π fs LLK . leakage inductor current iLk (= niLk ) at the switching instant
The transformer power flow equation is given as and the filter inductance L3 and L4 (assumed to be equal to Ls ).
Table VI lists the necessary ZVS conditions for all switches
 Ts
2 2 of the proposed high gain MPC (where Iγ denotes the leakage
Ptx = vab iLk dt. (9)
Ts 0 inductor current at different switching instants referred to the
secondary side, γ ∈ {v, w, x, y}). The expressions for Iv , Iw ,
Solving (9) for Mode I
Ix , and Iy can be found in Table III.
n Vc VDC The aforementioned conditions (from Table VI) are, however,
Ptx = Dp φ. (10)
XLK only necessary conditions and not sufficient. For example, at the
instant when Q1 turns OFF, the difference current of L1 and LLk
The closed-form expressions of the leakage inductor current
must be sufficient to charge and discharge the output capacitance
levels at different switching instants and the transformer power
of Q1 and Q3 , respectively, and there must be sufficient deadtime
flow in various modes can be obtained in a similar fashion.
between Q1 and Q3 .
Table III lists the expressions for the leakage inductor current
Considering these requirements, ZVS condition for primary
levels at different switching instants, as shown in Fig. 6(a)–(f).
unit bottom switch Q3 (since it is difficult to achieve ZVS turn
The transformer power flow equations in each of the modes are
ON for the primary unit bottom switches, with φ > 0) is given
listed in Table IV [34]. The value of the leakage inductor LLk is
by
decided based on the maximum power delivered (or absorbed)
by the battery at φ = π/2 (or φ = −π/2). Ptx VBAT Dp Ts Vc Vc
The expressions for the peak voltage and current stress of − + 2 Coss ≤ φ (13)
2 VBAT 2 Lp tdead XLk
the different switches are listed in Table V, neglecting compo-
nent nonidealities and assuming that the converter operates in The term (2 Coss Vc /tdead ) denotes the current required to charge
Mode III and Mode VI (with φmax = π/2 and φmin = − π/2, (and discharge) the output capacitor (Coss ) of Q3 (and Q1 ) within
respectively). the deadtime (tdead ).

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CHAUDHURY AND KASTHA: HIGH GAIN MULTIPORT DC–DC CONVERTER FOR INTEGRATING ENERGY STORAGE DEVICES 10507

TABLE V
PEAK SWITCH VOLTAGE AND CURRENT STRESS

TABLE VI
ZVS CONDITIONS FOR ALL SWITCHES

Fig. 7. (a), (b) ZVS boundaries for the primary unit bottom switches as
functions of VBAT and φ (with primary unit filter inductors Lp1 and Lp2
respectively, Lp1 < Lp2 ). The colored portion indicates the ZVS region.

It is difficult to obtain a closed-form solution of (13). Hence,

Fig. 7(a) and (b) plots the ZVS boundaries for the primary unit
bottom switches as functions of the battery voltage VBAT and the
phase shift angle φ (for nominal SC voltage). These plots are
shown for two different values of the primary unit filter inductors
Lp1 [see Fig. 7(a)] and Lp2 [see Fig. 7(b)].
Likewise, one can choose the secondary unit filter inductors
to achieve ZVS operation of the secondary unit switches. With
PSC > 0 and φ > 0, it is difficult for the bottom switches (Q7
and Q8 ) to achieve ZVS.1 Considering the deadtime transitions,
ZVS condition for secondary unit bottom switch Q7 is given as
PSC VSC Ds Ts VDC
− iLk |Q7 → ON − + ≥ 3 Coss . (14)
2 VSC 2 Ls 2 tdead
1 While considering the ZVS condition for the secondary unit switches, P
SC
and φ are considered to be independent.
Fig. 8. (a), (b) ZVS boundaries for secondary unit bottom switches as functions
of VSC and PSC (with secondary unit filter inductors Ls1 and Ls2 respectively,
Ls1 < Ls2 , and φ = π/20) (c), (d) ZVS boundaries for secondary unit bottom
switches as functions of VSC and φ (with secondary unit filter inductors Ls1 and
Ls2 respectively, and PSC = 0.75 PSC,MAX ). The colored portion indicates the
ZVS region.
Fig. 8(a)–(b) plots the ZVS boundaries for the secondary unit
bottom switches as functions of the SC voltage VSC and the
SC power PSC (with nominal battery voltage and the converter
operating in Mode I, φ = π/20). Here also, the plots are shown
for two different values of secondary unit filter inductors Ls1 [see
Fig. 8(a)] and Ls2 [see Fig. 8(b)]. Fig. 8(c)–(d) shows the ZVS
regions for Q7 as functions of the SC voltage VSC and the phase

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10508 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 10, OCTOBER 2020

TABLE VII
SYSTEM SPECIFICATIONS
operating point, i.e., dp = Dp + dˆp , ds = Ds + dˆs , and φ =
φ0 + φ̂. The time varying inputs produce perturbations in the
state variables, thus we have vc = Vc + vˆc , vDC = VDC + vDC ˆ ,
vSC = VSC + vˆSC , iBAT = IBAT + iBATˆ , and iSC = ISC + iSC
ˆ (for
this analysis, leakage inductor current of the transformer iLk
is not considered as a state variable). As analyzed in [35], the
inclusion of an additional capacitor in a series capacitor buck
converter do not influence the transfer characteristics. Thus, in
the proposed converter, the dynamics of Cs1 and Cs2 are ne-
∗
External.
glected. For the sake of simplicity, we assume that the operation
∗∗
Magnetizing inductance referred to the primary side. of the converter is limited in Mode I [0 ≤ φ ≤ π (Dp − Ds ),
similar to Fig. 6(a)].
The expression for the average current through the primary
shift angle φ with constant PSC . The plots are shown for PSC = side clamp capacitor Cp over a switching period is given as
0.75 PSC,MAX , with two different values of filter inductors, Ls1
[see Fig. 8(c)] and Ls2 [see Fig. 8(d)]. dvc n vDC
Cp = (1 − dp ) iBAT − (1 − dp ) φ. (15)
A current-fed DAB provides a much wider range of ZVS, dt XLK
compared to a voltage-fed DAB; however, at the expense of
Linearising (15) about the steady-state operating point and
increased conduction losses. The filter inductors of the primary
equating the first-order ac terms, we get
and secondary units are chosen, based on the current ripple
 
necessary to obtain full range ZVS. If the inductors are small, (1 − Dp ) ˆ (s) − n φ0 vDC
the ripple is larger, which, in turn, increases the conduction loss. vˆc (s) = iBAT ˆ (s) . (16)
s Cp XLk
In [34], Sha et al. analyzed all possible switching patterns in a
current-fed DAB. If the primary unit of the DAB is current-fed As described earlier, the dynamics of vSC is much slower as
while the secondary unit is voltage-fed, then Dp > Ds ensures compared to the switching dynamics, hence variation of φ
that the secondary unit will achieve ZVS, even under light is neglected in (16). The switching average voltages appear-
load conditions [34] (with voltage matching control). This is ing across the primary unit filter inductors L1 and L2 are
due to the profile of the leakage inductor current, produced given as
by two high-frequency ac waveforms, applied on either side diL1
of the transformer. Hence, this condition is always satisfied in L1 = vBAT − (1 − dp ) vc (17)
dt
the proposed high gain MPC, which helps to reduce the current
diL2
ripple of the secondary unit filter inductors, and, in turn, reduces L2 = vBAT − (1 − dp ) vc . (18)
the conduction loss. dt
Based on the transformer power flow equations and ZVS Assume L1 = L2 = Lp . Combination of (17) and (18) yields
conditions as specified in Section II-C and Section II-D, re-
diBAT
spectively, one can choose the parameters of the converter. The Lp = 2 vBAT − 2 (1 − dp ) vc . (19)
voltage across the clamp capacitor on the primary unit (Vc ) is dt
chosen to ensure Dp > Ds , under steady-state operating condi- Linearizing (19) around the steady-state operating point and
tions. From the designed values of Vc and VDC , the transformer considering only first-order ac terms, we obtain
turns ratio Np : Ns is decided to realize the voltage matching  
control, and, thus, reduce the transformer RMS current. The ˆ (s) = 2 Vc dˆp (s) − (1 − Dp ) vˆc (s) .
iBAT (20)
s Lp Vc
leakage inductor LLk is determined based on the maximum
power delivered (or absorbed) by the battery at the maximum (or For the secondary unit, the expression of the switching average
minimum) phase shift angle. The filter inductors of the primary current through the dc bus capacitor CDC is given as
unit L1 and L2 are chosen to ensure ZVS turn-ON for the primary
unit switches Q1 − Q4 over the entire operating range. Similar is dvDC (1 − ds ) n vc vDC
CDC = isc + (1 − dp ) φ − (21)
the case for the secondary unit filter inductors L3 and L4 . Finally, dt 2 XLK R0
the switches for the primary and secondary units are chosen where R0 represents the load resistance. Linearizing (21) about
based on the peak voltage and current stress, as per Table V. For the steady-state operating point, we get
this work, the choice of the converter parameters are listed in
Table VII. ˆ (s)
vDC (1 − Ds ) ˆ
ˆ (s) +
s CDC vDC = iSC (s)
R0 2
 
III. MODELING AND CONTROL VDC n Vc φ0 (1 − Dp ) ˆ
− − ds (s)
A. Small Signal Modeling (1 − Ds ) R0 XLk (1 − Ds )

To obtain the small-signal model for the converter, the con- n (1 − Dp ) φ0 n Vc φ 0 ˆ

+ vˆc (s) − dp (s). (22)
trol inputs are given small variation around the steady-state XLk XLk

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CHAUDHURY AND KASTHA: HIGH GAIN MULTIPORT DC–DC CONVERTER FOR INTEGRATING ENERGY STORAGE DEVICES 10509

Fig. 9. Detailed schematic of the control block diagram for the proposed high gain MPC.

Similar to (16), the variation of φ is neglected in (22). The voltage and the phase shift are considered (i.e., vˆSC = 0 , φ̂ = 0 ).
expression for SC current dynamics is given by Equation (27) is linearized about the steady-state operating
diSC point. Comparing the first-order ac terms, we obtain
Ls = 2 vSC − (1 − ds ) vDC . (23)
dt n Vc VDC (1 − Dp )
Linearising (23) about the steady-state operating point and col- s CSC VSC vˆSC (s) = φ̂(s). (28)
XLK
lecting the first-order ac terms
  Equations (16), (20), (24), (26), and (28) provide the small-signal
ˆ (s) = VDC dˆs (s) − (1 − Ds ) vDC
iSC ˆ (s) . (24) ac model of the proposed high gain MPC.
s Ls VDC
Substituting dˆp (s) and dˆs (s) in (22), we obtain B. Proposed Control Philosophy
 
2 φ0 (1 − Dp ) In a battery-SC-based hybrid ESS, the purpose of the MPC
s CDC + −  ˆ (s)
vDC is to dynamically allocate the load between the battery and
R0 2 XLk
  the SC. Under pulsed load conditions, the SC acts as a filter
Ls φ0 (1−Dp ) Ls (1 − Ds ) ˆ that relieves peak power stresses on the battery. Hence, it is
=  (1−D ) s− s + iSC (s)
2 XLk s (1 − Ds ) R0 2 appropriate that the SC current essentially controls the dc bus
n Lp φ0 voltage VDC . However, then under normal operating conditions,
− ˆ (s)
s iBAT (25) the SC voltage VSC will vary drastically. Therefore, the phase
2 XLk
shift φ between the two voltages vab and vcd (see Fig. 3) is used

where XLk denote the equivalent leakage inductance of the to control the average SC voltage. To reduce the RMS value of
transformer, referred to the secondary side. If the dynamics of the leakage inductor current iLk and the losses, voltage Vc must
the battery current control loop is much faster than the dc bus also be controlled such that proper voltage matching is ensured
voltage control loop, s iBAT ˆ (s) in (25) can be neglected. Thus, The detailed control block diagram for the proposed high
we obtain gain MPC (along with the plant model) is shown in Fig. 9,
 
2 φ0 (1 − Dp ) which consists of three parts: the primary unit controller, the
s CDC + −  ˆ (s)
vDC
R0 2 XLk secondary unit controller, and the phase shift controller. The
  primary unit controller ensures that the primary side clamp
Ls φ0 (1 − Dp ) Ls (1−Ds ) ˆ
=  s− s+ iSC (s). capacitor voltage remains regulated, so that voltage matching
2 XLk (1−Ds ) (1 − Ds ) R0 2 is achieved; whereas, the secondary unit controller ensures that
(26) the dc bus voltage remains regulated with fast dynamic per-
The SC voltage dynamics can be obtained from the power formance. Both the controller units have a conventional nested
balance equation of the secondary unit, and is given as two-loop structure with an outer voltage control loop and inner
2 2 2
current control loop. Proportional-Integral (PI) controllers are
1 dvSC n vc vDC 1 dvDC vDC
CSC = (1 − dp ) φ − CDC − . used throughout with appropriate feed-forward compensation
2 dt XLK 2 dt R0 terms (see Fig. 9). The phase shift controller also employs a slow
PI controller to control the average SC voltage, which, in turn,
(27)
generates the reference phase shift command. The proportional
The control variable φ is used to control the average SC volt- and integral control gains of the different PI controllers are
age. Variation of φ is much slower compared to the switching chosen based on the desired bandwidth and phase margin. The
frequency (even several times slower than the primary and choice of the proportional and integral control gains of the
secondary unit controllers). Hence, only perturbations in the SC various PI controllers along with the resulting bandwidths and

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10510 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 10, OCTOBER 2020

TABLE VIII
CHOICE OF PROPORTIONAL AND INTEGRAL CONTROL GAINS OF VARIOUS CONTROLLERS

phase margins of the different loops are listed in Table VIII (for
the system specifications mentioned in Table VII).
C. Effect of Operating Point Variation
In a battery-SC-based hybrid ESS, the variations in battery
and SC voltage, as well as the load, may affect the stabil-
ity/performance of the control system, which is designed based
on the linearized small-signal model. According to the small-
signal model of the proposed high gain MPC (as obtained in
Section III-A) and the proposed controller (see Fig. 9), the
closed-loop transfer functions are given by (29)–(33), shown
at the bottom of this page. For the transfer functions GCL,iBAT (s)
(30) and GCL,iSC (s) (32), the location of the closed-loop poles
are independent of the operating point (since the voltages Vc
and VDC are tightly regulated). Location of the poles for the
closed-loop system GCL,vc (s) (29) depend on battery voltage
VBAT , while the zero remains fixed. Fig. 10(a) shows the position
of the poles and zeros of GCL,vc (s), with VBAT varying from 55
to 65 V. To achieve desired bandwidth and phase margin, the
closed-loop zero is located near the pole closer to the origin.
The closed-loop system GCL,vDC (s) contains two poles and two
zeros, with both poles and one zero being dependent on operating
conditions like nominal duty ratios (Dp and Ds ), nominal phase
shift angle (φ0 ), and nominal load (R0 ). Fig. 10(b) and (e) shows
that the closed-loop poles of GCL,vDC (s) lie on the left half of
s-plane, with variations in VSC (40–52 V), VBAT (55–65 V), φ0
(0–π/4), and R0 (48.3–193.6 Ω). Here again, the pole closer to
the origin is nondominant as it is accompanied by the zero of the
PI controller. Likewise, for the closed-loop system GCL,vSC (s),
the pole locations are dependent on the ratio of VSC to VBAT .
Fig. 10(f) shows the pole-zero locations of GCL,vSC (s) with the
ratio VSC / VBAT varying from 0.945 to 0.615 (considering CSC =
10 F). Variations in the operating conditions affect the bandwidth
of the closed-loop systems, which is typical for a PI controller
with fixed controller gains. However, the system is always stable
for the variations, as described. Besides, all the closed-loop poles
lie on the real axis; hence, the system does not experience any
underdamped oscillations under any operating condition.
IV. EXPERIMENTAL VERIFICATION AND
COMPARATIVE ANALYSIS
In order to verify the operation of the proposed high
gain MPC, experiments were conducted on a 1-kW labora-
tory prototype fabricated with discrete components. SuperFET
(FCH023N65S3-F155) was used as the switching device in both
the bridges. A photograph of the laboratory prototype is shown
in Fig 11 (excluding the high-frequency transformer and filter
inductors). Ratings and parameters of the experimental setup are
provided in Table VII. Two three-phase diode bridge rectifiers
were used to emulate the battery and the SC. The proposed


vˆc (s)  s Kp1 + Ki1
GCL,vc (s) = ∗  = (29)
vˆc (s) iBATˆ(s) = 0 C p
s2 + s Kp1 + Ki1
1 − Dp
ˆ (s)
iBAT s Kp2 + Ki2
GCL,iBAT (s) = = (30)
ˆ ∗ (s)
iBAT L p
s2 + s Kp2 + Ki2
2 Vc

ˆ (s) 
vDC s2 Kp3 ζ0 + s (ζ0 Ki3 + ζ1 Kp3 ) + ζ1 Ki3
GCL,vDC (s) = ∗  = 2 (31)
ˆ (s) iSCˆ(s) = 0
vDC s (CDC + Kp3 ζ0 ) + s (ζ2 + ζ0 Ki3 + ζ1 Kp3 ) + ζ1 Ki3
ˆ (s)
iSC s Kp4 + Ki4
GCL,iSC (s) = = (32)
ˆ ∗ (s)
iSC L s
s2 + s Kp4 + Ki4
VDC
vˆSC (s) s Kp5 + Ki5
GCL,vSC (s) = = (33)
vˆSC ∗ (s) s 2
μ0
+ s Kp5 + Ki5
VDC
 
CSC VSC XLk Ls φ0 (1 − Dp ) 1 1 − Ds 2 φ0 (1 − Dp )
where μ0 = , ζ0 =  − , ζ1 = , ζ2 = − 
n Vc (1 − Dp ) 1 − Ds 2 XLk R0 2 R0 2 XLk

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CHAUDHURY AND KASTHA: HIGH GAIN MULTIPORT DC–DC CONVERTER FOR INTEGRATING ENERGY STORAGE DEVICES 10511

Fig. 10. (a) Pole-zero location of the closed-loop transfer function GCL,vc with variation in VBAT (55–65 V). (b)–(e) Pole-zero location of the closed-loop transfer
function GCL,vDC with variations in VSC (40–52 V), VBAT (55–65 V), φ0 (0–π/4), and R0 (48.3–193.6 Ω), respectively. (f) Pole-zero location of the closed-loop
transfer function GCL,vSC with variation in VSC and VBAT (VSC / VBAT varying from 0.945 to 0.615).

the converter is shown in Fig. 12(d), with VBAT = 57 V and

Fig. 11. Photograph of the laboratory prototype.
control philosophy is implemented digitally using a Kintex-7
based FPGA development board (programmed using Verilog
HDL).
Fig. 12 shows the steady-state waveforms with VBAT = 60 V
and VSC = 48 V. Based on the value of φ (φ > 0), the operation
of the converter is shown in Mode I [see Fig. 12(a)] and Mode II
[see Fig. 12(b)], respectively. The operation of the converter with
PSC < 0 (i.e., SC being charged) is highlighted in Fig. 12(c). For
this, an additional rheostat was connected across the SC port
(since diode rectifiers are unidirectional). Here, the converter
operates in Mode I, hence profile of the leakage inductor current
is similar to that shown in Fig. 12(a); however, the average
SC current remains negative (VBAT = 62 V and VSC = 48 V).
With negative phase-shift angles (φ < 0), the operation of
VSC = 52 V. Here, the converter operates in Mode IV, with
PBAT < 0 (additional rheostat connected across the battery port).
As observed from Fig. 12(d), the battery current is negative,
which indicates that the battery is being charged. Zero voltage
turn-ON is achieved by all switches, even for small values of φ.
Fig. 13(a) and (b) shows that switches Q1 , Q4 , Q7 , and Q9 get
ZVS for φ = 8.1◦ . Due to symmetry of the proposed converter,
ZVS of the other switches can be guaranteed for similar oper-
ating conditions. The filter inductor currents of the primary and
secondary units are shown in Fig. 13(c)–(d) (with PDC = 480
W). As can be seen from Fig. 13(c), the battery current is the
sum of the filter inductor currents iL1 and iL2 , and, thus, have
a ripple of frequency 50 kHz (double the switching frequency).
Similar argument holds true for the SC current [see Fig. 13(d)].
Fig. 14(a) highlights the performance of the controller during
load transients, with a step-change in load varying initially from
480 to 700 W, and finally settling to 480 W (with VBAT = 59 V
and VSC = 47 V). For both the primary and secondary unit
controller, the bandwidth of the inner current loop is kept at
2.5 kHz, while the outer voltage loop bandwidth is kept at 80 Hz.
Dc bus voltage vDC remains well regulated with maximum
overshoot/undershoot of 6 V and a settling time of 40 ms, as
can be observed from Fig 14(a). Proper voltage matching is
ensured, since the primary unit clamp capacitor voltage vc also
remains constant. The difference in the voltages of the switched
capacitors vcs1 and vcs2 are insignificant, even during transients,
as seen from Fig. 14(b). Fig. 14(c) highlights the performance of
the battery and the SC during load transients (iBATf and iSCf rep-
resents the filtered values of iBAT and iSC , respectively). The SC
compensates for the load transients by delivering or absorbing
the additional power, whereas the battery current remains almost
constant, which eventually improves battery life. Fig. 14(d)

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10512 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 35, NO. 10, OCTOBER 2020

Fig. 12. Steady-state operating waveforms with different phase-shift φ. (a) Mode I (φ = 8.1◦ , PBAT = 220 W, PSC = 288 W, PDC = 480 W). (b) Mode II
(φ = 29.7◦ , PBAT = 985 W, PSC = 33.6 W, PDC = 970 W). (c) Mode I (φ = 11.25◦ , PBAT = 350 W, PSC = − 96 W, PDC = 228 W). (d) Mode IV (φ = −10.5◦ ,
PBAT = − 339 W, PSC = 605 W, PDC = 220 W).

Fig. 13. ZVS turn-ON of switches on the primary and secondary units in Mode I (φ = 8.1◦ , PBAT = 220 W, PSC = 288 W, PDC = 480 W). (a) Q1 and Q4
(b) Q7 and Q9 . Filter inductor currents of (c) the primary unit and (d) the secondary unit (φ = 8.1◦ , PBAT = 220 W, PSC = 288 W, PDC = 480 W).

Fig. 14. Performance evaluation of the proposed controller (a, b, c) Transient response with the load, initially varying from 480 to 700 W and finally settling to
480 W. (d) Phase shift controller enabled to track the reference SC voltage command of 46 V, with an output power of 480 W.

shows the performance of the phase shift controller, with an
SC voltage reference of VSC ∗ = 46 V (with additional rheostat
connected across the SC port). The phase-shift controller is
designed much slower, having a bandwidth of approximately
5 Hz. At time t = t1 , the phase shift controller is enabled.
As a result, the SC voltage tracks the reference command and
eventually settles at time t = t2 . The transients are observed to
settle within 150 ms (the ripple observed in the SC voltage vSC
is due to the three-phase diode bridge rectifier).
The efficiency2 characteristics of the developed hardware
prototype are experimentally verified in Fig. 15 (with φ > 0),
2 For an MPC, efficiency is given as the ratio of the net output power to the
net input power.
and are shown for four different battery power levels while the
load power varies from 500 to 1000 W. Fig. 15(a) shows the
efficiency trends for VBAT = 61 V, VSC = 47 V, while Fig. 15(b)
corresponds to VBAT = 64 V, VSC = 50 V. The overall conversion
efficiency is high, and the maximum efficiency is 95.96%.
To evaluate the performance of the proposed high gain MPC
and the proposed control strategy, a comparison with the existing
MPCs is provided in Table IX. It can be seen that the number
of control variables ascend with the increase in the number of
transformer windings and control switches [7]. Although the
proposed topology utilizes more switches as compared to [18],
[19], and [22], the number of control variables are less, which
greatly reduces control complexities. Besides, the proposed
topology allows interfacing low-voltage energy storage devices

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CHAUDHURY AND KASTHA: HIGH GAIN MULTIPORT DC–DC CONVERTER FOR INTEGRATING ENERGY STORAGE DEVICES 10513

TABLE IX
COMPARISON OF THE PROPOSED TOPOLOGY WITH EXISTING MPCs

∗
Requires two additional resonant inductors and one resonant capacitor.
α
ZCS turn-OFF for only switch S1 , switches S2 and S3 operate under hard switching conditions.
β
ZVS turn-ON for the MOSFETs and ZCS turn-OFF for the diodes.
δ
Difficult to achieve ZVS for the secondary unit bottom switches when operating with low voltage SC.
ι
Switches Q5 –Q8 block half the dc bus voltage. Only switches Q9 and Q10 block the entire dc-link voltage.
κ
MOSFETs block half of the dc bus voltage, while the diodes block the entire dc bus voltage.
λ
Efficiency plotted as a function of Port-3 power, while the Port-2 power remains constant.
μ
Power transferred from battery port to load port.

management of the SC under different operating conditions.

Fig. 15. Experimental efficiency characteristics of the developed hard-
ware prototype. (a) Operating Condition #1: PBAT ≈ 210 W, Operating
Condition #2: PBAT ≈ 380 W. (b) Operating Condition #3: PBAT ≈ 300 W,
Operating Condition #4: PBAT ≈ 500 W.
with a high-voltage dc bus, retaining ZVS turn-ON for all the
switches (unlike [22]). The peak voltage stress of the switches
are compared as well, where 1.0 per unit corresponds to the
clamping capacitor voltage of the respective bridges. The devel-
oped hardware prototype also attains higher peak efficiency, as
compared to the existing MPCs.
V. CONCLUSION
In this article, a novel high gain multiport dc–dc converter,
suitable for integrating low voltage energy storage devices in a
dc microgrid, is proposed. The proposed topology provides a
three-port interface utilizing only one two-winding transformer,
which significantly reduces control complexities. The inclusion
of a VM module helps to increase the voltage conversion ratio
between the SC and the dc bus. With careful choice of the
primary unit clamp capacitor voltage and filter inductors of the
respective converter units, it is possible to achieve ZVS operation
of all switches over the entire operating range. A decoupled
closed-loop control strategy is proposed, which ensures dc-link
voltage control with fast dynamic performance and energy
Effectiveness of the proposed topology and the control strategy
are verified experimentally on a 1-kW laboratory prototype.
The developed hardware prototype achieves a peak efficiency
of 95.96%, which is superior in comparison with the existing
MPCs in literature. Experimental results also verify that the
proposed converter provides a fast dynamic response against
load variations along with energy management of the SC under
different operating conditions. Performance comparison of the
proposed high gain MPC with the existing solutions confirms
that the proposed converter has advantages such as reduced
voltage stress across some of the power devices, ZVS turn-ON
for all the switches over the entire operating range, and a much
simple control structure. Although ZVS turn-ON reduces the
switching losses, conduction losses of the different switches
are not balanced. Besides, the power density is low due to
the use of several discrete magnetic components. Hence, future
work will include efficiency optimizations and operation of the
converter at higher switching frequencies to extract the benefits
of soft-switching in improving power density without increasing
switching loss.
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Triptendu Chaudhury received the B.Tech. degree
in electrical engineering from the West Bengal Uni-
versity of Technology, Kolkata, India, in 2016 and
the M.Tech. degree in electrical engineering (with
specialization in machine drives and power electron-
ics) in 2019 from the Indian Institute of Technology
Kharagpur, Kharagpur, India, where he is currently
working toward the Ph.D. degree with the Department
of Electrical Engineering.
His research interests include topologies and con-
trol of isolated dc–dc converters and dc–ac converters.
Debaprasad Kastha (Senior Member, IEEE) re-
ceived the B.E. degree in electrical engineering from
the Indian Institute of Engineering Science and Tech-
nology, Shibpur, India (formerly Bengal Engineering
College, Calcutta University, Kolkata) in 1987, the
M.E. degree in electrical engineering (with special-
ization in power electronics) from the Indian Institute
of Science, Bangalore, India, in 1989, and the Ph.D.
degree from the University of Tennessee, Knoxville,
TN, USA, in 1993.
From March 1989 to December 1989, he was with
the Research and Development (Electronics) Division, Crompton Greaves,
Ltd., Mumbai, India. In April 1994, he joined the Department of Electrical
Engineering, Indian Institute of Technology, Kharagpur, India, where became a
Professor in 2011. He has been teaching and doing research in the area of power
electronics and drives for more than two decades now and has authored about 50
technical papers, books, and electronic teaching aids. He has coauthored a book
titled Wind Electrical Systems (Oxford University Press, 2005) and prepared
web-based and video courses on power electronics and electrical machines,
respectively, as parts of NPTEL program of Government of India. His research
interests include the areas of wind power generation, machine drives, dc power
supply, and distribution systems.