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1Gb NAND Flash: Datasheet
1Gb NAND Flash: Datasheet
2010
K9F1G08U0D
datasheet
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SPECIFICATIONS WITHOUT NOTICE.
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-1-
Rev. 1.1
0.1 1. Max tR value has changed from 35us to 40us May. 03, 2010 Advance H.K.Kim
2. Min tRC/ tWC value has changed from 30ns to 25ns
3. Chapter 2.9, 2.10 AC parameters revised
4. Chapter 2.3 ISB2 MAX value has changed from 50 to 80
5. Chapter 2.6 Capacitance value has changed from 8 to 10
1.0 1. FBGA pkg code change H->B Jul. 07, 2010 Final H.K.Kim
2. Device code(4th Cycle) has changed from 15h to 95h
3. Chapter 1.5.1 63ball FBGA pkg dimension has changed.
1.1 1. Chapter 2.4 NOTE is Amendment. Nov. 12, 2010 Final H.K.Kim
2. Chapter 1.4.1 PACKAGE DIMENSIONS revised.
3. Chapter 1.5 Pin Configuration (FBGA) revised.
-2-
Rev. 1.1
-3-
Rev. 1.1
1.2 Features
• Voltage Supply • Fast Write Cycle Time
- 3.3V Device(K9F1G08U0D) : 2.7V ~ 3.6V - Page Program time : 250μs(Typ.)
• Organization - Block Erase Time : 2ms(Typ.)
- Memory Cell Array : (128M + 4M) x 8bit • Command/Address/Data Multiplexed I/O Port
- Data Register : (2K + 64) x 8bit • Hardware Data Protection
• Automatic Program and Erase - Program/Erase Lockout During Power Transitions
- Page Program : (2K + 64)Byte • Reliable CMOS Floating-Gate Technology
- Block Erase : (128K + 4K)Byte -Endurance & Data Retention : Refor to the gualification report
• Page Read Operation -ECC regnirement : 1 bit / 528bytes
- Page Size : (2K + 64)Byte • Command Driven Operation
- Random Read : 40μs(Max.) • Unique ID for Copyright Protection
- Serial Access : 25ns(Min.) • Package :
- K9F1G08U0D-SCB0/SIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F1G08U0D-BCB0/BIB0 : Pb-FREE PACKAGE
63 FBGA (9 x 11 / 0.8 mm pitch)
-4-
Rev. 1.1
N.C 1 48 N.C
N.C 2 47 N.C
N.C 3 46 N.C
N.C 4 45 N.C
N.C 5 44 I/O7
N.C 6 43 I/O6
R/B 7 42 I/O5
RE 8 41 I/O4
CE 9 40 N.C
N.C 10 39 N.C
N.C 11 48-pin TSOP1 38 N.C
Vcc 12 37 Vcc
Vss 13 Standard Type 36 Vss
N.C 14 35 N.C
N.C 15 12mm x 20mm 34 N.C
CLE 16 33 N.C
ALE 17 32 I/O3
WE 18 31 I/O2
WP 19 30 I/O1
N.C 20 29 I/O0
N.C 21 28 N.C
N.C 22 27 N.C
N.C 23 26 N.C
N.C 24 25 N.C
MAX
20.00±0.20
0.004
0.10
0.787±0.008
+0.07
0.20 -0.03
#1 #48
( 0.25 )
0.010
+0.003
0.008-0.001
+0.07
0.16 -0.03
0.488 MAX
12.00
0.472
12.40
0.0197
0.50
#24 #25
1.00±0.05 0.05
0.039±0.002 0.002 MIN
1.20
0.010 TYP
+0.075
18.40±0.10 0.047MAX
0.125 0.035
+0.003
0.005-0.001
0.724±0.004
0.25
0~8°
0.45~0.75
0.018~0.030 ( 0.50 )
0.020
-5-
Rev. 1.1
Top View
10 9 8 7 6 5 4 3 2 1
A
N.C N.C N.C N.C
B
N.C N.C N.C
C /WP ALE Vss /CE /WE R/B
D NC /RE CLE NC NC NC
E NC NC NC NC NC NC
F NC NC NC NC NC NC
G NC NC NC NC NC NC
H NC I/O0 NC NC NC Vcc
-6-
Rev. 1.1
0.10 MAX
9.00±0.10
A
0.80 x 9= 7.20
#A1 INDEX MARK
3.60
0.80 0.40 B
9.00±0.10
10 9 8 7 6 5 4 3 2 1
A
#A1
B
C
(Datum B)
4.40
D
0.40
11.00±0.10
11.00±0.10
F
G
H
J
0.80
K
L
M
0.32±0.05
(Datum A)
0.90±0.10
63-∅0.45±0.05
∅ 0.2 M A B
-7-
Rev. 1.1
NOTE :
Connect all VCC and VSS pins of each device to common power supply outputs.
-8-
Rev. 1.1
VCC
VSS
Command
Command
Register
I/O Buffers & Latches VCC
VSS
CE Control Logic
RE & High Voltage I/0 0
WE Generator Global Buffers Output
Driver
I/0 7
CLE ALE WP
1 Block = 64 Pages
(128K + 4k) Byte
I/O 0 ~ I/O 7
Page Register
2K Bytes 64 Bytes
[Figure 2] K9F1G08U0D Array Organization
NOTE :
Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
-9-
Rev. 1.1
Caution :
Any undefined command inputs are prohibited except for above command set of Table 1.
- 10 -
Rev. 1.1
NOTE :
1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTE :
1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less
2) Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
- 11 -
Rev. 1.1
NOTE :
1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both
cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the
attached technical notes for appropriate management of invalid blocks.
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.
NOTE :
Capacitance is periodically sampled and not 100% tested.
NOTE :
1) X can be VIL or VIH.
2) WP should be biased to CMOS high or CMOS low for standby.
- 12 -
Rev. 1.1
NOTE :
1) Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature.
NOTE :
1) The transition of the corresponding control pins must occur only once while WE is held low
2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle
- 13 -
Rev. 1.1
NOTE :
1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5μs.
- 14 -
Rev. 1.1
Start
No
Last Block ?
Yes
End
- 15 -
Rev. 1.1
Start
Write 80h
Write Address
Write Data
Write 10h
I/O 6 = 1 ? No
or R/B = 1 ?
Yes
* No
I/O 0 = 0 ?
Yes
Program Completed
- 16 -
Rev. 1.1
Start Start
ECC Generation
I/O 6 = 1 ? No
or R/B = 1 ?
No
Yes Reclaim the Error Verify ECC
* No
Erase Error I/O 0 = 0 ? Yes
Erase Completed
Block Replacement
Block A
1st
{
∼
(n-1)th 1
nth an error occurs.
(page) Buffer memory of the controller.
Block B
1st
{
∼
2
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.
- 17 -
Rev. 1.1
: :
From the LSB page to MSB page Ex.) Random page program (Prohibition)
DATA IN: Data (1) Data (64) DATA IN: Data (1) Data (64)
- 18 -
Rev. 1.1
CLE
≈
CE don’t-care
CE
≈ ≈
≈
≈ ≈
WE
≈≈
ALE
≈
I/Ox 80h Address(4Cycles) Data Input Data Input 10h
tCS tCH
tCEA
CE CE
tREA
tWP
RE
WE
I/O0~7 out
CLE
≈
≈
CE don’t-care
CE
≈ ≈
≈ ≈
RE
≈
ALE
≈≈
≈
R/B t
≈
WE
≈
Address Information
I/O DATA ADDRESS
Device
I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2
K9F1G08U0D I/O 0 ~ I/O 7 ~2112byte A0~A7 A8~A11 A12~A19 A20~A27
- 19 -
Rev. 1.1
CLE
tCLS tCLH
tCS tCH
CE
tWP
WE
tALS tALH
ALE
tDS tDH
I/Ox Command
tCS
tWC tWC tWC
CE
ALE
tDH tDH tDH tDH
tDS tDS tDS tDS
- 20 -
Rev. 1.1
≈
tCH
CE
≈
tWC
ALE
≈
tALS
≈
tWP tWP tWP
WE
tWH
tDH
tDS tDH tDS tDS
tDH
≈
I/Ox DIN 0 DIN 1 DIN final
≈
CE tRC
≈
tCHZ
tREH
tREA tREA tREA tCOH
≈
RE
tRHZ tRHZ
tRHOH
≈
tRR
≈
R/B
NOTE :
Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
tRHOH starts to be valid when frequency is lower than 33MHz.
- 21 -
Rev. 1.1
tCS
CE
tCH
tWP
WE
tCEA tCHZ
tWHR tCOH
RE
- 22 -
Rev. 1.1
CLE
CE
tWC
WE
tCSD
tWB
tAR
ALE
tRHZ
tR tRC
RE
≈
tRR
≈ ≈
I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 30h Dout N Dout N+1 Dout M
R/B Busy
CLE
CE
WE tCSD
tWB
tCHZ
tAR tCOH
ALE
tR tRC
RE
tRR
I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 30h Dout N Dout N+1 Dout N+2
R/B
Busy
- 23 -
K9F1G08U0D
CLE
tCLR
4.7 Random Data Output In a Page
CE
WE
tWB
tWHR
tAR
ALE
- 24 -
tR tRC tREA
RE
datasheet
tRR
I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 30h Dout N Dout N+1 05h Col Add1 Col Add2 E0h Dout M Dout M+1
Column Address Row Address Column Address
R/B Busy
FLASH MEMORY
Rev. 1.1
Rev. 1.1
CLE
CE
tWC tWC tWC
≈
WE
tADL tWB tPROG
tWHR
ALE
RE
≈ ≈
Din Din
I/Ox 80h Co.l Add1 Col. Add2 Row Add1 Row Add2
N M
10h 70h I/O0
SerialData 1 up to m Byte Program Read Status
Column Address Row Address
Input Command Serial Input Command Command
R/B
≈
I/O0=0 Successful Program
m = 2112byte
I/O0=1 Error in Program
NOTE :
tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
- 25 -
K9F1G08U0D
CLE
CE
tWC tWC tWC
≈
≈
WE
tADL tADL tWB tPROG
tWHR
ALE
4.9 Page Program Operation with Random Data Input
- 26 -
RE
≈ ≈
≈ ≈
datasheet
R/B
≈
NOTE :
tADL iste time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
FLASH MEMORY
Rev. 1.1
K9F1G08U0D
CLE
CE
tWC
tWHR
WE tWB
tPROG
tWB
ALE
tR tRC
RE tADL
- 27 -
I/Ox 00h Col Add1 Col Add2 Row Add1 Row Add2 35h Data 1 Data N 85h Col Add1 Col Add2 Row Add1 Row Add2 Data 1 Data N 10h 70h I/Ox
≈ ≈
≈ ≈
4.10 Copy-Back Program Operation with Random Data Input
R/B
≈
≈
Busy Busy
I/O0=0 Successful Program
Copy-Back Data
I/O0=1 Error in Program
Input Command
NOTE :
tADL sthe time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
FLASH MEMORY
Rev. 1.1
Rev. 1.1
CE
tWC
WE
tWB tBERS
tWHR
ALE
RE
Row Address
R/B Busy
≈
Auto Block Erase Erase Command I/O0=0 Successful Erase
Setup Command Read Status I/O0=1 Error in Erase
Command
CLE
CE
WE
tAR
ALE
RE
tREA
I/Ox 00h ECh
Device 3rd cyc. 4th cyc. 5th cyc.
90h Code
Read ID Command Address 1cycle Maker Code Device Code
Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle
K9F1G08U0D F1h 00h 95h 40h
- 28 -
Rev. 1.1
3rd ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1 0 0
2 0 1
Internal Chip Number
4 1 0
8 1 1
2 Level Cell 0 0
4 Level Cell 0 1
Cell Type
8 Level Cell 1 0
16 Level Cell 1 1
1 0 0
Number of
2 0 1
Simultaneously
4 1 0
Programmed Pages
8 1 1
Interleave Program Not Support 0
Between multiple chips Support 1
Not Support 0
Cache Program
Support 1
4th ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1KB 0 0
Page Size 2KB 0 1
(w/o redundant area ) 4KB 1 0
8KB 1 1
64KB 0 0
Block Size 128KB 0 1
(w/o redundant area ) 256KB 1 0
512KB 1 1
Redundant Area Size 8 0
( byte/512byte) 16 1
x8 0
Organization
x16 1
50ns/30ns 0 0
25ns 1 0
Serial Access Minimum
Reserved 0 1
Reserved 1 1
- 29 -
Rev. 1.1
- 30 -
Rev. 1.1
CLE
≈
CE
≈
WE
≈≈
ALE
≈
R/B t
≈
RE
- 31 -
Rev. 1.1
R/B t
RE
Address Address
I/Ox 00h 4Cycles 30h Data Output 05h 2Cycles E0h Data Output
tPROG
R/B
"0"
I/Ox 80h Address & Data Input 10h 70h I/O0 Pass
- 32 -
Rev. 1.1
tPROG
R/B
"0"
I/Ox 80h Address & Data Input 85h Address & Data Input 10h 70h I/O0 Pass
tR tPROG
R/B
≈
"0"
I/Ox 00h Add.(4Cycles) 35h Data Output 85h Add.(4Cycles) 10h 70h I/O0 Pass
≈
Col. Add.1,2 & Row Add.1,2 Col. Add.1,2 & Row Add.1,2
"1"
Source Address Destination Address
Fail
NOTE :
Copy-Back Program operation is allowed only within the same memory plane.
[Figure 10] Page Copy-Back Program Operation
tPROG
tR
R/B
≈
I/Ox 00h Add.(4Cycles) 35h Data Output 85h Add.(4Cycles) Data 85h Add.(2Cycles) Data 10h 70h
≈
[Figure 11] Page Copy-Back Program Operation with Random Data Input
- 33 -
Rev. 1.1
tBERS
R/B
"0"
I/Ox 60h Address Input(2Cycle) D0h 70h I/O0 Pass
Fail
- 34 -
Rev. 1.1
CLE tCLR
tCEA
CE
WE
tAR
ALE
tWHR
RE
tREA Device
I/OX 90h 00h ECh Code 3rd Cyc. 4th Cyc. 5th Cyc.
Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle
K9F1G08U0D F1h 00h 95h 40h
5.7 Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or
erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high.
If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the
Reset command is written. Refer to Figure 14 below
tRST
R/B
I/OX FFh
- 35 -
Rev. 1.1
Rp
ibusy
VCC
CL
VOL
Busy
tf tr
GND
Device
Ibusy 200
200n 2m
tr,tf [s]
Ibusy [A]
150
1.2
100n 100 1m
0.8
tr
50 0.6
1K 2K 3K 4K
Rp(ohm)
Rp value guidance
- 36 -
Rev. 1.1
≈
~ 2.3V ~ 2.3V
VCC
High
≈
WP
≈
WE
Don’t care
≈ Operation
5 ms max
1ms
≈
Ready/Busy
- 37 -
Rev. 1.1
- 38 -