Microelectronics Journal

A Low-power Comparator with a Wide Input VCM Range

--Manuscript Draft--

Manuscript Number: MEJ-D-21-00494

Article Type: Research Paper

Keywords: Double-tail Comparator; Low-power Comparator; Control Circuit; ADC; Input VCM
Range; Low Offset

Abstract: In double tail dynamic comparators, the latch activation moment is variable and
governed by the circuit parameters as well as the input signals. Therefore, in normal
operation, the input referred offset voltage is deteriorated and power is consumed
more than needed. This moment cannot be adjusted at the best value for any given
input signals. In this paper, a controller is proposed to tackle the mentioned issue so
that the comparator operates in the optimum region all over the input Vcm range; using
the proposed controller, the comparator is aware of the input signals and produce the
best control signals. This way, the comparator adjusts itself to save power and offset
as much as possible. The proposed and conventional comparators were designed
similarly in 180nm technology. Simulations show the offset voltage is reduced by 15%
while the power consumption is decreased by 55%. The power is reduced to its
minimum value all over the range of the input Vcm.

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Procedia Analog Integrated circuit 00 (2012) 000–000

A Low-power Comparator with

a Wide Input VCM Range
Ata Khoramia, Roghayeh Saeidib
a
Department of Electrical Engineering, Sharif University of Technology, Azadi avenue, Tehran, Iran,
b
Leuven University, Leuven, Belgium

Abstract

In double tail dynamic comparators, the latch activation moment is variable and governed by the circuit
parameters as well as the input signals. Therefore, in normal operation, the input referred offset voltage
is deteriorated and power is consumed more than needed. This moment cannot be adjusted at the best
value for any given input signals. In this paper, a controller is proposed to tackle the mentioned issue so
that the comparator operates in the optimum region for a wide range of the input signals. In fact, using
the proposed controller, the comparator is aware of the input signals and produce the best control signals.
This way, the comparator adjusts itself to save power and offset as much as possible. As a result, the total
power consumption and the input referred offset voltage are reduced. To make a fair comparison, the
proposed and conventional comparators were designed for similar specs using 180nm CMOS technology.
Simulations show the offset voltage is reduced by 15% while the power consumption is decreased by
55%. The power is reduced to its minimum value all over the range of the input signals in contrast to other
comparators which are optimum at a certain condition and they waste power if that condition is not met.
Keywords: Double-tail Comparator; Low-power Comparator; Control Circuit; ADC; Input VCM Range; Low Offset;

1 Introduction:
Almost all of the Integrated Circuits (IC) such as the ones used in handheld devices and wearable electronics employ
mixed-mode circuits. In mixed-mode circuits conversion from an analog signal into a digital one is necessary which
is done through some kinds of comparison [1]. For example, in a brown-out detection circuit, comparison is required
to evaluate the level of the battery voltage and to make sure the level of the battery voltage is within the nominal or
standard range [2]. This comparison somehow digitizes the level of the supply voltage into one or more binary bits.
As another example, different types of Analog to Digital Converters (ADC) produce a binary code representing the
input analog signal. This is again done by comparison. For example, in a Single-Slope ADC the input signal is
compared to a ramp signal until the result of comparison appears to be inverted [3], or in a SAR ADC the comparison
is done until a pre-defined resolution is achieved [4]. Also, in other types of ADCs, the act of comparison so the
comparator circuits are essential. As a result, comparators are key components of mixed-mode circuits and they affect
the overall quality of them in terms of power consumption, precision, and speed. In recent applications, comparators
should be able to do comparison in a wide range of input common mode voltage (V CM). For example, in ultra-low-
power SAR ADCs which are promising candidates for future low-power applications, comparators usually should be
able to do the comparison in a wide input VCM range of 0.25Vdd-0.75Vdd [5-8]. Therefore, a comparator in modern
designs should be able to successfully operate in a wide range of the input VCM. The following presents recent advances
in the design of low-power comparators.
Few decades ago, high-gain OpAmps were employed to compare input signals. This way it was possible to compare
two input signals whose difference was very small. OpAmps had stability issues and design complexities (e.g.,
common-mode feedback or biasing) and for a large gain their delay was large. Moreover, OpAmps consume a lot of
static power which was not acceptable in modern applications such as portable devices. That’s why later dynamic
comparators were proposed [9]. In those circuits, a circuit similar to a latch and an amplifier are initialized then the
input signals are amplified to a fairly larger value in the amplifier; next, the amplified signal is given to the latch so
that it will be amplified to Vdd at one side and to Vss at the other side using the positive feedback of the latch. Both
the amplifier and the latch are dynamic meaning that in the steady-state there is no path from Vdd to Vss; so, they do
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Procedia Analog Integrated circuit 00 (2012) 000–000

not consume static power. Compared to OpAmps, dynamic comparators consume less power and area while they are
faster and do not need stability measures. Fig. 1 presents one of the first versions of dynamic comparators which is
called single tail comparator [9]. In this circuit, when clk=”0” the circuit is initialized and when clk=”1” the circuit
does the comparison until one output becomes Vdd while the other become Vss. In the right side of the figure, it is
seen that at the end of the comparison, there is no direct path from Vdd to Vss so no static power is consumed. The
circuit of Fig. 1 suffers from a large kickback noise which is the leakage of the large output swing into the input nodes
through parasitic gate-drain capacitors [10]. Kickback noise is an issue since in the applications where
capacitors are connected to the comparator input nodes, kickback noise disrupts the stored voltage and cause an error.
Later, double-tail comparators were proposed in which the pre-amplifier and the latch are separated to weaken this
effect.
Vdd Vdd Vdd Vdd

clk clk on
M6 M7 M8 M9 off off off
Example of
out- out+ end of comparison

M4 M5 on off
Vin+>Vin-
Vin+ Vin- x+1mV x-1mV
M2 M3

clk M1 on

Fig. 1 single tail comparator, the first dynamic comparators [9].

Fig. 2 presents two of the commonly used double tail comparators [11-16]. In both of the circuits, the first stage is
the preamplifier and the second stage is the latch. The preamplifier amplifies the input differential voltage and when
the latch is turned on, it finishes the comparison employing a positive feedback. In the circuits of Fig. 2, the large
output swing of the latch is leaked into the comparator internal nodes through a longer path of parasitic capacitors.
Moreover, the parasitic capacitors of the latch is much smaller than that in the preamplifier. As a result, the double
tail structures has less kickback noise and this is why they are more common these days compared to single tail
comparators. Especially in ADC design, double tail comparators are preferred [16-19].
Pre_Amplifier Pre_Amplifier

Vdd Vdd Vdd Vdd

clk clk

Dynamic Latch Dynamic Latch

Vdd Vdd Vdd
clkn
O1- O1+

Out- Out+
Out- Out+ clkn clkn
O1- O1+
Vin+ Vin- Vin+ Vin-

clk clk

Fig. 2 Two of the commonly used double tail comparators [11-16].

About double-tail comparators, several studies have been performed to reduce their power consumption, offset
voltage, and comparison delay. The following presents some of the recently proposed methods with the emphasis on
power reduction.
Calibration can be considered as a low-power method. In order to reduce the offset voltage sizing should be
increased which results in larger parasitic capacitors so a higher power consumption. However, using calibration, for
a given precision smaller sizing can be used which results in a lower power consumption. Although calibration could
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Procedia Analog Integrated circuit 00 (2012) 000–000

result in power reduction, it requires additional circuits and usually a much larger area (for calibration circuits and
capacitors) which reduce its low-power benefits and increase design complexities. Moreover, calibration routines
reduce the operating frequency. For example, the comparator presented in [14] reduces the offset voltage to some tens
of micro volts, however, it considerably increases the area and complexity and reduces the operating frequency to
MHz range. In modern designs, these complexities and drawbacks limit the usage of calibration to high precision
circuits where other methods are not able to satisfy the design requirements. Swing reduction is another technique to
reduce the amount of charging/discharging parasitic capacitors so the power consumption. This was firstly proposed
in [19] using an additional supply voltage. That method is very effective in power reduction and speed enhancement,
however, it increases the offset voltage and for maximum power reduction an additional supply voltage is required.
The comparators with control circuits can also be categorized as the swing reduction methods [20-22]. In such circuits,
the timing of the preamplifier and the latch are produced wisely to achieve the minimum power, offset voltage, and
comparison delay. The mentioned time management will result in swing reduction to its minimum value and this is
how the comparators with control circuits reduce the power consumption. These methods are very effective in power
reduction (40% power reduction is achievable) although their behavior is optimum only for a given fixed value of the
input VCM. For other values of the input VCM they usually offer a lower power compared to the conventional
comparator but they diverge from the optimum condition so their power reduction benefits degrades. Ideally if the
comparator is optimum all over the input VCM range a considerable more power reduction is achieved. Unfortunately,
the comparators with control circuits though power efficient are not able to produce optimum timing signals all over
the input VCM range. This is an issue we are going to solve in this paper in order to achieve a better power reduction.
Designing control circuits has its own difficulties and drawbacks and this is why in some researches it is tried to
control the comparator in a power efficient manner without any controller [23-25]. In fact, those comparators use the
internal signals of the comparator to decide when preamplifier/latch should be on or off. For example, the techniques
proposed in [23, 24] use the latch outputs to prevent the preamplifier from excess power consumption; or in the
comparator presented in [25], the preamplifier outputs are used to reduce the power of the preamplifier itself.
Employing the mentioned techniques results in a significant power reduction but not as good as the methods employing
controllers. Moreover, they are not able to considerably improve the speed and offset voltage. As a result, for an
overall better operation it is recommended to use the comparators with controllers. They are more complex and require
more time to design but they offer a better power and offset reduction as well as speed enhancement. The latest low-
power technique which is becoming popular these days is employing low supply voltages [26-28]. The value of the
supply voltage affects the power consumption almost with a power of three. Therefore, decreasing the supply voltage
considerably decreases the power consumption. Although these low supply voltage comparators are very effective in
power reduction, they suffer from a large variability. In fact, the lower the supply voltage is the higher the comparator
offset voltage will be which is not acceptable in many modern applications such as ADCs. Moreover, obviously the
maximum clock frequency of a comparator working in a lower supply voltage is much lower than that working in a
nominal supply voltage. These mentioned issues have become barriers against low voltage designs and limit the usage
of low-voltage comparators in bigger designs such as ADCs. Therefore, there are few studies which have been able to
propose a complete system operating at a small supply voltage.

As discussed, recent studies show the comparators employing control circuit are able to significantly improve the
specs of a comparator. Unfortunately, their benefits are limited to a small range of the input V CM of the comparator.
Therefore, they are not applicable to nowadays low-power applications such as ADCs. In this paper, the goal is to
solve this issue. In fact, we are going to present a comparator with an efficient controller which is able to operate
optimally almost all over the input VCM range. In modern designs, the required VCM range is 0.25Vdd-0.75Vdd so the
comparator should be able to reduce the power optimally all over that range. The proposed comparator is able to
reduce the power to the maximum possible value for any VCM value in the mentioned range.
In Section II, first the operation of double-tail comparators is discussed. Then, it is shown why that circuit is not
efficient. Next, it is explained how an external controller can help alleviate the issue although that technique is not
efficient in a wide range of the input VCM. In Section III, the proposed method is presented then its circuit
implementation is explained in detail. Section IV presents the simulation results and comparison to other comparators.
Section V concludes the paper.

2 Double-tail Comparators and Their Design Challenges

Fig. 3(a) presents a common version of double tail comparators [14, 18, 21, 22]. In this circuit while clk=”1” the
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Procedia Analog Integrated circuit 00 (2012) 000–000

comparator is reset, namely the outputs of the preamplifier are set to “0” while the latch outputs are set to “1”. When
clk makes a “1” to “0” transition, the tail transistor (M5 in Fig. 3(a)) is turned on so the preamplifier starts its operation.
During this time, the preamplifier output nodes are charged gradually and their difference grows (the red figure in Fig.
3(b)). When the preamplifier output nodes are charged to the threshold voltage of the latch stage input transistors, the
latch is turned on and finishes the comparison. In fact, the latch amplifies its small input differential voltage to Vdd
and Vss. Fig. 3(b) presents typical output waveforms of this comparator. This figure shows both the reset and
evaluation phases. As seen, during the evaluation phase, the preamplifier outputs are charged toward Vdd and a
differential voltage is created between them. A magnified version of the differential voltage is shown in red in Fig.
3(b).
Vdd
clk 2.5
M5
Out+
Out-
O1+
Vin+ Vin- 2 O1-
M4 A×Vdiff
M3
O1- Pre-amplifier O1+ 1.5

Voltage (V)
clk
M1 M2
1
Vdd
0.5
O1+
clkn Latch clkn
M6 M8 M9 M7 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Out- Out+ Time (ns)
M10 M11 clk : Reset phase Evaluation phase
M12 M13

(a) (b)
Fig. 3 (a) A commonly used version of DTDC [14, 18, 21, 22], (b) Typical output waveforms of this comparator.

Fig. 3(b) shows some drawbacks of the double-tail comparators which are explained as follows. First, the
preamplifier output nodes are charged continuously until they reach Vdd. In fact, they keep being charged so wasting
power even after the comparison is done. Second, the latch activation moment is out of control. In fact, the latch is
activated when its input nodes (preamplifier output nodes) are charged to V th of the latch input transistors. Ideally, the
latch should be activated right after the preamplifier output differential voltage is large enough to eliminate the latch
offset effect on the input referred offset voltage. In other word, for an ideal operation latch should be activated earlier
and finishes the comparison faster. This way power is saved and the comparison delay is reduced. Unfortunately, the
circuit of Fig. 3(a) does not allow this, since at a moment earlier than the latch activation moment of Fig. 3(b), the
overdrive voltage of the latch input transistors is not large enough so the latch cannot operate properly. As a result, it
is preferred to change the structure of Fig. 3(a) circuit in a way that the preamplifier can be turned off when its output
differential voltage is large enough, and the latch can be activated at any moment. One way which is firstly proposed
in [21], is to use a P-type latch (instead of an N-type latch) in addition to an external controller whose delay is set to
the minimum required time for the preamplifier to create the favorable output differential voltage and applies that to
the latch. Fig. 4 presents the comparator presented in [21]. Explaining the detail and all of the features of this
comparator such as the cross-coupled circuit is out of the length of this paper and enthusiastic readers may refer to
[21] for further explanations. The point in this comparator is that it requires an external controller to turn off/on the
preamplifier and the latch. In fact, first, it turns on the preamplifier while the latch is off. Then, when enough
differential gain is achieved at the preamplifier outputs, the preamplifier is turned off to prevent more power
consumption, and simultaneously the latch is turned on to finish the comparison. In this comparator, all the produced
delays in the control waveforms are fixed and they are designed for the worst case which is when the tail current is
minimum, namely VCM=1.35. This design methodology has to be obeyed to make sure that always there is enough
differential gain at the latch input nodes to eliminate the effect of the latch offset. As a result of this design
methodology, the comparator operation is optimum at VCM=1.35V although for different values of VCM the comparator
operation diverges from the optimum value. In other word, for any value of the input VCM voltage, there is an optimum
timing which results in the best power reduction, speed, and offset voltage; but this comparator is not able to always
operate in the optimum region since the timing of the control circuit is fixed. For example, in the circuit of Fig. 4 if
the input VCM=0.45V, as shown in Fig. 5 the tail current is much higher compared to VCM=1.35V so during the long
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Procedia Analog Integrated circuit 00 (2012) 000–000

preamplification delay (which has been designed for V CM=1.35V) a large amount of power is wasted since the
controller turn off the preamplifier with a large delay. Moreover, the offset voltage cannot be acceptable all over the
VCM range since for lower VCM’s the preamplifier output differential voltage is lower when the latch is activated. If it
was possible to always work in the optimum region more power reduction and less offset voltage could be achieved.
The comparators reported in [20, 22, 29] are some other comparators employing external controllers to efficiently
control the comparator. However, similarly they are controlled using fixed control signals, therefore, they are not able
to operate optimally in all range of the input VCM. With a better design more power reduction is achievable.

Vdd Vdd
clkb1 M8 clkb2 M17

Vin+ M7
Vin- M15 M16
M6
O1- O1+
M13 M14
O1- O1+
Out- Out+
clk M9 M10 M11 M12
clk
M4 M5

Vdd
M3
PMOS latch
clk :
M1
clk M2 clkb1 :
clkb2 :
Inv :

Fig. 4 The comparator proposed in [21].

800

700

600

500
Current (uA)

400

300

200

100

0
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
Vcm (V)

Fig. 5 The tail current versus input VCM in a Fig. 3 comparator.

3 The Proposed Comparator

The authors of this paper believe the key point to solve the explained issue is that the external controller must sense
the input signals and produce optimal control signals proportionally. In this way, the comparator is able to always
work in the optimum region so maximum power efficiency is achieved. Fig. 6 presents the proposed comparator. As
seen, in this comparator, the controller senses the input voltage to create optimum control signals proportionally. As
a result, the comparator is able to work optimally regardless of the value of the input signals.
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Procedia Analog Integrated circuit 00 (2012) 000–000

Vdd
clkb Vdd
M5 Vdd Vdd
Vin+ Vin- M21
M18 Vin+ Vin- Vin+ M33 Vin-
Vin+ Vin- M28 M29 M34
M3 M4

O1- Pre-amplifier O1+ clk clkn

M17 M24 x M27 x M32
clk
M1 M2
Vdd Vdd
Vdd Vdd Vdd
M16 M20
clkb Latch clkb clkn M26 M31
M6 M8 M9 M7 M23 clkb
clk x
Out- Out+ M15 M19 x M22 M25 M30
M10 M11

M12 M13
clkn=not of clk
clk : Reset phase Evaluation phase
clkb M14
PW
clkb :

(a) (b)
Fig. 6 (a) The proposed comparator, (b) the proposed control circuit.

Before the functionality of the circuit shown in Fig. 6 is explained, it is essential to know how much delay is required
and how that value changes over the range of the input V CM. In the proposed design methodology, preamplification
delay is set to the value which results in the maximum value of the preamplifier output differential voltage. Based on
Fig. 3(b), the preamplifier output differential voltage has a maximum before it goes down. In the proposed method that
maximum value is favorable and the preamplification delay (the pulse width, PW, in Fig. 6(b)) should be set on that
value. This is the best decision and it optimizes the power consumption and offset voltage. Simulations showed the
preamplification delay which results in the maximum differential voltage is as Fig. 7(a). Fig. 7(a) shows a higher
amount of delay is required for larger VCM voltages; this result is expected, since for larger V CM’s the tail current is
smaller so a longer time is required for the preamplifier to create the maximum differential voltage. The delay for the
maximum differential voltage changes from about 200ps to 8 ns. Therefore, the range of the delay is large and a special
control circuit should be proposed to cover all the range.
Fig. 7(b) shows typical waveforms of the proposed comparator (the black lines) working with the optimum
preamplification delay versus the conventional comparator (the blue lines) working normally. As seen, when the
differential voltage reaches its maximum value, the preamplifier is turned off saving power while the latch is tuned on
to finishes the comparison. During the latching process, the preamplifier output differential voltage remains almost
constant in contrast to the conventional comparator where a lower differential voltage is applied to the latch during
the latching process; As a result, a lower offset voltage is expected from the proposed comparator. This is confirmed
in the simulation results. The benefit of the proposed comparator versus the others employing external controllers
([20, 22, 29]) is that it is able to always produce optimum delay for any given value of the input V CM. Therefore, in
contrast to the other comparators, all over the VCM range saves power as much as possible so the average power
consumption of the proposed comparator is considerably better than the others.
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Procedia Analog Integrated circuit 00 (2012) 000–000

Delay versus Vcm

10

Delay (ns)
6
(a)
4

0
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
Vcm (V)
2.5
Conventional

Voltage (V)
2 Proposed

1.5

1
(b) 0.5

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ns)
clk : Reset phase Evaluation phase
clkb :

Fig. 7 (a) Preamplification delay for maximum differential voltage, (b) typical output waveforms with that delay.

In this part, the proposed controller is explained in detail to see how it is able to produce the required delay shown
in Fig. 7(a). First, we start from a small part of the proposed controller, then we grow that circuit step by step until
we come up with the whole controller. Fig. 8(a) presents the core idea of the proposed controller. In this circuit, when
clkn makes a “0” → "1" transition, clkb goes to “0” and remains at “0” until x is discharged to “0” and clkb comes
back to “1”. As a result, the circuit of Fig. 8(a) produces a “0” pulse whose width is equivalent to the delay of the first
two inverters. Obviously the delay of Fig. 8(a) circuit is constant regardless of the value of the comparator input
signals (Vin+, Vin). The two inverters at the end are used to sharpen the output signal (clkb) and to avoid the loading
effect of the tail transistor (which is rather large) on the controller.

The circuit presented in Fig. 8(a) was modified to the circuit of Fig. 8(b) to include the effect of the input signals.
The added circuit is highlighted with a dashed rectangle. In the modified circuit, the added branch reduces the pulse
width over the input VCM range of the comparator. Pulse width is reduced more for a lower VCM, since more current
is injected to output of the inverter so node x is discharged faster. In fact, the delay of the first two inverters which is
equivalent to the pulse width is reduced. The pulse width figure versus the input V CM originated from Fig. 8(b) circuit
is not good enough to produce the pulse width pattern of Fig. 7(a) because of its wrong curvature. Therefore, Fig. 7(c)
is proposed to produce a more accurate pulse width. In this circuit, Vin+ and Vin- affect the charging current of M27.
In this way, for larger values of the input VCM the current of M27 is significantly reduced and the pulse width is
increased exponentially. Using the circuit of Fig. 8(c) the curvature of the pulse width figure becomes consistent to
that in Fig. 7(a). However, still one problem exists and that is very large pulse width for larger V CM values. In other
word, for a large VCM the pulse width is very larger than what is needed based on Fig. 7(a). Moreover, as explained
in the simulation section, not only for larger V CM values the pulse width should not be larger than the figure of Fig.
7(a) but also it is preferred to be considerably lower than that. As a conclusion, the circuit of Fig. 8(d) is proposed
which is able to accurately produce the pulse width of Fig. 8(d). In this circuit, an NMOS pair is added (M33, M34)
which injects a large amount of current for larger values of the comparator input signals. As seen in the pulse width
figure, the controller of Fig. 8(d) is able to create the desired figure.
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Procedia Analog Integrated circuit 00 (2012) 000–000

Vdd Vdd
Vdd Vdd Vdd Vdd
Vin+ Vin- M21
M18
clkn x M27 clkn x
M24 M24 M27
Vdd Vdd
clk M17
M16 M20

x Vdd Vdd Vdd Vdd Vdd Vdd

clk
clkn M26 M31 M26 M31
M16 M20 clkn
M15 M19 M23 M23
clkb clkb
clk x
x M22 x M22
M25 M30 M25 M30
M15 M19

Pulse width (s)

Pulse width (s)

Previous

Vcm (V)
Vcm (V)

(a) (b)
Vdd
Vdd Vdd Vdd Vdd
Vdd Vdd Vin+ Vin- M21 Vin+ Vin- M21
M18 M18 Vin+ Vin- Vin+ M33 Vin-
Vin+ Vin- M21 M28 M29 M34
M18 Vdd

clkn x clk clkn

M24 M27 M17 M24 x M27 x M32
clk M17
Vdd Vdd
Vdd Vdd Vdd Vdd
M16 M20 Vdd Vdd
M16 M20 clkn M26 M31
M23 clk x clkn M26 M31
x clkb M23
clk clkb
x M22 M15 M19
M25 M30 x M22
M15 M19
M25 M30

Pulse width (s)

Pulse width (s)

Vcm (V) Vcm (V)

(c) (d)

Fig. 8 (a,b,c,d) The proposed controller and its delay versus VCM when more of its parts are added.

In the controller of Fig. 8(d), the sizing of the left hand side inverters (M 15-16, M19-20) is determined to set the
average value of the delay. Next, the size of the transistor pairs which are connected to Vin+ and Vin- signals are
designed to fit the pulse width figure of the clkb signal to Fig. 7(a) figure. Therefore, the controller will be able to
produce the optimum pulse width considering any value of the input V CM.

4 Simulations and Comparison

Comparators have both analog and digital characteristics. In order to test the proposed method and see how much it is
effective in power reduction, the proposed and conventional comparators were designed for the same clock frequency
of 50MHz and offset voltage of about 3mV. During the design, the goal was to minimize the power consumption and
meet the speed criterion for the VCM range of 0.25Vdd-0.75Vdd which is a commonly used range in many applications.
The proposed controller was designed to produce the required pulse width all over the V CM range. Fig. 9(a) shows the
pulse width of the proposed controller along with the optimum pulse width.
In Fig. 9(a), it is visible that for large VCM values the delay of the proposed controller is intentionally much lower
than the optimum value which gives us the maximum preamplifier output differential voltage. For larger values of
VCM, the preamplifier output differential voltage is generally larger so it is not essential for the preamplifier to wait
until maximum differential gain is achieved. In fact, even before the peak of the differential signal, the gain is larger
than its minimum value (so it is enough) which happens for V CM=0.45. Fig. 9(b), shows the maximum differential
voltage of the proposed and conventional comparators. This figure shows in the proposed comparator always enough
differential voltage is applied to the latch. For higher values of V CM the differential voltage of the proposed method is
smaller but it is large enough to guarantee the input referred offset voltage of the comparator over the whole V CM
range. As an advantage, this pulse width reduction for larger V CM voltages results in a lower power waste in the
preamplifier. Moreover, the controller can be designed more power efficient, since a lower delay requires a smaller
sizing which results in a lower power consumption. As a conclusion, it is power beneficial to reduce the optimum
pulse width for large VCM values, and this reduction has no effect on the worst case offset voltage.
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Procedia Analog Integrated circuit 00 (2012) 000–000

Delay versus Vcm, Vid=10mV

10
Conventional
Proposed
8

Pulse width(s)
6

(a) 4

0
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
Vcm (V)

Peak of Vdiff versus Vcm, Vid=10mV

220
Conventional
200 Proposed

180
Vid (mV)

160

(b) 140

120

100

80
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

Vcm (V)

Fig. 9 (a) The pulse width of the maximum differential gain and the proposed controller versus V CM, (b) the maximum differential voltage of
the proposed and conventional comparators.

Fig. 10 presents total power consumption of the proposed (including the controller) and conventional comparators.
The proposed comparator is able to significantly reduce the power consumption all over the range of the input VCM.
For small VCM values, power reduction is more recognizable (3.5x V.S. 1.5x) since the tail current is very large and
the proposed method prevents any power waste. The average power consumption is reduced from 29uW to 13uW
which is about 55% power reduction. The considerable amount of power reduction is a result of self-adjustability of
the proposed comparator. Fig. 11 presents the input referred offset voltage of the proposed and conventional
comparators. This figure also shows 0.85 offset voltage of the conventional comparator. The figure shows the proposed
method is able to reduce the offset voltage by 15%. In the proposed comparator, the latch starts working at the right
moment with high input differential voltage which eliminates its effect on the input referred offset voltage. In the
conventional comparator, usually before the maximum differential gain is formed the latch starts to work and finishes
the comparison. Therefore, a lower differential voltage is applied to the latch. In the conventional comparator, in order
to reduce the offset voltage by about 15% a rather big size increase is needed, however, the proposed method reduces
the offset voltage and power consumption together.
 Available online at www.sciencedirect.com

Procedia Analog Integrated circuit 00 (2012) 000–000

Delay-Vcm-Vid-constant-Vid=10mV
40
Conventional
35 Proposed

30

Power (uW)
25

20

15

10
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
Vcm (V)

Fig. 10 Total power consumption of the proposed and conventional comparators.

Delay-Vcm-Vid-constant-Vid=10mV
3.8
Conventional
3.6 Proposed
0.85*Conventional
3.4
(mV)

3.2

2.8

2.6
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
Vcm (V)

Fig. 11 Offset voltage of the proposed and conventional comparators.

Table I presents a comparison between the proposed and some other comparators. The power consumption of the
proposed comparator is the lowest value even if the power of all comparators are scaled down with respect to their
operating frequency, technology, and supply voltage. This shows that the proposed comparator is able to reduce the
power consumption all over the range of VCM to the minimum possible value. This is a unique feature of the proposed
comparator compared to the comparators employing external controllers. About the input V CM range, the proposed
comparator is among few circuits which are able to work in the whole range of 0.25Vdd-0.75Vdd and has an
acceptable offset voltage in the range. There are other comparators which are able to operate in a wide input V CM
range but they have very large offset voltages in V CM voltages other than 0.5Vdd. In fact, in those papers the offset
voltage is studied and reported only at 0.5Vdd.
Based on Table I, the proposed comparator is a low-power candidate with an acceptable offset voltage. This
comparator is able to significantly reduce the power over the common full range of the input VCM. As a result, the
proposed comparator is a low-power candidate suitable for precise applications where a VCM range of 0.25Vdd-
0.75Vdd is needed.

TABLE I COMPARISON BETWEEN THE COMPARATORS

VCM range Freq Vdd (V) Tech Offset (mV) Power (uW)
This 0-
50 MHz 1.8 180nm 2.9* 13
Paper 0.75Vdd
[14] - 100 kHz 5.0 0.5 µm 0.056** 766
[19] 0 - Vdd 0.5 GHz 1.8 180 nm 2.5 420
[28] 0.33Vdd -Vdd 1.8 GHz 1.2 65 nm 5.8 252
[21] 0 - Vdd 0.5 GHz 1.8 180 nm 2 230
[30] 0.42Vdd -Vdd 1 GHz 1.2 90 nm 5.62** -
[20] 0.27Vdd -Vdd - 1.2 130 nm 7.78 600
[29] - 0.9 GHz 1.0 90 nm 16.5 51
Conv (Fig. 3) 0 -0.75Vdd 50 MHz 1.8 180 nm 3.4* 28.9
* These values are the offset voltage over the operating input V CM range of the comparator in contrast to the others which are reported at a certain V CM.
** These values are from chip measurements while the other results in this table are result of simulations.
 Available online at www.sciencedirect.com

Procedia Analog Integrated circuit 00 (2012) 000–000

5 Conclusion
This paper introduces a low-power method which is capable of power reduction to its maximum possible value all
over the common range of the input VCM. A controller is proposed which is able to create optimum pulse width to
control the preamplifier regarding any value of the input VCM. Using this method, not only the power is reduced
significantly but also the offset voltage is reduced since maximum differential voltage is applied to the latch when it
is activated. This is in contrast to the conventional comparator where the latch is activated when its input differential
voltage is not maximum yet. The key core of the proposed comparator is the proposed controller. By appropriate sizing
the proposed controller is able to create exactly proper pulse width for any value in the input VCM range. The proposed
comparator is a promising candidate for future ultra-low-power applications and it is able to satisfy the requirements
of modern designs such as wide input VCM range and high comparison accuracy all over the range.

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