UNIT - III

PERIPHERAL INTERFACING

Architecture and interfacing: 8255 - 8259 - 8253 - 8251 - A/D and D/A
converters - Interfacing with 8085.

3.1 Programmable peripheral interface (8255)

The parallel input-output port 8255 is also called as programmable peripheral
input- output port.
Features of 8255
1. The 8255A is a widely used, programmable, parallel I/O device.
2. It can be programmed to transfer data under various conditions, from simple I/O to
interrupt I/O.
3. It is compatible with all Intel and most other microprocessors.
4. It is completely TTL compatible.
5. It has three 8-bit ports : Port A, Port B, and Port C, which are arranged in two
groups of 12 pins. Each port has an unique address, and data can be read from or
written to a port. In addition to the address assigned to the three ports, another
address is assigned to the control register into which control words are written for
programming the 8255 to operate in various modes.
6. Its bit set/reset mode allows setting and resetting of individual bits of Port C.
7. The 8255 can operate in 3 I/O modes: (i) Mode 0, (ii) Mode 1, & (iii) Mode 2.
a) In Mode 0, Port A and Port B can be configured as simple 8-bit input or output
ports without handshaking. The two halves of Port C can be programmed separately
as 4-bit input or output ports.
b) In Mode 1, two groups each of 12 pins are formed. Group A consists of Port A
and the upper half of Port C while Group B consists of Port B and the lower half of
Port C. Ports A and B can be programmed as 8-bit Input or Output ports with three
lines of Port C in each group used for handshaking.
8. In Mode 2, only Port A can be used as a bidirectional port. The handshaking
signals are provided on five lines of Port C (PC3 – PC7 ). Port B can be used in Mode
0 or in Mode 1.
8. All I/O pins of 8255 has 2.5 mA DC driving capacity (i.e. sourcing current of 2.5
mA).

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Pin diagram of 8255

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Architecture of 8255

Data Bus Buffer:

This tri-state bi-directional buffer is used to interface the internal data bus of
8255 Pin Diagram to the system data bus. Input or Output instructions executed by
the CPU either Read data from, or Write data into the buffer. Output data from the
CPU to the ports or control register, and input data to the CPU from the ports or
status register are all passed through the buffer.
Control Logic:
The control logic block accepts control bus signals as well as inputs from the
address bus, and issues commands to the individual group control blocks (Group A
control and Group B control). It issues appropriate enabling signals to access the
required data/control words or status word.

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Group A and Group B Controls:
Each of the Group A and Group B control blocks receives control words from
the CPU and issues appropriate commands to the ports associated with it. The
Group A control block controls Port A and PC 7-PC4 while the Group B control block
controls Port B and PC3-PC0.
Port A :
This has an 8-bit latched and buffered output and an 8-bit input latch. It can
be programmed in three modes: mode 0, mode 1 and mode 2.
Port B :
This has an 8-bit data I/O latch/ buffer and an 8-bit data input buffer. It can be
programmed in mode 0 and mode 1.
Port C :
This has one 8-bit unlatched input buffer and an 8-bit output latch/buffer. Port
C can be splitted into two parts and each can be used as control signals for ports A
and B in the handshake mode. It can be programmed for bit set/reset operation.

Operating modes of 8085

8255 has two modes of operation. They are as follows:
I/O mode: The I/ O mode is sub-classified into 3 modes.
I/O modes:
Mode 0: Simple I/O mode
In this mode all the three ports (port A, B, C) can work as simple input
function or simple output function.
 It does not support handshaking or interrupt capability.
 The input ports are buffered while outputs are latched.

Mode 1: Handshake I/O mode or strobed I/O mode

 Ports A and B function as 8 bit I/O ports. They can be configured either as
input or output ports.
 Each port uses three lines from Port C as handshake signals. The
remaining two lines of Port C can be used for simple I/O functions.
 Input and output data are latched
 Interrupt logic is supported

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 Handshaking signals are used to transfer data between devices whose data
transfer is not same.

Example: A CPU wants to transfer data to a printer. In this case since speed of
processor is very fast as compared to relatively slow printer, so before actual data
transfer it will send handshake signals to the printer for synchronization of the
speed of the CPU and the peripherals.

Mode 2: Bidirectional I/O data transfer

This mode allows bidirectional data transfer (transmission and reception) over
a single 8 bit data using handshake signals. This feature is available only in Group A
with Port A as the bidirectional data bus and PC 3 - PC7 are used for handshaking
purpose. The remaining lines of Port C PC0 – PC2 can be used for simple I/O
functions. The port B can be programmed in mode 0 or mode 1. When port B is
programmed in mode 1, PC0 – PC2 lines of port C are used as handshaking signals.

In this mode, both inputs and outputs are latched

Bit Set-Reset mode:
In this mode only port b can be used (as an output port). Each line of port C
(PC0 - PC7) can be set/reset by suitably loading the command word register. No
effect occurs in input-output mode. The individual bits of port c can be set or reset by
sending the signal OUT instruction to the control register.

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Control word formats of 8255
A high on the RESET pin causes all 24 lines of the three 8-bit ports to be in
the input mode. All flip-flops are cleared and the interrupts are reset. This condition is
maintained even after the RESET goes low. The ports of the 8255 Pin Diagram can
then be programmed for any other mode by writing a single control word into the
control register, when required.
I/O mode:

Bit set/reset mode:

The eight possible combinations of the states of bits D 3 – D1 (B2 B1 B0) in the
Bit Set-Reset format (BSR) determine particular bit in PC 0 – PC7 being set or reset
as per the status of bit D0. A BSR word is to be written for each bit that is to be set or
reset. For example, if bit PC3 is to be set and bit PC4 is to be reset, the appropriate
BSR words that will have to be loaded into the control register will be, 0XXX0111
and 0XXX1000, respectively, where x is don’t care.
The BSR word can also be used for enabling or disabling interrupt signals
generated by Port C when the 8255 Pin Diagram is programmed for Mode 1 or 2
operation. This is done by setting or resetting the associated bits of the interrupts.

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8255 programming and operation
Programming in Mode 0
The Ports A, B and C can be configured as simple input or output ports by
writing the appropriate control word in the control word register. In the control word,
D7 is set to ‘1’ (to define a mode set operation) and D 6, D5 and D2 are all set to ‘0’ to
configure all the ports in Mode 0 operation The status of bits D 4, D3, D1 and D0 then
determine whether the corresponding ports are to be configured as Input or Output.
For example in mode 0, if Port A and Port B are to operate as output ports
with Port C lower as input, and Port C upper as output, the control word that will
have to be loaded into the control register will be as follows.

This mode provides simple input and output operations for each of the three
ports. No handshaking is required; data is simply written to or read from a specified
port.
Input Mode

After initialization of 8255 Programming and Operation in the input mode 0,

CPU can read data through the input port by initiating read command with proper
port address. Read command activates RD signal. Upon activation of RD signal CPU
reads the data from the selected input port into the CPU register.
Output Mode

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 After initialization of 8255 in the output mode 0, CPU can write data into the
output port by initiating write command with proper port address. CPU sends data on
the data bus and upon activation of WR signal, data on the data bus gets latched on
the selected output port.
Mode 0 configurations

Programming in Mode 1 (Input / Output with Handshake):

Both Group A and Group B can operate in Mode 1, either together, or
individually, with each port containing an 8-bit latched Input or Output data port, and
a 4-bit port which is used for control and status of the 8-bit port.
When Port A is to be programmed as an input port, PC 3 , PC4 and PC5 are
used for control. PC6 and PC7 are not used and can be Input or Output, as
programmed by bit D3 of the control word. When Port A is programmed as an output
port, PC3 , PC6, and PC7 are used for control and PC4 and PC5 can be Input or
Output, as programmed by bit D3, of the control word.
When port B is to be programmed as an input or output port, PC0 , PC1 and
PC2 are used for control.
Mode 1 Input Control Signals:
STB (Strobe Input) :
This is an active low input signal for 8255 Programming and Operation and
output signal for the input device. The input device activates this signal to indicate
CPU that the data to be read is already sent on the port lines of 8255 port. Upon

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activation of this signal 8255 loads the data from the input port lines into the input
buffer of that port.
IBF (Input Buffer Full) :
This is an active high output signal for 8255 and an input signal for input
device. This signal is generated by 8255 Programming and Operation in response to
STB signal as an acknowledgment to input device. It also indicates to the input
device that the input buffer is full and it is not ready to accept next byte from the input
device. Therefore input device sends data on the port lines only when IBF signal is
not active. The IBF signal is deactivated when CPU reads the data from input buffer
of the respective port by activation of RD signal.
INTR (Interrupt Request) :
This is an active high output signal generated by 8255. A ‘high’ on this output
can be used to interrupt the CPU when an input device is requesting service. The
8255 Programming and Operation sets the INTR when STB signal is ‘one’, IBF
signal is ‘one’ and INTE is ‘one’, indicating CPU that the data from the input device is
available in the input buffer. This signal is reset by the falling edge of the RD signal
i.e. immediately after reading the data from the input buffer.
INTE (Interrupt Enable) flip flop is used to enable or disable INTR (Interrupt
request) signal. If INTE flip-flop is set, the interrupt request is generated depending
on the status of STB and IBF signals. If INTE flip flop is reset, the interrupt request is
not generated, allowing masking facility for the interrupt.

Mode 1: Port A Input Operation

Figure shows Port A as an input port along with the control word and control
signals (for handshaking with a peripheral). When the control word is loaded into the
control register, Group A is configured in Mode 1 with Port A as an input port. Port A
can accept parallel data from a peripheral (like a keyboard) and this data can be
read by the CPU. The peripheral first loads data into Port by making the STB A input
low. This latches the data placed by the peripheral on the common data bus into Port

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A. Port A acknowledges reception of data by making IBFA (Input Buffer Full) high.
IBFA is set when the STB A input is made low, as shown in figure.

INTRA is an active high output signal which can be used to interrupt the CPU
so that the CPU can suspend its current operation and read the data written into Port
A by the peripheral. INTRA can be enabled or disabled by the INTEA flip-flop which is
controlled by Bit Set-Reset operation of PC4. INTRA is set (if enabled by setting the
INTEA flip-flop) after the STBA has gone high again, and if IBFA is high.
On receipt of the interrupt, the CPU can be forced to read Port A. The falling
edge of the RD input resets IBFA and it goes low. This can be used to indicate to the
peripheral that the input buffer is empty and that data can again be loaded into it.

Mode 1: Port B Input Operation

Figure shows Port B as an input port (when in Mode 1). The timing diagram
and operation of Port B is similar to that of Port A except that it uses different bits of
Port C for control. INTEB is controlled by Bit Set/Reset of PC2.

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 If the CPU is busy with other system operations, it can read data from the
input port when it is interrupted. This is often called Interrupt driven I/O. However, if
the CPU is otherwise not busy with other jobs, it can continuously poll (read) the
status word to check for an IBF A. This is often called Program Controlled I/O. The
status word is accessed by reading Port C (A1 A0 must be 10, RD and CS must be
low). The status word format when Ports A and B are input ports in Mode 1, is shown
in Fig.

Mode 1: Output control signals:

1. OBF (Output Buffer Full) :
This is an active low output signal for 8255 Programming and Operation and
input signal for the output device. The 8255 activates this signal to indicate output
device that data is available on the output port. Upon activation of OBF signal,
output device reads data from the output port and acknowledges it by ACK signal.
The OBF signal is activated at the rising edge of the WR signal and de-activated at
the falling edge of the ACK signal.
2. ACK (Acknowledge Input):
This is an active low input signal for 8255 and output signal for the output
device. The output device generates this signal to indicate 8255 that the data from
port A or Port B has been accepted.
3. INTR (Interrupt Request) :
This is an active high output signal generated by 8255 A ‘high’ on this output
can be used to interrupt the CPU when an output device has accepted data
transmitted by the CPU. The 8255 Programming and Operation sets the INTR when
ACK signal is ‘one’, OBF is ‘one’ and INTE is ‘one, indicating that the output device
is ready to accept next data byte. This signal is reset by the falling edge of the WR
signal i.e. immediately after sending the data to the output port.
INTE (Interrupt Enable) flip-flop is used to enable or disable INTR (Interrupt
Request) signal. If INTE flip flop is set, the interrupt request is generated depending
on the status of ACK and OBF signals. If INTE flip flop is reset, the interrupt request
is not generated, allowing masking facility for the interrupt.

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Mode 1 : Port A output operation:

Figure shows Port A configured as an output port (when in Mode 1) along with
the control word and control signals (for handshaking with a peripheral). When the
control word is loaded into the control register, Group A is configured in Mode 1 with
Port A as an output port The CPU can send data to a peripheral (like a display
device) through Port A of the 8255.
The OBFA output (Output Buffer Full) goes low on the rising edge of the WR
signal (when the CPU writes data into the 8255). The OBF A output from 8255
Programming and Operation can be used as a strobe input to the peripheral to
latch the contents of Port A. The peripheral responds to the receipt of data by
making the ACK A input of the 8255 low, thus acknowledging that it has received the
data sent by the CPU through Port A. The ACK A low sets the OBFA signal, which
can be polled by the CPU through OBF A of the status word to load the next data
when it is high again.

INTRA is an active high output of the 8255 Programming and Operation which
is made high. (if the associated INTEA flip-flop is set) when ACK A is made high
again by the peripheral, and when OBF A goes high again . It can be used to interrupt

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the CPU whenever the output buffer is empty. It is reset by the falling edge of WR
when the CPU writes data onto Port A. It can be enabled or disabled by writing a ‘1’
or a’0′ respectively to PC6 in the BSR mode.
Mode 1 : Port B output operation:

Figure shows Port B as an output port when in Mode 1. The operation of Port
B is similar to that of Port A. INTRA is controlled by writing a ‘1’ or a ‘0’ to PC 2 in the
BSR mode. The status word is accessed by issuing a Read to Port C. The format of
the status word when Ports A and B are Output ports in Mode 1 is shown in Fig..

Programming in Mode 2 (Strobes Bi-directional Bus I/O):

When the 8255 Programming and Operation is operated in Mode 2 (by

loading the appropriate control word), Port A can be used as a bi-directional 8-bit I/O
bus using for handshaking. Port B can be programmed in Mode 0 or in Mode 1.

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When Port B is programmed in mode 1, PC 0 – PC2 lines of Port C are used as
handshaking signals.
Mode 2 : Control signals:
I NTR (Interrupt Request).: A ‘high’ on this output can be used to interrupt the
CPU for input or output operations.
Output Control Signals :
OBF A (Output Buffer Full):
This is an active low output which indicates that the CPU has written data into
Port A.
ACK A (Acknowledge):
This is an active low input signal (generated by the peripheral) which enables
the tri-state output buffer of Port A and makes Port A data available to the peripheral.
In Mode 2, Port A outputs are in tri-state until enabled.
INTE 1:
This is the flip-flop associated with Output Buffer Full. INTE 1 can be used to
enable or disable the interrupt by setting or resetting PC 6 in the BSR Mode.
Input Control Signals:
STB (Strobe Input):
This is an active low input signal which enables Port A to latch the data
available at its input.
IBF (Input Buffer Full Flip-Flop):
This is an active high output which indicates that data has been loaded into
the input latch of Port A.
INTE 2:
This is an Interrupt enable flip-flop associated with Input Buffer Full. It can be
controlled by setting or resetting PC4 in the BSR Mode.
Mode 2 : Port A operation:

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 Figure shows Port A and associated control signals when 8255 is in Mode 2.
Interrupts are generated for both output and input operations on the same
INTRA (PC3) line.
Status Word In Mode 2:

The status word for Mode 2 (accessed by reading Port C) is shown in Fig. D7 -
D3 of the status word carry information about OBF A, INTE1, IBFA ,INTE2 ,INTRA .The
status of the bits D2 - D0 depends on the mode setting of Group B. If B is
programmed in Mode 0, D2 - D0 are the same as PC2 - PC0 (simple I/O); however if B
is in Mode 1, D2 – D0 carry information about the control signals for Port B depending
upon whether Port B is an Input port or Output port respectively.
Timing diagram of mode 2

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Interfacing of 8255 with 8085
The 8255 can be either memory mapped or I/O mapped in the system. Using
a 3 to 8 decoder generates the chip select signals for I/O mapped devices. The
address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-
0 to IOCS-7) and in this, the chip select IOCS- 1 is used to select 8255.
The address line A7 and the control signal IO/M (low) are used as enable for
the decoder. The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085
is connected to A1 of 8255 to provide the internal addresses. The data lines D0-D7
are connected to D0-D7 of the processor to achieve parallel data transfer. RESET
OUT pin of 8085 is connected to the RESET pin of 8255. When the microprocessor
is reset, it also resets the 8255 via this connection. RD and WD pins of 8085 are
connected to the RD and WD pins of 8255, respectively.

The I/O addresses allotted to the internal devices of 8255 are listed in table.

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3.2 Programmable Interrupt Controller - 8259
Interrupts can be used for variety of applications. Each of these interrupt
applications requires a separate interrupt input. If we are working with an 8085
microprocessor we get TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR interrupt inputs.
For applications when we have multiple interrupt sources (more than five), we have
to use external device called a Priority Interrupt Controller (PIC). By connecting such
a device it is possible to increase the interrupt handling capacity of the
microprocessor.

The 8259A is a commonly used priority interrupt controller, which is

specifically designed for use with interrupt signals INTR and INTA.

Features of 8259
1. It can manage eight priority interrupts. This is equivalent to providing eight
interrupt pins on the processor in place of INTR pin.
2. It is possible to locate vector table for these additional interrupts any where in the
memory map. However, all eight interrupts are spaced at the interval of either four or
eight locations.
3. By cascading nine 8259s it is possible to get 64 priority interrupts.
4. Interrupt mask register makes it possible to mask individual interrupt request.
5. The Features of 8259A can be programmed to accept either the level triggered or
the edge triggered interrupt request.
6. With the help of 8259A user can get the information .of pending interrupts, in-
service interrupts and masked interrupts.
7. The Features of 8259A is designed to minimize the software and real time
overhead in handling multi-level priority interrupts.

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Pin Details of 8259

Architecture of 8259

The figure shows the internal 8259 Block Diagram. It includes eight blocks:
data bus buffer, read/write logic, control logic, three registers (IRR, ISR and IMR),
priority resolver, and cascade buffer.
Data Bus Buffer:
The data bus buffer allows the 8085 to send control words to the 8259A and
read a status word from the 8259 Block Diagram. The 8-bit data bus buffer also
allows the 8259A to send interrupt opcode and address of the interrupt service
subroutine to the 8085.

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Read/Write Logic:
The RD and WR inputs control the data flow on the data bus when the device
is selected by asserting its chip select ( CS ) input low.
Control Logic:
This block has an input and an output line. If the 8259A is properly enabled,
the interrupt request will cause the 8259A to assert its INT output pin high. If this pin
is connected to the INTR pin of an 8085 and if the 8085 Interrupt Enable (IE) flag is
set, then this high signal will cause the 8085 to respond INTR.
Interrupt Request Register (IRR):
The IRR is used to store all the interrupt levels which are requesting the
service. The eight interrupt inputs set corresponding bits of the Interrupt Request
Register upon service request.
Interrupt Service Register (ISR):
The Interrupt Service Register (ISR) stores all the levels that are currently
being serviced.
Interrupt Mask Register (IMR):
Interrupt Mask Register (IMR) stores the masking bits of the interrupt lines to
be masked. This register can be programmed by an Operation Command Word
(OCW). An interrupt which is masked by software will not be recognised and
serviced even if it sets the corresponding bits in the IRR.
Priority Resolver:
The priority resolver determines the priorities of the bits set in the IRR. The bit
corresponding to the highest priority interrupt input is set in the ISR during the INTA
input.
Cascade Buffer Comparator:
This section generates control signals necessary for cascade operations. It
also generates Buffer-Enable signals. As stated earlier, the 8259 Block Diagram can
be cascaded with other 8259s in order to expand the interrupt handling capacity to
sixty-four levels. In such a case, the former is called a master, and the latter are
called slaves. The 8259 can be set up as a master or a slave by the SP/EN pin.
CAS0— CAS2
For a master 8259, the CAS0-CAS2 pins are output pins, and for slave 8259,
these are input pins. When the 8259 is a master (that is, when it accepts interrupt
requests from other 8259s), the CALL opcode is generated by the Master in
response to the first INTA.
The vector address must be released by the slave 8259. The master sends an
identification code of three-bits to select one out of the eight possible slave 8259s on
the CAS0-CAS2 lines. The slave 8259s accept these three signals as inputs (on their
CAS0 – CAS2 pins) and compare the code sent by the master with the codes
assigned to them during initialization.
The slave thus selected (which had originally placed an interrupt request to
the master 8259) then puts the address of the interrupt service routine during the
second and third INTA pulses from the CPU.

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SP / EN (Slave Program /Enable Buffer):
The SP / EN signal is tied high for the master. However it is grounded for the
slave. In large systems where buffers are used to drive the data bus, the data sent
by the 8259 in response to INTA cannot be accessed by the CPU (due to the data
bus buffer being disabled).
If an 8259 is used in the buffered mode (buffered or non-buffered modes of
operation can be specified at the time of initializing the 8259), the SP / EN pin is used
as an output which can be used to enable the system data bus buffer whenever the
data bus outputs of 8259 are enabled (i.e. when it is ready to send data).
Thus, in non-buffered mode, the SP / EN pin of an 8259 is used to specify
whether the 8259 is to operate as a master or as a slave, and in the buffered mode,
the SP/EN pin is used as an output to enable the data bus buffer of the system.

Interrupt Sequence:
The events occur as follows in an 8085 system :
 One or more of the INTERRUPT REQUEST lines (IR 0-IR7) are raised high,
setting the, corresponding IRR bit(s).
 The priority resolver checks three registers : The IRR for interrupt requests,
the IMR for masking bits, and the ISR for the interrupt request being served. It
resolves the priority and sets the INT high when it is appropriate to do so.
 In response to the INTR signal, 8085 completes current instruction cycle and
executes interrupt acknowledge cycle, thus giving an INTA pulse.
 Upon receiving an INTA from the 8085, the highest priority ISR bit is set and
the corresponding IRR bit is reset. Then 8259A places the opcode for CALL
instruction on the data bus.
 This CALL instruction initiates two more interrupt acknowledge cycles.
 These two interrupt acknowledge cycles allow the 8259 to release
preprogrammed subroutine address onto, the data bus. In response to second
interrupt acknowledge pulse 8259 place’s a lower byte of interrupt subroutine
address and in response to third interrupt acknowledge pulse 8259 places a
higher byte of the subroutine address.
 This completes the interrupt cycle. In the AEOI (Automatic End of Interrupt)
mode the ISR bit is reset at the end of the second INTA pulse. Otherwise, the
ISR bit remains set until the issue of an appropriate EOI command at the end
of the interrupt subroutine.
Operating modes of 8259
The various Operating Modes of 8259 Programmable Interrupt Controller are:
 Fully Nested Mode
 Special Fully Nested Mode (SFNM)
 Rotating Priority Mode,
 Special Mask Mode
 Polled Mode

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1. Fully Nested Mode (FNM) :
After initialization, the 8259A operates in fully nested mode so it is called
default mode. The 8259 continues to operate in the Fully Nested Mode until the
mode is changed through Operation Command Words. In this mode, IR 0 has highest
priority and IR7 has lowest priority. When the interrupt is acknowledged, it sets the
corresponding bit in ISR.
This bit will inhibit all interrupts of the same or lower level, however it will
accept higher priority interrupt requests. The vector address corresponding to this
interrupt is then sent. The bit in the ISR will remain set until an EOI command is
issued by the microprocessor at the end of interrupt service routine. But if AEOI
(Automatic End 0f Interrupt) bit is set, the bit in the ISR resets at the trailing edge of
the last INTA .
End of Interrupt (EOI):
 The ISR bit can be reset by an End of Interrupt command issued by the CPU,
usually just before exiting from the interrupt routine.
 In the Fully Nested Mode, the highest level in the ISR would necessarily
correspond to the last interrupt acknowledged and serviced. In such a case, a
non-specific EOI command may be issued by the CPU.
 However, if the FNM is not used, the 8259 may not be able to determine the
last interrupt acknowledged. In such a case, a specific EOI command will
have to be issued by the CPU.
 It should be noted that in the cascade mode, the EOI command must be
issued twice, once for the master and once for the slave.
Automatic End of Interrupt (AEOI):
If the AEOI mode is set, the 8259 Block Diagram will perform a non-specific
EOI on its own on the trailing edge of The third INTA pulse. The AEOI mode can only
be used for a master 8259 and not for a slave.
2. Special Fully Nested Mode (SFNM):
` In the FNM, on the acknowledgement of an interrupt, further interrupts from
the same level are disabled. Consider a large system which uses cascaded 8259s
and where the interrupt levels within each slave have to be considered. An interrupt
request input to a slave, in turn causes the slave to place an interrupt request to the
master on one of the master’s inputs.
Further interrupts to the slave will cause the slave to place requests to the master
on the same input to the master, but these will not be recognised because further
interrupts on the same input level are disabled by the master.
The Special Fully Nested Mode (SFNM) is used to avoid this problem. The SFNM
is set up by ICW4 during initialization. It is similar to the FNM except for the following
differences:
 When an interrupt request from a slave is being serviced, the slave is allowed
to place further requests if these requests are of a higher priority than the
request currently being serviced. These interrupts are recognised by the
master and it initiates interrupt requests to the CPU.

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  Before exiting from the interrupt service routine, a non-specific EOI must be
sent to the slave and its ISR must be read to determine if it was the only
interrupt to the slave. If the ISR is empty, a non-specific EOI command can be
sent to the master. If it is not empty, it implies that the same IR level input to
the master is to be serviced again due to snore than one interrupts being
presented to the slave, and an EOI must not be sent to the master.
3. Rotating Priority Mode:
The Rotating Priority mode can be set in (i) Automatic Rotation, and (ii)
Specific Rotation.
i) Automatic Rotation:
In this mode, a device, after being serviced, receives the lowest priority. The
device just been serviced, will receive the seventh priority. Here IR 3 has just been
serviced.

ii)Specific Rotation:
In the Automatic Rotation mode, the interrupt request last serviced is
assigned the lowest priority, whereas in the Specific Rotation mode, the lowest
priority can be assigned to any interrupt input (IR 0 to IR7) thus fixes all other
priorities.

For example if the lowest priority is assigned to IR 2, other priorities are as

shown below.
4. Special Mask Mode:
If any interrupt is in service, then the corresponding bit is set in ISR and the
lower priority interrupts are inhibited. Some applications may require an interrupt
service routine to dynamically alter the system priority structure during its execution
under software control.
For example, the routine may wish to inhibit lower priority requests for a
portion of its execution but enable some of them for another portion. In these cases,
we have to go for special mask mode. In the special mask mode it inhibits further
interrupts at that level and enables interrupts from all other levels (lower as well as
higher) that are not masked. Thus any interrupt may be selectively enabled by
loading the mask register.
5. Polled Mode :
In this mode the INT output is not used. The microprocessor checks the status
of interrupt requests by issuing poll command. The microprocessor reads contents of
8259A after issuing poll command. During this read operation the 8259A provides
polled word and sets ISR bit of highest priority active interrupt request FORMAT.

22
I = 1 —> One or more interrupt requests activated.
I = 0 —> No interrupt request activated.
W 2 W 1 W 0 —> Binary code of highest priority active interrupt request.

Programming the 8259

The 8259 Programmable Interrupt Controller requires two types of command
words. Initialization Command Words (ICWs) and Operational Command Words
(OCWs). The 8259 Programmable Interrupt Controller can be initialized with four
ICWs; the first two are compulsory, and the other two are optional based on the
modes being used. These words must be issued in a given sequence. After
initialization, the 8259A can be set up to operate in various modes by using three
different OCWs; however, they are not necessary to be issued in a specific
sequence.

23
Initialization Command Word 1 (ICW1):

Figure shows the Initialization Command Word 1(ICW1). A write command

issued to the 8259 with A0 = 0 and D4 = 1 is interpreted as ICW1, which starts the
initialization sequence. It specifies,
 Single or multiple 8259As in the system
 4 or 8 bit interval between the interrupt vector locations.
 The address bits A7 – A5 of the CALL instruction. (3 bits of lower byte address
of CALL are given by user, rest bits are inserted by 8259A)
 Edge triggered or level triggered interrupts.
 ICW4 is needed or not.
Initialization Command Word 2 (ICW2):

Figure shows the Initialization command Word 2 (ICW2).

A write command following ICW1, with A0 = 1 is interpreted as ICW2. This is
used to load the high order byte of the interrupt vector address of all the interrupts.

24
Initialization Command Word 3 (ICW3):

ICW3 is required only if there is more than one 8259 in the system and if they
are cascaded. An ICW3 operation loads a slave register in the 8259 Programmable
Interrupt Controller. The format of the byte to be loaded as an ICW3 for a master
8259 or a slave is shown in the Fig. For master, each bit in ICW3 is used to specify
whether it has a slave 8259 attached to it on its corresponding IR (Interrupt Request)
input. For slave, bits D0 – D2 of ICW3 are used to assign a slave identification code
(slave ID) to the 8259 Programmable Interrupt Controller.
Initialization Command Word 4 (ICW4):
It is loaded only, if the D0 bit of ICW1 is set. The format of ICW4 is shown in
Fig.

It specifies,
 Whether to use special fully nested mode or non special fully nested mode.
 Whether to use buffered mode or non buffered mode.
 Whether to use Automatic EOI or Normal EOI.
 CPU used 8086/8088 or 8085.

25
Operation Command Words (OCWs):
After initialization, the 8259 Programmable Interrupt Controller is ready to
process interrupt requests. However, during operation, it might be necessary to
change the mode of processing the interrupts. Operation Command Words (OCWs)
are used for this purpose. They may be loaded anytime after the initialization of 8259
to dynamically alter the priority modes.
Operation Command Word 1 (OCW1):
A Write command to the 8259 with A0 = 1 (after ICW2) is interpreted as
OCW1. OCW1 is used for enabling or disabling the recognition of specific interrupt
requests by programming the IMR.

M = 1 indicates that the interrupt is to be masked, and M = 0 indicates that it is

to be unmasked as shown in Fig. 14.80.

Operation Command Word 2 (OCW2):

A Write command with A0 = 1 and D4 D3 = 00 is interpreted as OCW2. The R
(Rotate), SL (Select-Level), EOI bits control the Rotate and End of Interrupt Modes
and combinations of the two.

Figure shows the Operation Command Word format. L 2-L0 are used to specify
the interrupt level to be acted upon when the SL bit is active.
Operation Command Word 3 (OCW3):
OCW3 is used to read the status of the registers; and to set or reset the
Special Mask and Polled modes. Figure shows format of operation command word
3.

26
8259 Status Read Operations:
The status of the Interrupt Request Register, the Interrupt-Service Register,
and the Interrupt Mask Register of the 8259 may be read by issuing appropriate read
commands.
IRR Status Read:
An OCW3 with RR (Read Register) = 1 and RIS (Read ISR) = 0 set up the
8259 for a status read of the Interrupt Request Register.
When the 8259 is not in the Polled mode, after it is set up for. an IRR status
read operation, all Read commands with A0=1 cause the 8259 to send the IRR
status word.
ISR Status Read:
An OCW3 with RR = 1 and ISR = 1 sets up the 8259 for a status read of the
Interrupt-Service Register. A subsequent read command issued to the 8259 will
cause the 8259 to send the contents of the ISR onto the data bus.
IMR Status Read:
A Read command issued to the 8259 Programmable Interrupt Controller with
A0 = 1 (with RD, CS = 0 ) causes the 8259 to put the contents of the Interrupt Mask
Register on the data bus. OCW3 is not required for a status read of the IMR.
As described earlier, the sequence shown in flowchart must be followed to
initialize 8259A. According to this flow chart, an ICW1 and an ICW2 must be sent to
any 8259A in the system. If the system has any slave 8259As (cascade mode), then
an ICW3 must be sent to the master, and a different ICW3 must be sent to the slave.
If the system is an 8086, or if you want to specify certain special conditions; then you
have to send an ICW4 to the master and to each slave.

27
Interfacing of 8259 with 8085

28
3.3 Programmable Interval Timer – 8253/54
Necessity
The 8253/54 solves one of most common problem in any microcomputer
system, the generation of accurate time delays under software control. Instead of
setting up timing loops in system software, the programmer configures the 8253/54
to match his requirements, initializes one of the counters of the 8253/54 with
the desired quantity, then upon command the 8253/54 will count out the delay
and interrupt the CPU when it has completed its tasks. It is easy to see that the
software overhead is minimum and that multiple delays can be easily be
maintained by assignment of priority levels.
The 8253/54 includes three identical 16 bit counters that can operate
independently. To operate a counter, a 16-bit count is loaded in its register and,
on command, it begins to decrement the count until it reaches 0. At the end of
the count, it generates a pulse that can be used to interrupt the CPU. The
counter can count either in binary or BCD. In addition, a count can be read by the
CPU while the counter is decrementing. The 8254 is a superset of 8253. The
functioning of these two ICs are almost similar along with the pin configuration.
Only the differences are:
8253 8254
1. Operating frequency 0 - 2.6 MHz 1. Operating frequency 0 - 10 MHz
2. Uses N-MOS technology. 2. Uses H-MOS technology.
3. Read-Back command not 3. Read-Back command available.
avail- able.
4. Reads and writes of the same 4. Reads and writes of the same
counter cannot be interleaved. counter can be interleaved.

Features of 8253/54
 Three independent 16-bit down counters.
 8254 can handle inputs from DC to 10 MHz (5MHz 8254-5
8MHz 8254 10MHz 8254-2) where as 8253 can operate upto 2.6 MHz.
 Three counters are identical presettable, and can be programmed for
either binary or BCD count.
 Counter can be programmed in six different modes.
 Compatible with all Intel and most other microprocessors.
 8254 has powerful command called READ BACK command which
allows the user to check the count value, programmed mode and current
mode and current status of the counter.

29
Pin diagram of 8253

Block Diagram of 8253

It includes three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals CLOCK and GATE and
one output signal OUT.
Data Bus Buffer:
This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to
the system data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.
2. Loading the count registers.
3. Reading the count values.

30
Read/Write Logic:
The Read/Write logic has five signals: RD , WR, CS and the address lines
A0 and A1. In the peripheral I/O mode, the RD and WR signals are connected to
IOR and IOW respectively. In memory-mapped I/O, these are connected to
MEMR and MEMW . Address lines A0 and A1 of the CPU are usually connected
to lines A0 and A1 of the 8253/54, and CS is tied to a decoded address. The control
word register and counters are selected according to the signals on lines A0 and
A1.
A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control word Register
Control Word Register:
This register is accessed when lines A0 and A1 are at logic 1. It is used
to write a command word which specifies the counter to be used (binary or BCD),
its mode, and either a read or write operation.
Counters:
These three functional blocks are identical in operation. Each counter
consists of a single, 16 bit, pre-settable, down counter. The counter can operate
in either binary or BCD and its input, gate and output are configured by the
selection of modes stored in the control word register. The counters are fully
independent. The programmer can read the contents of any of the three counters
without disturbing the actual count in process.
Operational Description:
Programming with 8253/54
Each counter of the 8253/54 is individually programmed by writing a
control word into the control word register (A0A1 = 11). Bits SC1 and SC0
select the counter, bits RW 1 and RW 0 select the read, write or latch command,
bits M2, M1 and M0 select the mode of operation and bit BCD decides whether
it is a BCD counter or binary counter.
WRITE Operation:
1. Write a control word into control register.
2. Load the low-order byte of a count in the counter register.
3. Load the high-order byte of count in the counter register

31
READ Operation:
In some applications, especially in event counters, it is necessary to
read the value of the count in process. This can be done by three possible
methods:
Simple Read:
It involves reading a count after inhibiting the counter by controlling the
gate input or the clock input of the selected counter, and two I/O read operations
are performed by the CPU. The first I/O operation reads the low-order byte,
and the second I/O operation reads the high order byte.
Counter Latch Command:
In the second method, an appropriate control word is written into the
control register to latch a count in the output latch, and two I/O read
operations are performed by the CPU. The first I/O operation reads the low-
order byte, and the second I/O operation reads the high order byte.
Read-Back Command (Available only for 8254):
The third method uses the Read-Back command. This command allows the
user to check the count value, programmed Mode, and current status of the OUT
pin and Null count flag of the selected counter(s).

32
Control word register for Read-Back command

The Read-Back command may be used to latch multiple counter output

latches by setting the COUNT bit D5 = 0 and selecting the desired counter (s).
Each counter’s latch count in held until it is read (or the counter is reprogrammed).
That counter is automatically unlatched when read.
Other Features of Read - Back Command (Available only for 8254) :
The Read-Back command may also be used to latch status information of
selected counter(s) by setting STATUS bit D4 = 0. The contents of the counter
must be latched before reading. The status of a counter is then accessed by a
read from that counter.

Bit D5 - D0 contains the counter’s programmed mode exactly as written in

the last mode control word. Bit D7 contains the current status of the output
pin. In 8254, it is not possible to read count from the counter, if the count is not
loaded into the counting element (CE). The Bit D6 indicates whether the
counting element has count or not. If D6 = 0, counting element has count
otherwise null count.
Interleaved Read and Write:
Another feature of the 8254 is that reads and writes of the same counter
may be interleaved. For example, if the counter is programmed for the two
byte counts, the following sequence is valid.
1. Read least significant byte.
2. Write new least significant byte.
3. Read most significant byte.
4. Write new most significant byte.

33
Modes of operation of 8253/54:
Each of the three counters of 8253 can be operated in one of the following six
modes of operation.
 Mode 0 (Interrupt on terminal count)
 Mode 1 (Programmable monoshot)
 Mode 2 (Rate generator)
 Mode 3 (Square wave generator)
 Mode 4 (Software triggered strobe)
 Mode 5 (Hardware triggered strobe)
Mode 0:
This mode of operation is generally called as interrupt on terminal count. In
this mode, the output is initially low after the mode is set. The output remains low
even after the count value is loaded in the counter. The counter starts decrementing
the count value after the falling edge of the clock, if the GATE input is high. The
process of decrementing the counter continues at each falling edge of the clock till
the terminal count is reached (the count becomes zero).
When the terminal count is reached, the output goes high and remains high till
the selected control word register or the corresponding register is reloaded with a
new mode of operation or a new count respectively.
This high output may be used to interrupt the processor whenever is required,
by setting a suitable terminal count. Writing a count register while the previous
counting is in process generates the following sequence of response.
The first byte of the new count when loaded in the count register stops the
previous count. The second byte when written, starts the new count, terminating the
previous count and then and there.
The GATE signal is active high should be high for normal counting. When
GATE goes low counting is terminated and the current count is latched till the GATE
again goes high.

34
Mode 1:
This mode of operation is called as programmable one shot mode. As the
name implies, in this mode, the 8253 can be used as a monostable multivibrator.
The duration state of the monostable multivibrator is decided by the count loaded in
the count register. The gate input is used as a trigger input in this mode of operation.
Normally the output remains high till the suitable count is loaded in the count register
and a trigger is applied.
After the application of a trigger( on the positive edge), the output goes low
and remains low till the count becomes zero. If another count is loaded when the
output is already low, it does not disturb the previous till a new trigger pulse is
applied at the gate input. The new counting starts after the new trigger pulse.

Mode 2:
This mode is called either rate generator or divide by N counter. IN this mode,
if N is loaded as the count value, then after N pulses, the output becomes low only
for one clock cycle. The count N is reloaded and again the output becomes high and
remains so for N clock pulses. The output is normally high after the initialization or
even a low signal on GATE input can force the output to go high. If GATE goes high,
the counter starts counting down from the initial value. The counter generates an
active low pulse at the output initially, after the count register is loaded with a count
value
Then count down starts and whenever the count becomes zero, another
active low pulse is generated at the output. The duration of these active low pulses
are equal to one clock cycle. The number of input clock pulses between the two low
pulses at the output is equal to the count loaded/ The counting is inhibited when
GATE becomes low.

35
Mode 3:
In this mode 8253 can be used as a square wave generator. The operation is
somewhat similar to mode 2. When the count N loaded is even, then for half of the
count, the output remains high and for the remaining half it remains low. If the count
loaded is odd, the first clock pulse decrements it by 1 resulting in an even count
value(holding the output high). Then the output remains high for half of the new
count and goes low for the remaining half. This procedure is repeated continuously
resulting in the generation of a square wave.
In case of odd count, the output is high for longer duration and low for shorter
duration. The difference of one clock cycle duration between the two periods is due
to the initial decrementing of the odd count. In general, if the loaded count ‘N’ is odd,
then for (N+1)/2 pulses the output remains high and for (N-1)/2 pulses it remains low.

Mode 4:
This mode of operation is called software triggered strobe. After the mode is
set, the output goes high. When a count is loaded, counting down starts. On terminal
count, the output goes low for one clock cycle and then it again goes high. This low
pulse can be uses as a strobe, while interfacing the microprocessor with other
peripherals. The count is inhibited and the count value is latched, when the GATE
signal goes low.
If a new count is loaded in the count register while the previous counting is in
progress, it is accepted from the next clock cycle. The counting then proceeds
according to the new count.

36
Mode 5:
This mode of operation also generates a strobe in response to the rising edge
at the trigger input. This mode may be used to generate a delayed strobe in
response to an externally generated signal. Once this mode is programmed and the
counter is loaded, the output goes high.
The counter starts counting after the rising edge of the trigger input (GATE).
The output goes low for one clock period, when the terminal count is reached. The
output will not go low until the counter content becomes zero after the rising edge of
any trigger. The GATE input in this mode is uses as trigger input.

37
Interfacing of 8253 with 8085
Initialize 8253/54 in mode 1 to read and load lower 8 bits only. Assume
that 8253/54 is interfaced in memory mapped I/O.

Step 1:
12H is the control word for 8253 with the counter in mode 1. Binary counter 0
is selected. Load lower 8 bits only.

Step 2:
05H is the lower 8 bit count.
Step 3:
02H is the control word for 8253 with the counter in mode 1. It latches the
count and then stores it in register, so that it can be read.
Step 4:
Connect the gate to VCC through a tag and start giving pulse. When the pulse
is given the LED turns off at the falling edge of the pulse. The count is OFH. So the
output of the counter will go low for 16 counts and the LED at that pin remains off
and then it begins to glow again.
Step 5:
On the basis of chip select logic and A1A0 signals, assuming X=0, the address
of the different counters and CWR are

Program:

38
Interfacing diagram:

39
3.4 Serial communication Interface
Classification of serial data transmission
Simplex
The data transfer takes place only in one direction. There is no possibility of
data transfer in the other direction. Ex: Transmission from a computer to the printer
Half Duplex
It allows the data transfer in both directions, but not simultaneously. Ex:
Walkie-Talkie
Full Duplex:
It allows the data transfer in both directions simultaneously. Ex: Transmission
through telephone lines
Asynchronous Vs Synchronous transmission
Asynchronous transmission

Synchronous transmission

Comparison

40
8251 - USART
USART stands for Universal Synchronous and Asynchronous Receiver Transmitter
and functions as an intermediary that allows serial and parallel communication
between the microprocessor and the peripheral devices.
 It takes data serially from peripheral (outside devices) and converts into
parallel data.
 After converting the data into parallel form, it transmits it to the CPU.
 Similarly, it receives parallel data from microprocessor and converts it into
serial form.
 After converting data into serial form, it transmits it to outside device
(peripheral).
Features:
 It supports standard asynchronous protocol and synchronous protocol.
 It has built in baud rate generator
 It allows full duplex transmission and reception.
 It provides double buffering of data both in the transmission and receiver
section.
 It provides error detection logic, which detects parity, overrun and framing
errors.
 It has modem control logic, which supports basic data set control signals.
 It provides separate clock inputs for transmitter and receiver sections.

Pin details of 8251:

41
D0 to D7 (l/O terminal)
This is bidirectional data bus which receives control words and transmits data
from the CPU and sends status words and received data to CPU.
RESET (Input terminal)
A “High" on this input forces the 8251 into “reset status" .The device waits for
the writing of "mode instruction." The min. reset width is six clock inputs during the
operating status of CLK.
CLK (Input terminal)
CLK signal is used to generate internal device timing. CLK signal is
independent of RxC or TxC . However, the frequency of CLK must be greater than
30 times the RxC and TxC at Synchronous mode and Asynchronous "x1" mode,
and must be greater than 5 times at Asynchronous "x16" and "x64" mode.
WR (Input terminal)
This is the "active low" input terminal which receives a signal for writing
transmit data and control words from the CPU into the 8251.
RD (Input terminal)
This is the "active low" input terminal which receives a signal for reading
receive data and status words from the 8251.
C / D (Input terminal)
This is an input terminal which receives a signal for selecting data or
command words and status words when the 8251 is accessed by the CPU. If C / D =
low, data will be accessed. If C / D = high, command word or status word will be
accessed.
CS (Input terminal)
This is the "active low" input terminal which selects the 8251 at low level when
the CPU accesses. Note: The device won’t be in "standby status"; only setting CS =
High.
TXD (output terminal)
This is an output terminal for transmitting data from which serial-converted
data is sent out. The device is in "mark status" (high level) after resetting or during a
status when transmit is disabled. It is also possible to set the device in "break status"
(low level) by a command.
TXRDY (output terminal)
This is an output terminal which indicates that the 8251is ready to accept a
transmitted data character. But the terminal is always at low level if CTS = high or
the device was set in "TX disable status" by a command. Note: TXRDY status word
indicates that transmit data character is receivable, regardless of CTS or command.
If the CPU writes a data character, TXRDY will be reset by the leading edge or WR
signal.
TXEMPTY (Output terminal)
This is an output terminal which indicates that the 8251 has transmitted all the
characters and had no data character. In "synchronous mode," the terminal is at high

42
level, if transmit data characters are no longer remaining and sync characters are
automatically transmitted. If the CPU writes a data character, TXEMPTY will be reset
by the leading edge of WR signal.
Note : As the transmitter is disabled by setting CTS “High" or command, data written
before disable will be sent out. Then TXD and TXEMPTY will be “High". Even if a
data is written after disable, that data is not sent out and TXE will be “High". After the
transmitter is enabled, it sent out.
TXC (Input terminal)
This is a clock input signal which determines the transfer speed of transmitted
data. In “synchronous mode," the baud rate will be the same as the frequency of
TXC . In “asynchronous mode", it is possible to select the baud rate factor by mode
instruction. It can be 1, 1/16 or 1/64 the TXC . The falling edge of TXC sifts the serial
data out of the 8251.
RXD (input terminal)
This is a terminal which receives serial data.
RXRDY (Output terminal)
This is a terminal which indicates that the 8251 contains a character that is
ready to READ. If the CPU reads a data character, RXRDY will be reset by the
leading edge of RD signal. Unless the CPU reads a data character before the next
one is received completely, the preceding data will be lost. In such a case, an
overrun error flag status word will be set.
RXC (Input terminal)
This is a clock input signal which determines the transfer speed of received
data. In “synchronous mode”, the baud rate is the same as the frequency of RXC . In
“asynchronous mode", it is possible to select the baud rate factor by mode
instruction. It can be 1, 1/16, 1/64 the RXC .
SYNDET/BD (Input or output terminal)
This is a terminal whose function changes according to mode. In “internal
synchronous mode" ,this terminal is at high level, if sync characters are received and
synchronized. If a status word is read, the terminal will be reset. In "external
synchronous mode, "this is an input terminal. A “High" on this input forces the 8251
to start receiving data characters.
In “asynchronous mode", this is an output terminal which generates “high
level" output upon the detection of a “break" character if receiver data contains a
“low-level" space between the stop bits of two continuous characters. The terminal
will be reset, if RXD is at high level. After Reset is active, the terminal will be output
at low level.
DSR (Input terminal)
This is an input port for MODEM interface. The input status of the terminal can
be recognized by the CPU reading status words.

43
DTR (Output terminal)
This is an output port for MODEM interface. It is possible to set the status of
DTR by a command.
CTS (Input terminal)
This is an input terminal for MODEM interface which is used for controlling a
transmit circuit. The terminal controls data transmission if the device is set in "TX
Enable" status by a command. Data is transmittable if the terminal is at low level.
RTS (Output terminal)
This is an output port for MODEM interface. It is possible to set the status
RTS by a command.

Architecture of 8251

Data bus buffer:

This tri-state, bi-directional, 8-bit buffer is used to interface 8251 to the system
data bus. Along with the data, control word, command words and status information
are also transferred through the data bus buffer.
Read/Write control logic:
This functional block accepts inputs from system control bus and generates
control signals for overall system operation. It decodes the control signals on the
8085 control bus into signals which controls the internal and external I/O bus. It
contains control word register and command word register that stores various control
formats for the device functional description.

44
Transmit Buffer:
The transmit buffer accepts parallel data from the CPU, adds the appropriate
framing information, serializes it and transmits it on the TxD pin on the falling edge of
TxC .
It has two registers: A buffer register to hold eight bits and an output register
to convert eight bits into a stream of serial bits. The CPU writes a byte in the buffer
register, which is transferred to the output register when it is empty. The output
register then transmits serial data on the TxD pin.
In the asynchronous mode the transmitter always adds START bit, depending
on how the unit is programmed, it also adds an optional even or odd parity, and 1,
1½ or 2 stop bits. In synchronous mode, no extra bits (other than parity, if enable)
are generated by the transmitter.
Transmit control
It manages all activities associated with the transmission of serial data.
TxRDY (Transmit Ready):
This output signal indicates CPU that buffer register is empty and the USART
is ready to accept a data character. It can be used as an interrupt to the system or
for polled operation; the CPU can check TxRDY using the status read operation.
This signal is reset when a data byte is loaded into the buffer register.
TxE (Transmitter Empty):
This is an output signal. A high on this line indicates that the output buffer is
empty. In the synchronous mode, if the CPU has failed to load a new charter in time,
TxE will go high momentarily as SYNC characters are loaded into the transmitter to
fill the gap in transmission.
TxC (Transmitter Clock):
This clock controls the rate at which characters are transmitted by USART. In
the synchronous mode TxC is equivalent to the baud rate and is supplied by the
modem. In asynchronous mode TxC is 1, 16, or 64 times the baud rate. The clock
division is programmable. It can be programmed by writing proper mode in the mode
set register.
Receiver Buffer:
The receiver accepts serial data on the RxD line, converts this serial data to
parallel format, checks for bits or characters that are unique to the communication
technique and sends an assembled character to the.
When 8251 is in the asynchronous mode and it is ready to accept a character,
it looks for a low level on the RxD line. When it receives the low level, it assumes
that it is a START bit and enables an internal counter. At a count equivalent to one-
half of a bit time, the RxD line is sampled again.
If the line is still low, a valid START bit is detected and the 8251 proceeds to
assemble the character. After successful reception of a START bit, the 8251
receives data, parity and STOP bits and then transfers the data on the receiver input
register. The data is then transferred into the receiver buffer register.

45
 In the synchronous mode, the receiver simply receives the specified number
of data bits and transfers them to the receiver input register and then to the receiver
buffer register.
Receiver control:
It manages all receiver related activities. Along with data reception, it does
false start bit detection, parity error detection, framing error detection, sync detection
and break detection.
RxRDY (Receiver Ready)
This is an output signal. It goes high when the USART has a character in the
buffer register and is ready to transfer it to the CPU. This line can be used either to
indicate the status in the status register or to interrupt the CPU. This signal is reset
when a data byte from receiver buffer is read by the CPU.

RxC (Receiver Clock):

This clock controls the rate at which the character is to be received by USART
in the synchronous mode. RxC is equivalent to the baud rate and is supplied by the
modem. In asynchronous mode RxC is 1, 16 or 64 times the baud rate. The clock
division is programmable. It can be programmed by writing proper word in the mode
set register.
SYNDET/BRKDET:
When the 8251 is operating in asynchronous mode, a high on this pin
indicates an intentional break in data transmission or a break in the signal line. This
pin goes high if serial data input line RxD stays low for more than two consecutive
stop bit sequences.
When the 8251 operates in synchronous mode, this pin will go high if the
8251 finds a specified sync character(s) in the incoming string of data bits.
Modem control:
The 8251 has a set of control inputs and outputs that can be used to simplify
the interface to almost any modem. It provides control circuitry for the generation of
RTS and DTR and the reception of CTS and DSR . In addition, a general purpose
inverted output and a general purpose input are provided. The output is labeled DTR
and the input is labeled DSR . DTR can be asserted by setting bit 2 of the command
instruction and DSR can be sensed as bit 7 of the status register. When used as a
modem control signal DTR indicates that the terminal is ready to communicate and
DSR indicates that it is ready for communication.

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Control words of 8251
The control words of 8251 is divided into two functional types
 Mode instruction control word
 Command instruction control word
Mode instruction control word

The instruction can be considered as four 2-bit fields. The first 2-bit field (D1-
D0) determines whether the USART is to operate in the synchronous (00) or
asynchronous mode. In the asynchronous mode, this field determines the division
factor for clock to decide the baud rate. For example, if D 1 and D0 are both ones, the
RxC and TxC will be divided by 64 to establish the baud rate.
The second 2-bit field (D3-D2) determines number of data bits in one
character. With this 2-bit field we can set character length from 5-bits to 8 bits.
The third 2-bit field, (D5-D4), controls the parity generation. The parity bit is
added to the data bits only if parity is enabled.
The last field, (D7-D6), has two meanings depending on whether operation is
to be in the synchronous or asynchronous mode. For asynchronous mode, (i.e.
D1D0 ≠ 00), it controls the number of STOP bits to be transmitted with the character.
In synchronous mode, (i.e. D1D0) = 00) this field controls the synchronizing process.
It decides whether to operate with external synchronization or internal
synchronization and whether to transmit single synchronizing character or two
synchronizing characters.
Command instruction control word
After the mode instruction, command character should be issued to the
USART. It controls the operation of the USART within the basic frame work
established by the mode instruction.
It does function such as : Enable Transmit/Receive; Error Reset and modem
Control.

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Status word of 8251
In the data communication systems it is often necessary to examine the
“status” of the transmitter and receiver. It is also necessary for CPU to know if any
error has occurred during communication. The 8251 Block Diagram in
Microprocessor allows the programmer to read above mentioned information from
the status register any time during the functional operation. Figure shows the format
of status register.

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Interfacing of 8251 with 8085

The figure shows the Interfacing 8251 with 8085 in I/O mapped I/O technique.
Here, RD and WR signals are activated by CPU when IO/M signal is high, indicating
I/O bus cycle.

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3.5 Analog to Digital Converter
The ADC0808 Pin Diagram and ADC 0809 are monolithic CMOS devices with
an 8-channel multiplexer. These devices are also designed to operate from common
microprocessor control buses, with tri-state output latches driving the data bus.
Features of ADC0808
 8-bit successive approximation ADC
 8-channel multiplexer with address logic
 Conversion time 100 μs
 It eliminates the need for external zero and full-scale adjustments
 Easy to interface to all microprocessors
 It operates on single 5V power supply
 Output meet TTL voltage level specifications
Pin diagram of ADC0808

ADC 0808/0809 has eight input channels, so to select desired input channel,
it is necessary to send 3-bit address on A, B and C inputs. The address of the
desired channel is sent to the multiplexer address inputs through port pins. After at
least 50 ns, this address must be latched: This can be achieved by sending ALE
signal.
After another 2.5 μs, the start of conversion (SOC) signal must be sent high
and then low to start the conversion process. To indicate end of conversion ADC
0808/0809 activates EOC signal. The microprocessor system can read converted
digital word through data bus by enabling the output enable signal after EOC is
activated.

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Timing diagram of ADC0808

Interfacing of ADC 0808 with 8085

The figure shows interfacing of ADC 0808 with 8085 using 8255. ADC 0808
has eight input channels, so to select desired input channel, it is necessary to send
3-bit address on ADC, ADB and ADA inputs. The address of the desired channel is
sent to the multiplexer address inputs through PB0 to PB2 lines.
After at least 50 ns, this address must be latched. This is achieved by sending
ALE signal using Tort line PB3. After another 2.5 μs the start of

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conversion signal (SOC) must be sent high and then low. Port line PB4 is used for
this purpose. The end of conversion (EOC) is detected by port line PC0.
The Fig. shows timing wave forms for the ADC 0808. Schmitt-trigger inverter
circuitry generates 300 kHz clock which is required to operate ADC 0808. The zener
diode and LM 308 amplifier circuitry is used to produce a V CC and +VREF of 5.12 V for
the A/D converter. With this reference voltage the A/D converter will have 256 steps
of 20 mV each.

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3.6 Digital to analog converter
The DAC0830 Digital to Analog Converter is an advanced CMOS 8-bit DAC
designed to interface directly with the microprocessors. A deposited silicon-
chromium R-2R resistor ladder network divides. the reference current and provides
the circuit with excellent temperature tracking characteristics (0.05% of Full Scale
Range maximum linearity error over temperature).
The circuit uses CMOS current switches and control logic to achieve low
power consumption and low output leakage current errors. Special circuitry provides
TTL logic input voltage level compatibility. Double buffering feature allows this DAC
to output a voltage corresponding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number of DACs.
The DAC0830 Digital to Analog Converter series
(DAC0830/DAC0831/DAC0832) are the 8-bit members of a family of
microprocessor-compatible DACs. For applications demanding higher resolution, the
DAC1000 series (10-bits) and the DAC1208 and DAC1230 (12-bits) are available
alternatives.
Features:
 Double-buffered, single-buffered or flow-through digital data inputs.
 Easy interchange and pin-compatible with 12-bit DAC1230 series.
 Direct interface to all popular microprocessors.
 Built-in facility for zero adjustment.
 Works with ± 10V reference voltage.
 Can be used in the voltage switching mode.
 Logic inputs which meet TTL voltage level specifications.
 Operates “STAND ALONE” (without up) if desired.
 Available in 20-pin small-outline or molded chip carrier package.
Pin diagram

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Functional Block Diagram

A most unique characteristic of this DAC is that the 8-bit digital input byte in
double-buffered, as shown in the Fig. This means that the data must transfer through
two independently controlled 8-bit latching registers before being applied to the R-2R
ladder network to change the analog output. The addition of a second register allows
two useful control features. First, any DAC in a system can simultaneously hold the
current DAC data in one register (DAC register) and the next data word in the
second register (input register) to allow fast updating of the DAC output on demand.
Second, and probably more important, double-buffering allows any number of DACs
in a system to be updated to their new analog output levels simultaneously via a
common strobe signal.
Timing Diagram
The ILE pin is an active high chip select which can be decoded from the
address bus as a qualifier for the normal CS signal generated during a write
operation. This can be used to provide a higher degree of decoding unique control
signals for a particular DAC, and thereby create a more efficient addressing scheme.

Another useful application of the ILE pin of each DAC in a multiple DAC system is to
tie these inputs together and use this as a control line that can effectively “freeze” the
outputs of all the DACs at their present value. Pulling this line low latches the input
register and prevents new data from being written to the DAC. This can be

54
particularly useful in multiprocessing systems to allow a processor other than the one
controlling the DACs to take over control of the data bus and control lines. If this
second system were to use the same addresses as those decoded for DAC control
(but for a different purpose) the ILE function would prevent the DACs from being
erroneously altered.

Analog output
In the case of the DAC0830 Digital to Analog Converter, the output, I OUT1, is a
current directly proportional to the product of the applied referenced voltage and the
digital input word. For application versatility, a second output, Ta rn, is provided as a
current directly proportional to the complement of the digital input. Basically:

where the digital input is the decimal (base 10) equivalent of the applied 8-bit
binary word (0 to 255), VREF is the voltage at pin 8 and 15 kΩ is the nominal value of
the internal resistance, R, of the R-2R ladder network.
Typical Connection

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 DAC0832 takes in parallel 8 bit data from a microcontroller or microprocessor
and converts that data in to analog signal at the output. This analog signal is the
current quantity that is directly proportional to the input digital value and this current
parameter needed to be converted in to voltage parameter for further use. So to
convert the current parameter in to voltage parameter we will use op-amp circuit as
shown in circuit diagram. This op-amp circuit is called current-to-voltage converter.
The analog voltage output from the op-amp circuit is in direct relation with
inputted digital value and hence DAC conversion with DAC0832 is achieved.
Applications
 Microprocessor interface
 Analog and digital circuits
 Electrical measurements
 Audio conversion
 Hobbyist applications
Interfacing of DAC 0808 with 8085

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