Arithmetic Operations

Binary Arithmetic Binary Addition

Add 1011112 and 10111 S C

eg d D 10 0 0
die d

0 1 1 11 Otl I O

I O I l l

Ito 1 0

11 1

1 00 0 1 1 0 0 p

171 0 0 1

11 1 1 1

Add 110101 and 1110k

1O I O
d
leg

0 1 001 0

Binary Arithmetic Binary subtraction

R Borrow

Eg Subtract 10101 from 101010

B B O 0 0 0

0 0 1 O I O

I I 0 0

Eg Subtract b 1101 from I 00000

0 1 needsto borrow

Fööö

the nearest 1 auch The pinkcolored Olsand

on the way all 0 s Is inne exampleis

O o r I will get complemented after borrowing die 1 from

if any MSB

I I O l l

Binary Multiplication

1 0 1 0
1 1 1 1

o o o o

0 1 0 1 1
1 1 1 1

0 0 0 o o o
00 0 0

I O l O l l

1 1 0 1 01 1 1 0

1 0 0 1 0 1 1

Binary Division I Ioi to 110

1011101 110

1 1 0g 1 1 0 1 I O

I l

II 0 1 0 1 1 1 0 1

01 I D I l o

l l O

0 10 1 1

1 1 0

i Quotient Ikt 0 I 0

Reminder 010

0 0 1

Complement A binary numbers

Is complement Inversion of individual bits

2 s complement Add L to the LSB of is complement

Eg Given number is 1 0 1 0 1 0 1

1s complement O I O I O I O just inversethe given

number

2s complement O l O I O I O t

O I O l O l l Add I to LSBof Is

complement

Subtraction of two numbers using 2 s complement method

Given M 1 1 0 1 0 1 1 0

n 0 1 0 00 1 0 1

Find 2 s complement An

M 10 1 1 1 01 1

add Mtn 1 1 0 1 0 1 1 0

11
0 1 1 1 0 1 1

D 1 0 0 1 0 0 0 1

sincetheeis carry

discard it
and aus is 1 0 0 1

00011

Tofindumf

Find 2s complement AN M 00 1 I t

o_0
Add Dtm
01005inch

l t t l l l

no any is

generated find again 2s complement of answer

ie ans 1 00 1 0 0 0 0

Thefinalanswer is 1 001

00011

0in

The basic logical operation im

digital logic is

derived from Boolean Laws

These operations are Logical AND OR e NOT

Y A AND B AB AND operation

Y A OR B ATB OR operation

Y Ä not operation

Bodean.ddenktiescla

AA

OAIdeutityl.NU
l Law A Atl 0 0

ßyµeuf w aA A AA

1 A.A n 0 at

commutahwelaWA.Bn.BA A BtA

Associative Law ABc ALB G B At t C

ct.at f

Absorption Law A.CATB A At AB A

D LWA.tt AT AB

Prove the following

Truth table

I At AB A
A B AB AHAB

solution At AB D It B A I A o o o

O I
I O

From the first and last

I I I I
column of trutertable wen

SeeHat AandAxABaesame


2 AtÄB ATB A ÄB A HB AB HB

A AB FB

AB AB A ÄB ATB

00 0 0 0 D A 1Ä B ATF

0 1 1 1 1

1 0 0 1 1 At B

I I 0 1 1

Earn the truth table since last two columns are identical

we can concludethat A ÄB AFB

3 A BC At B Htc

4 B A c AA Act AB BC distributive
usingcommutative

T and Law

ATAC 1 AB 1 BL

A Itc AB BL

A AB BC

A HB BL

Atzt

alternate method using truth tabk

A BA CA BCA BCA.CI

Observing them

0 0 0 0 0 0 0 0 last two columns

0 0 1 0 0 1 0 0

0 1 0 0 1 0 0 0 We can conclude

out

O O O I 1 1 1

1 0 1 0 1 1 1 1 AtBC B A

1 0 0 1 1 1 1

I I
1 1 1 1

ABC 1 ABI t ABE ABT AL

ABC AB TABE ACCB 5 c ABE AC e AB C

ACC c B

A AB 1A

HALFADDE.IR

Half adder adds two bits

The truth table at half adder is

Outputs

Inputs Observing the truth table

A B S
g A B A x on B

0 0

c a

0 1 1 0

1 0 1 0

I A Sum A B

1 0

HALF
ADDER

B Carry A B

Realization of Half adder

A B
wing gates Realisation of half adder

using basic gates

Es an

DIFFÄ

A TAB

Full adder

A Full adder adds 3 bits the third bit is generally

the carry generated during the addition process

The truth table of the full adder is shown below

Inputs output

A B ei s From the truth table

0 0 0 0 0
after simplification we get

0 0 1 1 0 5 A B Ci

Ba an a

1 0 0 1 0

1 1

0 1 0
1 0 0 1

1 1 1 1 1

Proof of S A B Ci

Frau fruthndable s A B Cit A Bei ABE ABC

taking Ci and I common we can write

S B AB Cit GÄB AB E

T t

t z

ifz AB AB.ie
AtOBZ

AB AB AT3 AI unng Delemorgans theorem

4 5 A B

RÄTABtAB BB

AB

AB.is
Zi

The basic memory element is a Latch SRLatch

Simple hatch circuit

EDT

it outand b O

at first q O g L

a D 0 q O g

aiq lb qn Dg.no g

äämändäqston

Basic Communication System 18.2

Elements Namen
System
 mobile phone 918.32
Principles of operations of