REVISION

Fall 2020
 All Logic Functions of Two Variables

• 16 possible functions of 2 input variables:

– 2^(2^n) = functions of n inputs
22
n

x F Map 1st
y row to 23

xy F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F

0 0Y 0 0 0 0 0 0 0 0 1 1 1 –F15 ) 1 1 1 1
0 10 0 0 0 0 0 0 0 0 1 1 1 1
X 16 possible functions (F0

1 1 1 1
0 1 00 00 10 10 01 01
0 0 0 0 0 1 1 1 1 0 0 0 0

0 1 1 0 0 0 0 1 1 1 1
1
1 0 0 0
1 1 0
1 1 0 0 1 1 0
0
0
1
1
1
1
0
0
0 1 1

11 11 00 11 00 11 00 11 00 11 0 1 0 1 0 1 0 1
0 X Y X xor Y
not Y not X 1 Map last
X and Y
X=Y X nand Y Row to 20

X or Y X nor Y not (X and Y)

not (X or Y)
Digital Logic Gates
Sum of Product (SoP) Representation

• We can uniquely define a logic function A Logic F

using its truth table B Circuit
• Focusing on the terms where the function C F(A,B,C)
evaluates to TRUE min-

– We can represent the function by Oring term A B C F

all input combinations that evaluate to (m0) 0 0 0 0
TRUE (m1) 0 0 1 0
(m2) 0 1 0 1
(m3) 0 1 1 1
(SoP): F = ABC + ABC + ABC + ABC (m4) 1 0 0 0
Sum of minterms: F = m2 + m3 + m5 + m7 (m ) 5
1 0 1 1
F=Σ(2,3,5,7) (m6) 1 1 0 0
(m7) 1 1 1 1
Map to 22 Map to 20
Karnaugh Maps

• Karnaugh map is a graphical representation of a truth

table of a logic function.
• Each line in the truth table (minterm) corresponds to
a square in the Karnaugh map.
• The Karnaugh map squares are labeled so that
horizontally or vertically adjacent squares differ only in
one variable. (Each square in the top row is considered
to be adjacent to a corresponding square in the bottom
row. Each square in the left most column is considered
to be adjacent to a corresponding square in the right
most column.)
ABC 00 B 011 111
01 11 10 010 110
0 0 1 3
001
2
B C 101
A 1 4 5 7 6
000
A
100
C
 Karnaugh Maps – 4 Variables
Map to 23 Map to 23 2 21
2
22 21 20 20
Numerical equivalent of logic combinations ABCD
msb and D = lsb

C
AB C D F
AB CD 00 01 11 10
0 0 1 3 2
() 0 0 0 0 ... 00
1
() 0 0 0 1 ... 4 5 7 6
2
() 0 0 1 0 ... 01
3 B
() 0 0 1 1 ... 11 12 13 15 14
4
read as binary values with A =

() 0 1 0 0 ... A 10 8 9 11 10
5
() 0 1 0 1 ...
6
() 0 1 1 0 ... D
7
() 0 1 1 1 …
8
() 1
9
0 0 0 … The minterms are listed by an
() 1 0 0 1 …
10
( )1 0 1 0 … equivalent decimal number for
11
( )1 0 1 1 … easy reference
12
( )1 1 0 0 …
13
( )1 1 0 1 …
14 1 1 0 …
( )1
15
( )1 1 1 1 ...
The Uniting Theorem

• Key tool for simplification: A (B' + B) = A

where A can be a product term of any other
input variables
• Essence of simplification:
– Find two element subsets of the ON-set where only
one variable changes its value – this single varying
variable can be eliminated and a single product
term used to represent both elements

A B F F = A'B'+AB' = (A'+A)B' = B'

B has the same value (0) in both on-set rows
0 0 1
=> B remains in the expression of the product term
0 1 0
1 0 1 A has different values in the two
1 1 0 rows => A is eliminated
Implicants & Graphic Representation

• Given a logic function z = f(x0, x1, x2, …)

• Implicant = product term that, if equal to 1, implies f = 1
– whenever the implicant is 1=> f = 1
– f can be 1 other times, as well: it may be implied by other
implicants
– from the K-map point of view, an implicant is a rectangle
of 1, 2, 4, 8, … (any power of 2) 1’s of adjacent squares
• Prime Implicant (PI): the largest possible k-cube
for which f = 1
– cannot be totally covered by another implicant
Logic Minimization using K-Maps

• To obtain the SoP of Fmin (the minimized F), one has to

find the minimum set of PI’s which covers F as follows:
1. Represent the given function F on a K-map
2. Find the PI set of the function F
3. Mark with * all K-map cells that contain a 1 which
is covered by only a single PI; each PI that
contains a * is an EPI. Include all EPI’s in the
minimal set which covers the function.
Logic Minimization using K-Maps

• To obtain the SoP of Fmin (the minimized F), one has to

find the minimum set of PI’s which covers F as follows:
4. Remove from the K-map the EPI’s and the 1’s they
cover, then apply step 3 onto the remaining 1’s
and PI’s, to find the secondary EPI’s.
5. Repeat step 4 until no higher order EPI’s are
found. Then find a minimum set from the rest of
the non-EPI prime implicants that cover the
remaining 1's on the map, then add them to the
minimal set which covers the function.
Incompletely Specified Logic Functions

• Don't care terms can be treated as 1’s or 0’s, depending on

which one is more advantageous.
• don't care should be included in the group if including a
don't care in the group makes
1. the group bigger, or
2. makes it possible to reduce the number of groups,
 Incompletely Specified Logic Functions
F 0,1,3,7,8,12 dc(5,10,13,14) dc -> x = don’t care terms
Don't care terms can be treated as 1’s or 0’s,
AB C D F depending on which one is more advantageous.
(0) 0 0 0 0 1 So, if including a don't care in a group makes
(1) 0 0 0 1 1 1. the group bigger, or
(2) 0 0 1 0 0 2. makes it possible to reduce the number of groups, the
(3) 0 0 1 1 1 don't care should be included in the group, but not otherwise!
(4) 0 1 0 0 0 CD Secondary
(5) 0 1 0 1 x 00 01 11 10 AB PI EPI* EPI
(6) 0 1 1 0 0 00 0 1 3 2

(7) 0 1 1 1 1 1 1 1* 0 AD
4 5 7 6 AD
(8) 1 0 0 0 1 01 ABC
0 x 1* 0
(9) 1 0 0 1 0 AD
11 12 13 15 14
(10) 1 0 1 0 x 1* x 0 x
(11) 1 0 1 1 0 8 9 11 10 ABC
10
(12) 1 1 0 0 1 1 0 0 x
(13) 1 1 0 1 x AD BC D
BC D
(14) 1 1 1 0 x ABC
(15) 1 1 1 1 0 Fmin = AD + AD + or
BCD
Combinational Circuits Design

1. Define the problem

2. Assign different letter symbols to the input
and output variables
3. Derive the truth table defining the relationship
between the inputs and the outputs
4. Obtain the simplified Boolean expression for
each output variable
5. Draw the circuit's logic diagram
Sequential Circuits as FSM

• Input set: X={Xi |i=0,m-1} X= {X0,X1,X2,…, Xm-1}

• Output set: Z={zj | j=0,p-1} Z = {Z0,Z1,Z2,…, Zp-1}
• States : S = {Sk | k=0,q-1} S={S0,S1,S2,…, Sq-1}
S(t) Present State S(t)

S(t+Δt)=δ(S(t),X(t)) S(t+Δt) Memory S(t)

Next
State

X(t) Combinational
Circuits Z(t)
Z(t) = λ(S(t),X(t))
Latches & Flip-Flops

• A flip-flop or a latch holds (stores) 1 "bit".

• "Bit" ::= "binary digit.“

S
Q
Q
S
Q Q
R
R

t S R S R Qt+Δt Qt+Δt
311 0 0 0 0 Set
210 0 1 1 0
101 1 0 0 1 Reset
0 0 0 1 1 Qt Q
t Hold
 S Q
S-R Latch BLOCK
R DIAGRAM
STATE TABLE
Presen Next State Q
t+Δt CHARACTERISTIC or EXCITATION
t
State SR FUNCTIONAL TABLE TABLE
t 00 01 10 11 t+Δt
Q t t t t t
0 0 0 1 - St Rt Qt Qt+Δt Q S R Qt+Δt Function Q Qt+Δt S R
1 1 0 1 - 0 0 0 0 1 0 0 Qt Hold 0 0 0 x
0 0 1 1 0 0 1 0 Reset 0 1 1 0
0 1 0 0 1 1 0 1 Set 1 0 0 1
S
Q 0 1 1 0 1 Indeterminate
1 1 x 0
1 1 0? / Forbidden
Q 1 0 0 1 0 (non-sense)
R 1 0 1 1 0 Characteristic Qt t  S t  Qt  Rt
LOGIC 1 1 0 0? 0? Equation: condition : t  t  0
DIAGRAM 1 1 1 0? 0? S R

SR=10
SR=00v01 00v10
STATE DIAGRAM 0 01 1
 JK Flip-Flop

10v11
JK=00v01 00v10
0 1 CHARACTERISTIC or
01v11 FUNCTIONAL TABLE EXCITATION
n n TABLE
J K Qn+1 Function n n n
0 0 n
Q Hold Q Q n+1 J K
0 1 0 Reset 0 0 0 x
1 0 1 Set 0 1 1 x
1 1 Toggle 1 0 x 1
Q
n 1 1 x 0
CHARACTERISTIC EQUATION:
MEV representation
n1 n n n n
Q Q J Q K (Map-Entered Variable)
 D-Latch Enable D S R
0 0 1 1
Q Q
Q
Q
0 1 1 1 Q
Q
1 0 1 0 0 1
1 1 0 1 1 0

S
D Q

Q
δ R
Enable
 Master-Slave D Flop-Flop

D=1 DQ n n n n
D Q Qn+1 Q Qn+1 D
0 0 1 1 0 0 0 0 0 0
CLK
0 Q 0 1 0 0 1 1
STATE DIAGRAM 1 0 1 1 0 0
BLOCK
DIAGRAM 1 1 1 1 1 1
TIME Setup Q n+1 = Dn Dn = Qn+1
DIAGRAM time
Hold There is a timing "window" around the clocking moment during which

time the input must remain stable and unchanged in order to be recognized.
D Din* Input data D may change
CLK 1

0
Propagation
Q time 1
Q = Din* 0
T Flip-Flop

TQ n n n n
T Q Qn+1 Q Qn+1 T
CLK 0 0 0 0 0 0
Q
0 1 1 0 1 1
1 0 1 1 0 1
0 T=1 0 1 1 0 1 1 0
0 1
n n
T=1 Q n1  Q T  Q  T
 Synchronous Sequential Circuits as FSM

• The behavior of sequential circuits can be described

using the Finite State Machine (FSM) model

Mealy FSM Output based on present state

and present input:
Zn = λ(Sn,Xn)
m

s(n)

StateRegister
Next state
x(n) p z(n)
m s(n+1) present λ
Present input state q
clk
 Synchronous Sequential Circuits as FSM

• The behavior of sequential circuits can be described

using the Finite State Machine (FSM) model

Moore Output based on present state

FSM only:
m
Zn =

State
Register
λ(Sn)
Next state s(n) z(n)
x(n) p
δ m λ
Present input s(n+1) present q
clk state
Sequential Circuits Design

1. From the problem specification, create the state

diagram which shows all of the states that the FSM
can be in, and how to switch from one state to another
2. State Table - transition (δ) and output (λ) functions
Make a state table based on the problem specification or
state diagram. It may show the next states Sn+1 and
outputs Zn as functions of present states Sn and inputs Xn
Transition function: Sn+1 = δ(Sn,Xn), output function Zn =
λ(Sn,Xn).
State minimization = reduce the number of states
in the table (not in CEG2136)
Sequential Circuits Design

3. State Assignment (Encoding). Assign binary codes to

the states in the state table, if they were not assigned
already. If you have N states, your binary codes will
have at least log2 N digits, and your circuit will have
at least log2 N flip-flops  Transition table (i.e.,
binary-coded state table) = a state table with encoded
states.
4. Excitation Table and Equations. Choose the type of
flip-flops to be used. For each flip-flop and each row of
your transition table, find the flip-flop input values that
are needed to generate the next state from the
present state. You may use flip-flop excitation tables.
Sequential Circuits Design

5. Find simplified equations for the flip-flops inputs &

the circuit outputs Z.
6. Build the circuit!
MEV K-maps Minimization

• Use K-maps to minimize F = Σ (3,7,11,12,13,14,15,16,18)

+ d(24,25,26,27,28,29,30,31).
• To find the simplified function from a MEV K-map,
5. EPI: Essential
follow these steps:
1. Determine the EPI’s consisting of only 1’s along with
any don't care terms that may exist (i.e., cover the
1’s in the K-map).
2. Consider the 1’s as don't care terms once step 1 is
completed, because all of the 1’s have been previously
covered.
 MEV m a b c d e F MEV m a b c d e F
0 0 00000 0 8 16 1 0000 1
MEV K-maps 1 00001 0 17 1 0001 0
1 2 00010 0 9 18 1 0010 1
3 00011 1 19 1 0011 0
3. Group all identical MEV terms 2 4 00100 0 10 20 1 0100 0
with 1’s or don't care terms 5 00101 0 21 1 0 101 0
– Write the term AND MEV 3 6 00110 0 11 22 1 0110 0
7 00111 1 23 1 0111 0
value 4 8 01000 0 12 24 1 1000 x
9 01001 0 25 1 1001 x
– F = bc + a’de + ac’e’ 5 10 01010 0 13 26 1 1010 x
11 01011 1 27 1 1011 x
cd 00 01 11 10 6 12 01100 1 14 28 1 1100 x
ab
13 01101 1 29 1 1101 x
00 00 e1 e3 02 7 14 01110 1 15 30 1 1110 x
01 04 e 5 1*7 1* 6 15 01111 1 31 1 1111 x

11
x12 x 13 x15 x 14
10 e’8 e’9
011 010
Multi-function Registers

• Bidirectional Shift Register with Parallel Load is the

most general form of register
– It can be loaded and retrieved serially and in parallel
– It has the following capabilities:
1. clock pulse input to synchronize all operations.
2. shift right operation with a serial input line
3. shift left operation with a serial input line
4. parallel load operation with n input lines
5. n parallel output lines
6. A control state to leave the output lines unchanged
Multi-function Registers

Mode Control Serial S S

S1 S 0 Register operation In 1 0

A3
00 No change

Register
I (msb)
1 Shift right (msblsb) 3
A2
10 Shift left (lsb  msb) I2
A1
11 Parallel load I1
A0
I0 (lsb)
 Multi-function RegistersSerialIn S1S0 CL
CK

0
f3 0M D3 Q
f3
1
1U A
3
2 CLK (msb)
f3 2
Q
X3

3
I3 f3 R

f 3 f 2 f 1
f 0
S1 S0 Function I2 D2 Q
0M
2 2 2 2 1 U A2
CLK
2 X3 Q
R
0
(f ) 0 0 No Change=Store
1
(f ) 0 1 Shift Right: direction msb→lsb
2 f 0
(f ) 1 0 Shift Left: direction lsb →msb 1 0M D1 Q
3
(f ) 1 1 Parallel Load DB I1 f 3 f 2
f1
1 1U A1
1 CLK
1 2 X3 Q
R

0M Q
0 D0
f0 1U A0
1 (lsb)
f0 2 X3 CLK
f0
2 Q
R
3
I0 f0
 Memory
Memory A …A A A
N-1 2 1 0

N Address Lines

M Data Lines

• A computer has Central Processing Unit (CPU) and memory.

• The memory stores the program/data and the CPU can
read (extract or fetch) the data from computer memory for
processing, or, it can write (store) the data onto the
computer memory.
• The memory can be seen as a set of registers of the same
length that store binary data, called “words”. Each
memory location (i.e., such a register) stores a word and
has an address.
 Memory
Memory A …A A A
N-1 2 1 0

N Address Lines

M Data Lines

• The computer uses:

– the address lines to locate the specific data word in the
computer memory.
– the data lines to write a word into the memory location
specified by the address lines, or to read a stored word
from a memory location specified by the address lines,
as shown in the figure.
• Address bus is unidirectional CPU → Memory
• Data bus is bidirectional CPU ↔ Memory
Memory Unit

• Memories are collection of registers

together with associated circuits needed to
transfer information in and out of storage.
• The memory stores binary information in
groups of bits called words. Address Location=
• A word in memory may contain any type K bits M bit
of binary information that fits its size (e.g., word
a number, an instruction code, a memory 0000 WORD 0

address, or one or more alphanumeric 0001 WORD 1

characters) 0010 WORD 2
• The internal structure of a memory is
0011 WORD 3
specified by the number of words it contains
… …
and the number of bits in each word.
k
(2 -1)2 WORD 2k-1
Memory Unit

• Each memory location (register) holds

one “word” that
– can be read or written into the memory Address Location=
K bits M bit
– Has a unique address
 addresses are represented as binary word
vectors, consecutively numbered 0000 WORD 0
 if address is encoded with k bits, memory can have
k 0001 WORD 1
a capacity of 2 words
• Data is transferred to/from memory in 0010 WORD 2

multiples of words; it is NOT possible to 0011 WORD 3

read or write partial word … …

• One can access memory using only one k
(2 -1)2 WORD 2k-1
address at a time, while simultaneous
readings and writings are not possible
Memory Capacity

• Capacity = memory size = amount of data (measured

in bits, bytes, words) stored in a memory.
– Memory Size = N x M
Address Location=
– N: Number of words K bits M bit word
A
– M: word size in bits A
K-1
D 0000 WORD 0

– K: the address size in bits …… E 0001 WORD 1

A2
– N=2K A1
C 0010 WORD 2

• Example 1 KB memory: 1024 x 8 A0

O 0011 WORD 3

D
• K = log2(1024) = 10 bits … …

• M = 8 bits E K
(2 -1)2 WORD N-1= 2K-1

D DD
M-1 …… 1 0
ADDR ADDR A A A A A A A A A7 A6 A5 A4 A3 A2 A1 A0 D D D D D D D D D7 D6 D5 D4 D3 D2 D1 D0
15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8
(HEX)
0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RAM 0,3 RAM 0,2 RAM 0,1 RAM 0,0
… … … … … 1KX4 1KX4 1KX4 1KX4
1023 03FF 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
1024 0400 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
1025 0401 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 RAM 1,3 RAM 1,2 RAM 1,1 RAM 1,0
… … … … … 1KX4 1KX4 1KX4 1KX4
2047 07FF 0 0 0 0 01 1 1 1 1 1 1 1 1 1 1
2048 0800 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
2049 0801 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
… … … … …
0BFF 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 EEPROM 1 EEPROM 0
0C00 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 2K X 8 2K X 8
0C01 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1
…
4095 0FFF 0 00 0 11 1 1 1 1 1 1 1 1 1 1

Basic Computer MemoryD D D D 15 14 13 12

D D D D
11 10 9 8
D7 D6 D5 D4 D3 D2 D1 D0
A9-A0
CS0 RAM 0,3 RAM 0,2 RAM 0,1 RAM 0,0
S0 1KX4 1KX4 1KX4 1KX4

S1 CS1 RAM 1,3 RAM 1,2 RAM 1,1 RAM 1,0

A9-A0
1KX4 1KX4 1KX4 1KX4
E
S + CS A10-A0
EEPROM 1 EEPROM 0
+ 2

A A S 2K X 8 2K X 8
11 10 3
A -A
15 12
 Unsigned Numbers

• Unsigned binary number of n-bits is in the

range [0, 2n-1] – Example 4-bit binary number
3 0011 1111 0000 0001
1110
+4 +0100 0 0010
15 1
7 0111
1101 14 2 0011
8 1000 13 3

+ 9 +1001 1100 12 4 0100

17 1 0001 11 5
When the result of
1011 10 6 0101
operation is
causing overflow, the 9 8 7
carry bit is set
1010 0110
1001 1000 0111
 2’s Complement of a Number

• 2’s complement of a number P = 2n – P

Since a rotation of 2n 1111 0000 0001
brings back to point

0, doing (2’s complement 1110 0 0010

of a number P)
= – P (negate P) -1 +1
Hence, one can find 1101 -2 +2 0011
negative P by
complementing P -3 +3
1100 -4 +4 0100

-5 +5

1011 -6 +6 0101
-7 -8 +7
1010 0110
1001 1000 0111
Signed numbers

• When a signed number is negative, the sign bit

assumes a value of 1 while the rest of the number may
be represented in one of three possible ways:
1) Signed magnitude representation
2) Signed 1’s complement representation
3) Signed 2’s complement representation
• Example: represent -14 with 8 bits, including the
sign bit:
1) In signed magnitude form, −14 is represented as: 10001110 .
2) In signed 1’s complement form, −14 is represented as: 11110001.
3) In signed 2’s complement form, −14 is represented as: 11110010.
2’s Complement Representation
Detection of Addition Overflow

• Overflow means that the result is out of range

• An overflow in an addition operation can be detected
• For unsigned numbers in the range [0, 2n-1], if
the carry-out of the most significant bit has a value
of 1, that means an overflow has occurred
• For 2’s Complement Representation of Signed
numbers in the range [-2n-1, 2n-1-1] an overflow is
signalized :
1. if the addends have the same sign, but the sign
of the sum is different than the addends’ sign; or
2. if the carry into the sign bit position and the
carry out of the sign bit position are different,.
Floating-Point Representation

• A floating-point is always interpreted to represent

a number in the following form:
e
 mxr
• Only the mantissa m and the exponent e are
physically stored in registers (including their signs).
• The radix and radix-point position in the mantissa are
supposed to be known (fixed for a given hardware).
• A floating-point number is said to be normalized if the
most significant digit (excluding the sign bit) is non-zero
• +1001.110 with an 8-bit mantissa and a 6-bit exponent:

copy Mantissa Exponent

01001110 000100
Count digits after floating
point (4)
IEEE 754 Standard

• Most common standard for representing floating

point numbers
• Single precision: 32 bits, consisting of...
• Sign bit (1 bit)
• Exponent (8 bits)
• Mantissa (23 bits)
• Double precision: 64 bits, consisting of…
• Sign bit (1 bit)
• Exponent (11 bits)
• Mantissa (52 bits)
 IEEE 754 Standard – 32b Single Precision
31 30 29 28 27 26 25 24 23 22 21 2 1 0

Sign bit S Exponent E Mantissa

m
(1 bit) (8 bits) (23 bits)

Range: [-2128, 2128]  [-1012, 1012]

IEEE 754 Standard – 32b Single Precision

• Sign Bit: 0-positive, 1-negative

• Exponent:
– using unsigned number
– biased by adding 127 to the actual value
• Mantissa:
– normalized, if 255 > exponent > 0
 the first bit of mantissa (not shown), assumed 1

– de-normalized, if exponent = 0 & mantissa ≠0,

– +/- 0, exponent = 0 , mantissa = 0
– +/- infinity, exponent = 255, mantissa = 0
– NaN, exponent = 255, mantissa is not 0
 IEEE 754 Standard – 32b Single Precision

• Example: -0

• Example: 0.15625

2- . 0.15625
0 0.3125
3 0 0.625
Impli 1 0.25
cit! 0
1
0.5
0
-3
(0.15625)d = (1.01 x 2 )b
IEEE 754 Standard – 32b Single Precision

• Express 36.562510 as a 32-bit floating

point number?
Express original value in binary
36.562510 = 100100.10012
Normalize
100100.10012 = 1.0010010012 x 25
Put S, E, and M together to form 32-bit binary result

0 10000100 001001001000000000000002
S E = 5+127 M
IEEE 754 Standard – 32b Single Precision

• What decimal value is represented by the

following 32-bit floating point number?
C17B000016
– Express in binary and find S, E, and M

C17B000016 =
1 10000010 111101100000000000000002
S E M
Real Exponent n = E-127 Real Mantissa m =
= 100000102 – 127 = 1.11110112
1 = negative =130–127=3 = 1.9609375
0 = positive
Answer = - 1.9609375 x 23 = -15.6875
 Write
Memory
Din Addr Dout 16 7 Common Bus Read

LD 16
Memory
Din Addr Dout
16
7
AR
•A typical digital computer
AR 12 1
system contains a large number AR 12 1
of registers. 12
LDPC
•The number of wires will be
PC 12 2
excessive if separate wires are 12 PC 12 2
used to connect each register 16 Select
LDIR
16 5 to all the other registers. 5
IR IR Source
•A more efficient scheme of 16

DR BUS transferring information LDDR

between registers is a common
16 DR 16 3
bus system. 16
3
4 •A bus structure consists of
16 common lines, one for each bit of ALU 4
AC a register, through which binary LDAC
16
16 AC
information is transferred.
•Control signals, or bus selection
INPR 8 path

BUS
bits, determines which register is Data INPR
selected by the bus during each 16 6 Sel
TR
16 6
particular register transfer. LDTR TR
TRAC 16
(destination  source) 8
OUTR
OUTR S2-S0 49
8 LD
Select Destination OUTR
 D0
Write Memory B
A
D1 Read Din Addr Dout 7
I
14 D2
I LDAR AR
S
13 D3
I D INRAR
12
D5
4
X 12 1
CLRAR

I
3-to-8 D6 input
Other decoder D LDPC PC
C
7 12 2
inputs INRPC
CLRPC
Combinational
Control Circuits LDIR IR 16 5

C
(Control logic
Unit gates) LDDR DR

BUS

O
INRDR
T0 output
Fetch
T1 CLRDR 163

M
T2 ALU 4
4-to-16
T3 present
16
state
P
decoder … LDAC AC
… INRAC
Exec T14

U
CLRAC
T
15
Data INPR
4-bit INRSC

LDTR
path
T
E
sequence
Counter CLRSC Clock INRTR TR CLRTR 16 6 Sel
(State Register) next

R
LD
state OUTR OUTR
S2-S0
Arithmetic microoperations

• The microoperations most often encountered in

digital computers are classified into four categories:
• Register transfer microoperations: they transfer
binary data from one register to another.
• Arithmetic microoperations: they perform arithmetic
microoperations, such as additions and subtractions for
instance, on digital data stored in registers.
• Logic microoperations: they perform bit
manipulation operations on data stored in registers.
• Shift microoperations: they perform shift operations
on data stored in registers.
 Combined Addition/Subtraction Op

 For signed numbers,

 When M = 0 (addition micro-operation),⊕ Sn−1 . . . S1 S0 gives the result of (A + B ). An
overflow occurs when Cn ⊕ Cn−1 = 1.
 When M = 1 (subtraction micro-operation), Sn−1 . . . S1 S0 gives the result of (A −
B ). An overflow occurs when Cn Cn−1 = 1.
 Select Bits Output = R Micro-operation
RRR +S SSS
S1 S0 Cin D =R+S+Cin Add n-1… 2 1 0 n-1… 2 1 0
000 D=A+B =A AAA +B BBB
Op.0 001 D = A+B+1 Add with carry = A n-1… 2 1 0 n-1… 2 1 0
AAA +B B B B +00000001
n-1… 2 1 0 n-1… 2 1 0
010 D = A−B−1 Subtract with borrow A AAA +B’
B’ B’ B’
Op.1 011 D=A−B Subtract =A n-1… 2 1 0 n-1… 2 1 0
AAA +(B’ B’ B’ B’ + 0000 0001)
100 D=A Transfer A n-1… =A
2 1 0 n-1… 2 1 0
A A A + 0000 0000
Op.2 101 D=A+1 Increment A = A n-1…A2A A +10000 0
0000 + 0000 0001
n-1… 2 1 0

Op.3 110 D=A−1 Decrement A = A + 2’s Compl(1) = A + 1111 1111

111 D=A Transfer A = A + 1111 1111+0000 0001
C S S C in S 2 =AC’/LSC B i A i S
in 1 0
Ai C
1 S 0 in
Op0 Σ
Bi

C
in
Ai
Op1 Σ
Bi

C i 0

FALU
S
0 FALU
in 1 S0
MUX
ALU i

Ai C F Op.4 0 1 S S 1
in0
Op2 2 1 0
Op.5 1
Op2 Σ C E= FLSC
F

0 out0 Op.4 0

Op.6 2 Op.5 1 E=
C LSC
Ai
in
C Op.7 3 Op.6 2 F
in0 3 LSC i
Op3 Σ FOp3
53 3 LSCi
1 C Op .7
out0
Logic Circuit (LC)

• The circuit performing a set of logic

microoperations is called a logic unit,
or a logic circuit (LC).
• An n-bit logic unit that can perform 2k
logic operations on two n-bit registers
A and B is composed of:
− Two n-bit input lines for A and B
− n multiplexers of type 2k × 1, with each
multiplexer operating on one bit from
each register
− The particular logic operation to be
performed is chosen by the k selection
bits that are common to all n LC
multiplexers.
Shift microoperations

• There are three types of shift microoperations:

1. logical shift,
2. circular shift, and
3. arithmetic shift
The following is a list of the different shift
microoperations and their notations:
Symbolic designation Description
R ← shl R Shift-left register R
R ← shr R Shift-right register R
R ← cil R Circular shift-left register R
R ← cir R Circular shift-right register R
R ← ashl R Arithmetic shift-left register R
R ← ashr R Arithmetic shift
.
 S 2 the logic unit (LC) if it simplifies the design (LSC).
ALSU(for 8 bits) S1 S0
• It may be convenient to merge the shift unit (SC) with

AC7
Select Bits Output
A7
C
SSSC in F in7
2 1 0 ALU C =C

F
0000 FAC = A+B 0 Σ in 0
7

AC1
0001 FAC = A+B+1 A 1 S1 S0
Cout7 A1
1
0010 F = A−B−1 C in1

F
AC

0011 AC = A−B 0 2
0
F A Σ
AC7 A0

AC0
0100 F =A C
0 1

in0

F
AC 3 1 C
0101 F = A+1 out1

AC 0
0110 F = A−1 0 2 Σ0
0111 AC = A
S1 S0
F
AC 3 1 C

AC1
out0

100x FLSC = A B 1
101x ∧ B 0 0 0 2 0
FLSC=A
∨ S S AC0

ALU7
110x 1E= FLSC7 1 1 3 1

ALU0
FLSC = shift left B7 1 0
111x FLSC = shift right A6 2 0 0
F
F

F
ALU0 S1 S0
B1 SerIn 3 1E= FLSC1
AC LSC7 B1 A0 2 1 0
B
0 1E= F
LSC0
3 B0
A2 LSC1 SerIn 2
Another way of implementing an ALSU
LC
is to build: - one full arithmetic unit (AC) A1 3
− one full logic unit (LC), and
LSC0
− one full shift unit (SC)
and pass the outputs of all the units to a multiplexer that will select the final output
depending on the values of its selection bits.
 Symbol I=0 I= 1 Description

Instruction Set
MRI
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
Memory Reference Instructions BUN 4xxx Cxxx Branch unconditionally
dominate the instruction set: BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero
– Divided equally between RRI
Direct/indirect memory CLA 7800 Clear AC
CLE 7400 Clear E
addressing CMA 7200 Complement AC

– Direct memory addressing CME

CIR
7100
7080
Complement E
Circulate right AC and E
use refers to data in CIL 7040 Circulate left AC and E

memory INC
SPA
7020
7010
Increment AC
Skip next instruction if AC positive
– Indirect addressing refers SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
to address in memory SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
IOI
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
lOP F040 Interrupt off
 Symbol
Instruction Set
I=0 I= 1 Description
AND 0xxx 8xxx AND memory word to AC

MRI
ADD 1xxx 9xxx Add memory word to AC

LDA 2xxx Axxx Load memory word to AC

There are 3 instruction formats. STA 3xxx Bxxx Store content of AC in memory
BUN 4xxx Cxxx Branch unconditionally
The opcode is composed of 3 bits BSA 5xxx Dxxx Branch and save return address
[14:12] ISZ 6xxx Exxx Increment and skip if zero
000~110 = 6 operations to be RRI 7800 Clear AC

performed on AC CLA
CLE 7400 Clear E
the rest of the 12-bits [11:0] specify CMA 7200 Complement AC
an address in memory: CME 7100 Complement E

If bit[15]=0, direct address CIR 7080 Circulate right AC and E

If bit[15]=1, indirect address CIL 7040 Circulate left AC and E

INC 7020 Increment AC
bit[15:12]=0111, register reference SPA 7010 Skip next instruction if AC positive
instruction, bit[11:0] used to specify the SNA 7008 Skip next instruction if AC negative

type of operation to be performed SZA 7004 Skip next instruction if AC zero

SZE 7002 Skip next instruction if E is 0
bit[15:12]=1111 input-output HLT 7001 Halt computer
instruction, bit[11:0] used to specify the IOI
type of operation to be performed INP F800 Input character to AC
UT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
lOP F040 Interrupt off
 Instruction Set (binary)
D7 Instr. Addressing Mode op code
Dec I I I
I I I I I I I I I I I I
I15=0 I15=1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MRI Direct Addr. MRI Indirect Addr. Me mo ry A D D R E S S

D 0
AND=$0addr AND =$8(addr) 0 0 0 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1
i
AR0
D 1
ADD=$1addr ADD =$9(addr) 0 0 1 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1
i
AR0
D LDA =$2addr LDA =$A(addr) 0 1 0 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
STA =$B(addr) 0 1 1 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1
2 i

D =0
7
D 3
STA =$3addr i
AR0
mem D 4
BUN =$4addr BUN =$C(addr) 1 0 0 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1
i
AR0
D 5
BSA =$5addr BSA =$D(addr) 1 0 1 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1
i
AR0
D 6
ISZ =$6addr ISZ =$E(addr) 1 1 0 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1
i
AR0
RRI IOI 1 1 1 C o d e Ext ension
D
7 CLA =$7800 INP = $F800 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
D7 CLE =$7400 OUT = $F400 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0
D7 CMA =$7200 SKI = $F200 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0
D
7 CME =$7100 SKO = $F100 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0
D7 CIR =$7080 ION = $F080 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0
D7=1 D7 CIL =$7040 IOF = $F040 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0
D
reg 7 INC =$7020 n/a 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0
D7 SPA =$7010 n/a 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0
D
7 SNA =$7008 n/a 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0
D7 SZA =$7004 n/a 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0
D7 SZE =$7002 n/a 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0
D7 HLT =$7001 n/a 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1
Binary encoding One-hot (bit-per-state) encoding “addr” = 12 bit address of the operand
“(addr)” = address of the operand address
Instruction Set Completeness

• A computer instruction set is complete if it can be

used to evaluate any function that is known to be
computable.
• To be complete, the instruction set must contain
enough instructions in each of the following categories:
1. Arithmetic, logic, and shift instructions.
2. Instructions for moving information to and from
memory and processor registers. (load/store)
3. Program control instructions together with
instructions that check status conditions.
4. Input and output instructions
Instruction Set Completeness

• Program control instructions, such as branch

instructions, are used to change the sequence in
which the program is executed.
• Input and output instructions are needed for
communication between the computer and the
user (outside world).
• In this context, the instruction list of the Basic
Computer is complete as it provides enough
instructions in each category.
High Level Division of Instruction Cycle

• We first divide the instruction cycle into 2 major

phases: ASM Level1 (High level of detail)
1. Fetch Phase: T0-T2
2. Execution Phase: T3-T6

T1 T4 T6

EXECUTION
FETCH
T T3 T
T0 2 5
Fetch Cycle – @ ASM Level1

• Fetch instruction from memory location specified by

PC to Instruction Register (IR)
1. T0: AR  [PC] - Transfer contents of PC to
Memory Address Register
2. T1: IR <- [M(AR)] - Fetch instruction =
contents of addressed memory location [M(AR)]
is transferred to the IR
3. T1: PC<-PC+1 - PC incremented to point to
the next instruction
4. T2 Instruction decoded by CU – now that
instruction is in IR
Determine the Type of Instruction

• The following segment of the ASM flowchart for

instruction cycle presents an initial configuration of
the instruction cycle.
RTL
ASM#2
Execution Cycle

• Register-Reference Instructions (PRI)

• Triggered by: I14I13I12 = 111 → D7 = 1, I15 = I = 0
• Start at time T3
• Let Bi = IR[i], i=0,…, 11
• Let r = D7 I’ T3 trigger for all RRIs
 Register-Reference Instructions (PRI)

• Triggered by: I14I13I12 = 111 → D7 = 1, I15 = I = 0

• Start at time T3
• Let Bi = IR[i], i=0,…, 11
• Let r = D7 I’ T3 trigger for all RRIs

reister
1
H
T
0 RTL
O Fetch T1
ASM#2
T T2
E 4-to-16 T3
N State
C Decoder
T4
…
RTL
O Exec T ASM#2
D 14
T
I 15
N
G
4-bit
Sequence
Counter (SC)

Every Register-Reference Instruction is executed during T3

 Memory-Reference Instructions (MRI)

RTL RTL
From the Instruction List: ASM#2
ASM#2

I14I13I12 = [000 – 110] => Di = 1, i = {0 .. 6}

• I15 = I = 0 => direct addressing
• I15 = I = 1 => indirect addressing
Memory-Reference Instructions (MRI)

AND DT: DR M[AR]

0 4
DT: ACAC^DR,SC0
0 5
ADD DT: DR M[AR]
1 4
DT: ACAC+DR,EC
out ,SC0
1 5
LDA DT: DR M[AR]
2 4
DT: ACDR,SC0
2 5
STA DT: M[AR] AC, SC  0
3 4
BUN DT: PCAR,SC0
4 4
BSA DT: M[AR] PC, AR AR + 1
5 4
DT: PCAR,SC0
5 5
ISZ DT: DR M[AR]
6 4
DT: DRDR+1
6 5
DT: M[AR] DR, SC 0
6 6
D T DR': if (DR = 0) then (PC  PC + 1)
6 6
I/O Interface

• Hardware provides an interface to the I/O

device. Contains:
– data register (for data transfer, INPR and OUTR)
– status register (flags=peripheral ready, FGI & FGO)
– control register (R, IEN)
1. SW Polling (Programmed Control): CPU monitors the
status register - When data is ready, CPU reads or
writes from/to the data register
2. Interrupts: I/O interface can interrupt the CPU
when data can be read or written (will study later)
3. DMA (direct-memory access): the IF takes over
the control of the system’s Data, Address & Control
I/O Instructions
Interrupt Cycle

RTo

2
R'(T0+T1+T2)’

RT1 4

RT
3 2

1
 Interrupt Cycle

1. Save the return address

(PC=address of the
next instruction) at the
address 0;
2. BUN directly to the ISR
address 1120
corresponding to the
interrupt
3. Disable interrupts (IEN
0,R0)
4. Execute the Interrupt
Service Routine (ISR)
5. Resume the interrupted
program with BUN
indirectly to address 0 ISR ISR

72
Basic Computer Operation
RTL

Init
R’ R

Fetch INT

Exec FSM
 Fetch R'To: AR <- PC
Decode IR <- M[AR], PC <- PC + 1
RTL R'T1:
R'T2: D0, ... , D7 <- Decode IR(12-14),
AR <- IR(0-11), I <- IR(15)
Indirect D'7IT3: AR <- M[AR]
Interrupt: T T T (IEN)(FGI + FGO): R <- 1
0 1 2
RTo: AR <- 0, TR <- PC
RT1: M[AR] <- TR, PC <- 0
RT2: PC <- PC+1, IEN <- 0, R <- 0, SC <- 0
Memory-reference:
AND D0T4: DR <- M[AR]
D0T5: AC<-AC^DR,SC<-0
ADD D1T4: DR <- M[AR]
D1T5: AC <- AC + DR, E <- Cout, SC <- 0
LDA D2T4: DR <- M[AR]
D2T5: AC <- DR, SC <- 0
STA. D3T4: M[AR] <- AC, SC <- 0
BUN D4T4: PC <- AR, SC <- 0
BSA D5T4: M[AR] <- PC, AR <- AR + 1
D5T5: PC <- AR, SC <- 0
ISZ D6T4: DR <- M[AR]
D6T5: DR<-DR+1
D6T6: M[AR] <- DR,
if (DR = 0) then (PC <- PC + 1), SC <- 0
Reg-ref D7I'T3 = r (common to all reg.-ref. instr.)
IR(i) = Bi (i = 0, 1, 2, ... , 11)
r: SC <-0
CLA rB11: AC <-0
CLE rB10: E<-0
CMA rB9: AC <- AC'
CME rB8: E<-E'
CIR rB7: AC <- shr AC, AC(15) <- E, E <- AC(0)
CIL rB6: AC <- shlAC, AC(0) <- E, E <- AC(15)
INC rB5: AC<-AC+1
SPA rB4AC'(15): If (AC(15) = 0) then (PC <- PC + 1)
SNA rB3AC(15): If (AC(15) = 1) then (PC <- PC + 1)
SZA rB2AC': If (AC = 0) then (PC <- PC + 1)
SZE rB1E': If (E = 0) then (PC <- PC + 1)
HLT rB0: S<-0
In-out D7IT3 = p (common to all input-output instructions)
IR(i) = Bi (i = 6, 7, 8, 9, 10, 11)
p: SC<-0
INP pB11: AC(0-7) <- INPR, FGI <- 0
OUT pB10: OUTR <- AC(0-7), FGO <- 0
SKI pB9FGI: If (FGI = 1) then (PC <- PC + 1)
SKO pB8FGO: If (FGO = 1) then (PC <- PC + 1)
74
ION pB7: IEN <- 1
IOF pB6: IEN <- 0
 Assembly Language Program to
Subtract Two Numbers
• In order for a program to be executed by any computer it has to be converted into
that computer’s specific machine code by an appropriate compiler.
• An assembler is a compiler that translates each assembly instruction into its
equivalent binary instruction.
• The translation of the assembly program for subtracting two numbers (presented in
the previous example) into its equivalent machine code is shown in the following table.
Assembl Address Conten Run time
yLanguage (source code) (hex) t (hex) AC
ORG 100 /Origin of program is location 100 100 2107
LDA SUB /Load subtrahend to AC 0017
CMA /Complement AC 101 7200 FFE8
INC /Increment AC 102 7020 FFE9
ADD MIN /Add minuend to AC 103 1106 003C
STA DIF /Store difference 104 3108 003C
HLT /Halt computer 105 7001 003C
MIN, DEC 83 /Minuend 106 0053
SUB, DEC 23 /Subtrahend 107 0017
DIF, HEX 0 /Difference stored here 108 0000
END /End of symbolic program 75
Table 6.8 6.9
 LOOPS DO-WHILE
DO …. In Assembly Language, a
START
…. variable, called counter is
Increment ctr stored at label CTR and
ptr := ADS
ctr := -n =(-5) ENDO keeps track of the number
sum:= 0 of iterations were executed.
WHILE ctr < 0

MACHINE CODE If a sequence of

DO ASSEMBLY instructions is to be
executed n times,
LOP, sum := sum + M[PTR] addr memory
… the counter is
104 … initialized with –n
105 … LOP … and then
BUN ptr := ptr + 1
106 … … incremented by 1 at
ctr := ctr + 1

ISZ 107 610E ISZ CTR every pass through

WHILE 108 2105 BUN LOP the loop, until it
NO ctr = 0 109 7001 HLT reaches 0.

Yes
... … …
10E FFFB CTR equ -5
STOP
 Double-
• To increase the accuracy of an

Precision rather than only one.

operation, operands may be stored

Addition in two or more memory words

words31 is said to have1615double 210
• A number stored in two memory
LDA AL /Load A low Table 6.15 precision.AH AL

BH BL
ADD BL / Add B low, carry in E
CH CL
STA CL /Store in C low
CLA /Clear AC 1615 210

CIL /Circulate to bring carry from E to AC(0) E AC

ADD AH / Add A high and carry CIL 16 15 210

ADD BH /Add B high AL

STA CH /Store in C high carry  AC(0)
BL
HLT
AC
AL, - /Location of operands E CL
AH, -  An assembly program to 0 0000000000000E AC
BL, - add two double-precision AH
BH, - numbers is shown
CL, -  The little- endian BH
CH - approach is used CH AC
 P P + cil X if Xi = 1,
i=1,4
Multiplicati
cil X P
Y
0000 1011 0000 1111 0000 0000+
0000 1111 0000 1111

onA C
0000 1011 0000 1111+
E
0001 1110 0001 1110
0010 1101+ ORG 100
0000 1011 0011 1100 0000 0000 LOP, CLE /Clear E
0010 1101+ LDA Y /Load multiplier
0000 1011 0111 1000 0111 1000 CIR /transfer multiplier bit to E
1010 0101 STA Y /Store shifted multiplier
The basic computer designed in SZE /Check if bit is zero
Chapter 5 does not contain an BUN ONE /Bit is one; go to ONE
instruction to perform BUN ZRO /Bit is zero; go to ZRO
multiplication operation. ONE, LDA X /Load multiplicand
Thus, a SW implementation ADD P /Add to partial product
is necessary to provide the STA P /Store partial product
basic computer with the
capability to perform a CLE /Clear E
multiplication of two ZRO, LDA X /Load multiplicand
numbers. CIL /Shift left
To simplify the SW implementation STA X /Store shifted multiplicand
of the multiplication operation in ISZ CTR /Increment counter
the basic computer, it is assumed BUN LOP /Counter not zero; repeat loop
that the two operands are HLT /Counter is zero; halt
unsigned and that they have no CTR, DEC -8 /This location serves as counter
more than eight significant bits so X, HEX 000F /Multiplicand stored here
that the product cannot exceed the Y, HEX 000B /Multiplier stored here
16-bit word capacity P, HEX 0 /Product formed here
(Table 6.14). END
 MAIN CALLS SUBROUTINE
RAM
MAIN 1. m(808)  (PC) m(808) = 0805
…. 2. PC  addr op + 1 PC = 0809
0804 BSA 808
1
0805 …. RAM
RAM
803 MAIN 803 MAIN
BSA 808 804 BSA 808
804
805 805
2 AC 806
AC
806
807 807
808 08 05
DR DR
808 Ret addr
TR TR 809 S
PC = 0805 809 S 80A U
PC = 0809
80A U 80B B
80B B 80C BUNin808
80C BUNin808 1
 SUBROUTINE RETURNS TO MAIN
RAM
Subroutine 3. PC  [m(m(808))] PC=0805
080B …

080C BUNindirect808
RAM
080D …. 803 RAM

804 MAIN 803 MAIN

804 BSA 808
805 BSA 808
805
AC 1 806 A B 806
DR 807 X 807
TR 808 Y 808 08 05
PC = 080D 809 08 05 SP = 0A08 809 S
80A S PC = 0805 80A U
U
80B 80B B
80C
B 80C BUNin808
BUNin808
 SUBROUTINES
BSA: Branch and Save Return Address

20 BSA 135
21 next instruction
22 …… 3 1
…. …….
135 stored ret. addr (21) 2
136 Subroutine 1st instruc
137 …..
… …..
159 Subroutine last instr 3
160 BUNindirect 135
81
Parameter Linkage ORG 200 Table 6.17

200 /Load first operand into AC

Subroutine OR LDA X
performs logic OR 201 W, BSA OR /Branch to subroutine OR
between 2 operands 202 HEX 3AF6 /Second operand stored here
203 STA Y /Subroutine returns here
204 HLT
Y=WVX= W ∙X 205 X, HEX 7B95 /First operand stored here
206 Y, HEX 0 /Result stored here
Call-by-value 207 OR, HEX 0 /Subroutine OR
208 CMA /Complement first operand
1st operand (X) passed  209 STA TMP /Store in temporary location
registers (AC) 20A LDA OR I /Load second operand
2nd operand (W) passed  20B CMA /Complement second operand
memory = the location 20C AND TMP /AND complemented first operand
following the BSA 200 CMA /Complement again to get OR
instruction! 20E ISZ OR /Increment to get return address
20F BUN OR I /Return to main program
210 TMP, HEX 0 /Temporary storage
END
CALL-BY-REFERENCE

– Pointer to memory
 Pass the address of the parameters in memory
to the subroutine by
– a register or
– memory = global variable or parameter
linkage
 More complex, extra overhead for use of
the pointer
 Addr ORG 0 /Main program

program
nMai
0 BSA MVE /Branch to subroutine
1 HEX 100 / 1st parameter = address of first source data
Call-by- 2 HEX 200 / 2nd parameter = address of first destination data

parameters
3 DEC -16 / 3rd parameter (FF0) = Number of words to move
reference 4
5
HLT
HEX 0
/To store address provided by BSA MVE (1)
MVE,
Write and test a 6 LDA MVE I /Copy 1st parameter, i.e., address of source (100),
subroutine that copies 7 STA PT1 / into the first pointer (PT1:=100)
a block of 16 16-bit 8 ISZ MVE /Increment M[5] to point to 2 = addr. of 2nd param.
words {a0, a1, … a15} 9 LDA MVE I /Bring address of destination (200)
from memory A STA PT2 / and store it in the second pointer (PT2:=200)
B ISZ MVE /Increment M[5] to point to 3 = addr. of 3rd param.
locations starting at C
100 HEX to 200 HEX LDA MVE I /Bring the number of words to be copied (-16)
D STA CTR / and initialize the word counter with it (CTR:=-16)
E ISZ MVE /Increment M[5] to obtain correct return address
F LOP, LDA PT1 I /Load source item: AC ak @ M[PT1]
Subroutine

MVE(PT1,PT2,CTR)
POL 10 STA PT2 I /Store in destination: M[PT2] ak @ AC
11 ISZ PT1 /Increment source pointer
12 ISZ PT2 /Increment destination pointer
AC:=M[PT1] 13 ISZ CTR /Increment counter
M[PT2]:=AC 14 BUN LOP /Repeat 16 times
PT1:=PT1+1
15 BUN MVE I /Return to main program
16 PT1, / pointer to the source data
17 PT2, / pointer to the destination data
18 CTR,
PT2:=PT2+1
CTR:=CTR+1
ORG 100
100
Data

After running the program

CTR=0
a0
101
No … a1 PT1 = 110
…
Yes 10F a
15 PT2 = 210 Table 6.18
ORG 200 CTR=0
200 …
END
RTS
 000 ZRO, BUN SRV / Return address stored here
001 / Branch to service routine
ISR ••••• ••••• ••••••• •••••••
100 CLA /Portion of running program
101 ION / Turn on interrupt facility
102 LDA X / Interrupt occurs here
The service routine (ISR) 103 ADD Y
must contain instructions to 104 STA Z / Program returns here after intr
perform the following tasks: ••••• •••••
200 SRV,
•••••••
STA SAC
/ Interrupt service routine
/ Store content of AC
1

1. Save the contents of CIR / Move E into AC(15)

STA SE / Store content of E 2

processor registers (AC and E SKI / Check input flag

BUN NXT / If flag is OFF, check next flag
in this basic computer) INP / Flag ON, input char & reset FGI
2. Check which input-output flag OUT / Print character 3
STA PT1 I / Store it in input buffer
is set (FGI, FGO) NXT, ISZ PT1 / Increment input pointer
SKO / Check output flag 2
3. Service the device whose flag BUN EXT / Flag is OFF, exit
LDA PT2 I / Load char from output buffer
is set OUT / Output character 3
4. Restore the contents of EXT, ISZ PT2 / Increment output pointer
LDA SE / Restore value of AC(15) 4
processor registers CIL / Shift it to E
LDA SAC / Restore content of AC
5. Turn ON the interrupt facility ION / Turn interrupt on 5
6. Return to the running program SAC, BUN ZRO I / Return from ISR to run’g prog 6
/ AC is stored here
SE, / E is stored here
Table 6.23 PT1, / Pointer of85input buffer
PT2, / Pointer of output buffer