mm 40 60 80 100 120

6. Logical Effort
40
Jacob A. Abraham

Department of Electrical and Computer Engineering

60 The University of Texas at Austin
EE 382M, VLSI I
EE 360R, Computer-Aided IC Design
Fall 2009
80
September 15, 2009

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 1/1 v
 Introduction

mm 40 60 80 100 120
Chip designers have to face a bewildering array of choices
What is the best circuit topology for a function?
How many stages of logic give least delay?
40 wide should the transistors be?
How

Logical effort is one method to make these decisions

Uses a simple model of delay
60
Allows back-of-the-envelope calculations
Helps make rapid comparisons between alternatives
Emphasizes remarkable symmetries
80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 1/1 v
 Example
Design the decoder for a register file
mm specifications
Decoder 40 60 80 100 120
16 word register file
Each word is 32 bits wide
Each
40
bit presents load of 3 unit-sized transistors
True and complementary address inputs A[3:0]
Each input may drive 10 unit-sized transistors

Need to60decide
How many stages to use?
How large should each
gate be?
80
How fast can decoder
operate?
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 2/1 v
 Delay in a Logic Gate
Express delay in a process-independent unit
τ = 3RC
mm 40 60 80 100 120
d= dabs ≈ 12 ps in 180 nm process
τ
40 ps in 0.6 µm process
Delay has two components: d = f + p
40
Effort delay, f=gh (stage effort)
g: Logical Effort h: Electrical Effort=Cout /Cin
Measures relative ability of Ratio of output to input
gate to
60 deliver current capacitances, sometimes called
g ≡ 1 for inverter fanout effort

Parasitic delay, p
Represents
80 delay of gate driving no load
Set by internal parasitic capacitance

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 3/1 v
 Delay Plots

mm 40 60 80 100 120

d=f +p
40
= gh + p

60
What about
NOR2?

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 4/1 v
 Computing Logical Effort

Logical effort is the ratio of the input capacitance of a

mm 40 60 80 100 120
gate to the input capacitance of an inverter delivering
the same output current
Measure from delay vs. fanout plots
Or,
40 estimate by counting transistor widths

60

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 5/1 v
 Catalog of Gates

mm 40 60 80 100 120

Logical Effort of common gates

40 Number of inputs
Gate type
1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 60 5/3 7/3 9/3 (2n+1)/3
Tristate/Mux 2 2 2 2 2
XOR, XNOR 4,4 6,12,6 8,16,16,8

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 6/1 v
 Catalog of Gates

mm 40 60 80 100 120
Parasitic delay of common gates
In multiples of pinv (≈ 1)

40
Number of inputs
Gate type
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
60
NOR 2 3 4 n
Tristate/Mux 2 4 6 8 2n
XOR, XNOR 4 6 8
80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 7/1 v
 Example: Ring Oscillator

mm the frequency
Estimate 40 of an N-stage
60 ring 80
oscillator 100 120

40

Logical Effort: g = 1 31 stage ring

60
Electrical Effort: h = 1 oscillator in 0.6
Parasitic Delay: p = 1 µm process has
frequency of
Stage Delay: d = 2
∼ 200 MHz
Frequency:
80 fosc = 1/(2 · N · d) = 1/4N

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 8/1 v
 Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter
mm 40 60 80 100 120

40

60
The FO4 delay is about:
Logical Effort: g = 1
200 ps in a 0.6µm process
Electrical Effort: h = 4
60 ps in a 180 nm process
80
Parasitic Delay: p = 1
f/3 ns in a f µm process
Stage Delay: d = 5
(f/3 ps in a f nm process)
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 9/1 v
 Multistage Logic Networks

mm
Logical effort40generalizes 60
to multistage80networks 100 120
Q
Path Logical Effort, G = gi
C
Path Electrical Effort, H = Cout−path
Q in−path
40
Q
Path Effort, F = fi = gi hi

60

Can we write F = GH in general?

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 10 / 1 v
 Consider Paths that Branch

mm 40 60 80 100 120

G =1
H = 40
90 / 5 = 18
GH = 18
h1 = (15 +15)/5 = 6
h2 = 90/15 = 6
F = g1 g2 h1 h2 = 36 = 2GH
60

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 11 / 1 v
 Branching Effort and Multistage Delays

Branching
mm Effort40accounts for60branching between
80
stages
100
in path 120
Con path + Cof f path
b=
Con path
Y Y
B= bi (Note : hi = BH)
40
Now, path effort, F = GBH

Multistage Delays
60 X
Path Effort Delay, DF = fi
X
Path Parasitic Delay, P = pi
X
80 Path Delay, D = di = DF + P

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 12 / 1 v
 Designing Fast Circuits

mm 40 X60 80 100 120

D= di = DF + P
Delay is smallest when each stage bears same effort
1
40 fˆ = gi hi = F N
Thus, the minimum delay of an N-stage path is

1
60 D = NF N + P

This is a key result of logical effort

Find fastest possible delay
80 Doesn’t require calculating gate sizes

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 13 / 1 v
 Gate Sizes

mm 40 60 80 100 120
How wide should the gates be for the least delay?
Cout
fˆ = gh = g
40
Cin
gi Couti
=⇒ Cini =
fˆ

Working backward, apply capacitance transformation to find

60
input capacitance of each gate given load it drives
Check work by verifying input capacitance specification is met

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 14 / 1 v
 Example: 3-stage Path

mm
Select gate sizes x40and y for least
60 delay from
80 A to B 100 120

40

60

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 15 / 1 v
 Example: 3-stage Path, Cont’d

mm 40 60 80 100 120

40

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
60
Branching Effort B=3*2=6
Path Effort F=√ GBH = 125
Best Stage Effort ˆ
f = 3F =5
Parasitic Delay P=2+3+2=7
Delay80 D = 3*5 + 7 = 22 = 4.4 FO4

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 16 / 1 v
 Example: 3-stage Path, Cont’d

Workmm
backward for
40sizes 60 80 100 120
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10
40

60

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 17 / 1 v
 Best Number of Stages
How many stages should a path use?
Minimizing number
mm 40 of stages
60 is not always
80 fastest100 120
Example: drive 64-bit datapath with unit inverter

1
D =40 NF N + P
1
D = N(64) N + N
60

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 18 / 1 v
 Example of a Derivation Using the Logical Effort Equations

Consider adding inverters

to end of path
mm 40 60 80 100 120
How many give least
delay?
n1
1 X
D = NF N + pi + (N − n1 )pinv
40 i=1

∂D 1 1 1
= −F N lnF N + F N + pinv = 0
∂N
1
Define
60best stage effort, ρ = F
N

pinv + ρ(1 − lnρ) = 0

The above equation has no closed form solution
80
Neglecting parasitics (setting pinv = 0), we find ρ = 2.718 (e)
For pinv = 1, solve numerically for ρ = 3.59
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 19 / 1 v
 Sensitivity Analysis
How sensitive is delay to using exactly the best number of stages?
mm 40 60 80 100 120

40

60

2.4
80 < ρ < 6 gives delay within 15% of optimal
We can be sloppy
For example, use ρ = 4
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 20 / 1 v
 Decoder Example: Number of Stages
16 word, (32 bit) register file
Each
mmbit presents
40 load of 3 unit-sized
60 80 100 120
transistors
True and complementary address inputs
A[3:0]
40 input may drive 10 unit-sized
Each
transistors
Find: number of stages, sizes of gates, speed
Decoder effort is mainly electrical and branching
60
Electrical Effort: H = (32*3)/10 = 9.6
Branching Effort: B = 8
If we neglect logical effort (assume G = 1)
Path Effort: F = GBH = 76.8
80
Number of Stages: N = log4 F = 3.1
Try a 3-stage design
ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 21 / 1 v
 Decoder: Gate Sizes and Delay

Logical Effort: G = 1 * 6/3 * 1 = 2

mm
Path Effort: 40
F = GBH =60
154 80 100 120
1
Stage Effort: fˆ = F = 5.363

Path Delay: D = 3fˆ + 1 + 4 + 1 = 22.1

Gate sizes: z = 96*1/5.36 = 18
40
Gate sizes: y = 18*2/5.36 = 6.7

60

80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 22 / 1 v
 Decoder: Comparison

mm 40 60 80 100 120
Compare many alternatives with a spreadsheet
Design N G P D
NAND4-INV 2 2 5 29.8
40
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
60
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6

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ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 23 / 1 v
 Review of Definitions

mm
Term 40 Stage 60 80 Path 100 120

Number of stages 1 N
Q
Logical effort g G= gi
40 Cout Cout−path
Electrical effort h= Cin H= Cin−path
Con−path +Cof f −path Q
Branching effort b= Con−path B= bi
Effort f = gh F = GBH
60 P
Effort delay f DF = fi
P
Parasitic delay p P = pi
P
Delay
80 d=f+p D = di = DF + P

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 24 / 1 v
 Method of Logical Effort
1. Compute path effort F = GBH
2. Estimate best number of stages N = log4 F
3. mm
Sketch 40 N stages60
path with 80 100 120
1
4. Estimate least delay D = NF + PN
1
5. Determine best stage effort fˆ = F N
6. Find gate sizes Cin = gi Cfout
40
Limits of logical effort
Chicken and egg problem
Need path to compute G
60 But, don’t know number of stages without G
Simplistic delay model, neglects input rise time effects
Interconnect
Iteration required in designs with significant wires
80
Maximum speed only
Not minimum area/power for constrained delay

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 25 / 1 v
 Summary of Logical Effort

mm 40 60 80 100 120
Logical effort is useful for thinking of delay in circuits
Numeric logical effort characterizes gates
NANDs are faster than NORs in CMOS
40
Paths are fastest when effort delays are ∼4
Path delay is weakly sensitive to stages, sizes
But using fewer stages doesn’t mean faster paths
Delay of path is about log4F FO4 inverter delays
60
Inverters and NAND2 best for driving large caps
Provides language for discussing fast circuits, but requires
practice to master
80

ECE Department, University of Texas at Austin Lecture 6. Logical Effort Jacob A. Abraham, September 15, 2009 26 / 1 v