Altera Digital Logic Lab Exercises

Introduction

This folder contains a set of laboratory exercises for use on the Altera DE1-SoC Development and Education
board. These exercises are intended for use in a first course on Digital Logic Design, which is included as part of
the curriculum in most Computer Engineering, Electrical Engineering, and Computer Science programs.
Circuits are designed for implementation on the DE1-SoC board by using Altera’s state-of-the-art Quartus II
CAD system. To teach students how to use this software, which is provided at no charge for educational use, we
have developed a set of step-by-step tutorials that are available on Altera’s University Program web site. There is
a tutorial that introduces the use of the DE1-SoC board, and a set of tutorials that show how to develop circuits
with the Quartus II software by using Verilog HDL or VHDL as the design entry method. Students should work
through these tutorials as a preparation for the lab exercises.
There is also a basic tutorial on using schematic capture in the Quartus II software. Although we do not provide
a version of the lab exercises that use schematic capture, a course Instructor could easily adapt the material for this
purpose if desired.

Overview of Lab Exercises

The laboratory exercises begin with fundamental concepts and perform simple operations on the DE1-SoC board,
like using switches and controlling LEDs and 7-segment displays. These exercises assume that students are just
beginning to learn about digital logic concepts. Subsequent exercises progress to more advanced topics such as
arithmetic circuits, flip-flops, counters, state machines, memories, data paths, and simple processors. Instructors
of courses may choose to adopt the entire sequence of exercises, only selected exercises, or just parts of some
exercises. We have tried to make the material as modular as possible so that instructors can combine these exercises
with their own teaching material.
Each exercise consists of multiple parts. In most cases the solution required for the early parts can be reused
in a modular fashion for later parts. Also, the solutions produced for early exercises are often reusable for parts of
more advanced exercises. Our basic approach is to encourage students to develop their circuits in small increments
and to build larger circuits in a modular, hierarchical fashion. As an aid for the Instructor, we provide complete
solutions in Verilog and VHDL code for all lab exercises.

Obtaining the Source Code Files

To make it easier for Instructors to modify the lab exercises as needed, we provide the original source files that
were used to create the lab exercise write-ups. The lab exercises are written in ASCII text files that include
formatting information for the LaTeX word processing system. Instructors who are not familiar with LaTeX may
choose to import the text into some other word processing system of their choice. The figures used in the exercises
were created using Adobe FrameMaker. They are provided to course Instructors in both the FrameMaker format
as well as in Adobe PDF format.
We also provide the Verilog and VHDL source files for all of the suggested solutions, and the Quartus II project
files that are needed to compile the code for implementation on the DE1-SoC board.
To obtain the source files for both the lab exercises and solutions, visit Altera’s University Program web site
at www.altera.com. You will find instructions for obtaining this information, which is protected from access by
students. Please do not freely distribute the suggested solutions on the Internet, and protect this material as you
would other similar educational materials that are assigned by Instructors to students as a part of their course
grade.

Copyright 2014
c Altera Corporation.