5 4 3 2 1

UltraBook 15" Schematics Document

Vinafix.com
D
Ivy Bridge D

Panther Point

2012-08-14
C
REV : A00 C

DY : None Installed
UMA: UMA only installed
SG: Optimus solution installed.

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 1 of 106
5 4 3 2 1
 5 4 3 2 1

CHARGER
BQ24727 40
INPUTS OUTPUTS
Project code : 91.4VQ01.001
Block Diagram PCB P/N : 1319F
AD+

SYSTEM DC/DC
BT+

TPS51125RGER 41
(Discrete / UMA) Revision : 11307-1 INPUTS OUTPUTS
3D3V_AUX_S5
5V_S5

Vinafix.com DCBATOUT 3D3V_S5

15V_S5

D
CPU DC/DC D

Intel CPU VT1318+VT1326 42,43

Discrete GPU Ivy Bridge DDRIII 1600MHz Channel A
INPUTS OUTPUTS
DDRIII Slot A 5V_S5 VCC_CORE
17W 1600MHz 14
GFX DC/DC
Nvidia PCIe x 8 DDRIII 1600MHz Channel B
VT1318+VT1323 44
VRAM(DDR3) DDR3 DDRIII Slot B
N13P-GV2 INPUTS OUTPUTS
256Mbx16x4(2GB) 1600MHz 15
5V_S5 VCC_GFXCORE
88,89,90,91
83.84,85,86,87 BGA1023 SYSTEM DC/DC
4,5,6,7,8,9,10 VT385
INPUTS OUTPUTS
5V_S5 1D05V_PCH
VCCP_CPU 45
FDIx4x2 DMIx4
SYSTEM DC/DC
TPS51216 46
INPUTS OUTPUTS
Intel Mini-Card 1D5V_S3
TMDS PCIE x 1 USB2.0 x 1 DCBATOUT 0D75V_S0
HDMI 51 802.11a/b/g/n DDR_VREF_S3
PCH BT V4.0 combo 65
26
Panther Point SYSTEM DC/DC
Mini-Card RT8068A 47
LCD LVDS USB2.0 x 1 WWAN UIM SIM 66 INPUTS OUTPUTS
C 49 66 C
BGA989 3D3V_S5 1D8V_S0
Mini-Card
SATA GENII x 1 mSATA
SYSTEM DC/DC
66 APL5916 48
Camera 49 USB2.0 x 1
HM77
INPUTS OUTPUTS
5V_S5 0D85_S0
Internal Digital MIC Codec
14 USB 2.0/1.1 ports HDA IDT Combo Jack VGA DC/DC
4 USB 3.0 ports 92HD94 29 ADP3211 92
10/100/1000 Lan High Definition Audio INPUTS OUTPUTS
PCIE x 1 DCBATOUT VGA_CORE
RJ45 ATHEROS 6 SATA ports
59 AR8161 31
8 PCIE ports Switches
LPC I/F INPUTS OUTPUTS
2CH Speaker 1D5V_S3 1D5V_S0
ACPI 4.0a 5V_S5 5V_S0
( 2W, 4ohm /channel ) 3D3V_S5 3D3V_S0
3D3V_S5 3D3V_WLAN_AOAC
Left side USB3.0 x 1 3D3V_S5 3D3V_VGA_S0
1D8V_S0 1D8V_VGA_S0
1D5V_S3 1D5V_VGA_S0
Daughter Board VCCP_CPU 1D05V_VGA_S0
USB3.0 / PowerShare USB3.0 x 1 USB3.0 Redriver
USB Port:1 TI
USB PowerShare
62
USB2.0 USB2.0 x 1 SN65LVPE502RGER USB 3.0 UMA/Discrete
TI
TPS2541 62 USB2.0 x 1 PCB LAYER
USB Port:4
B
L1:Top L5:VCC B
L2:GND L6:Signal
L3:Signal L7:GND
Left side USB3.0 Redriver L4:Signal L8:Bottom
USB3.0 x 1 USB3.0 x 1
TI USB3.0
USB3.0 SN65LVPE502RGER USB Port:3

USB Port:2 USB2.0 x 1 USB2.0 x 1

Debug Port 63

LPC BUS
CardReader Connector
LPC debug port
71
USB2.0 x 1 Realtek SD/SDHC/SDXC/SD UHS-I
17,18,19,20,21,22,23,24,25
RTS5179 MMC/MMC+, MS/MS Pro

Thermal
NUVOTON SMBUS
SATA GenIII x 1 HDD
NCT7718W 28 56
KBC
Fan Control NUVOTON SPI
GMT NPCE885P SATA GenI x 1
G991P11U 28 27 ODD 56

PS2 Flash ROM

A 8MB 60 A

Int. Touch I 2C
KB69 PAD69
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Block Diagram
Size Document Number Rev
A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 2 of 106
5 4 3 2 1
 A B C D E
PCH Strapping Chief River Schematic Checklist Rev.0_72 Sandy & Ivy Bridge Compatibility Chief River Schematic Checklist Rev.0_xx

Name Schematics Notes Pin Name Configuration Schematic Notes

SPKR The signal has a weak internal pull-down. Sandy Bridge + Ivy Bridge DDR3 VREF, M1 and M3 function are required.

Vinafix.com
If the signal is sampled high, this indicates that the system is strapped to the
"No Reboot" mode (Panther Point will disable the TCO Timer system reboot feature). DDR3 VREF
Ivy Bridge No change.
4 INIT3_3V# Weak internal pull-up. Leave as "No Connect". 4
INTVRMEN Integrated 1 V VRMs is enabled when high, External when low.
Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. Sandy Bridge + Ivy Bridge through a 1K±5% series resistor. PROC_SELECT# also needs a 2.2K±5%
GNT2#/GPIO53 Mobile: Used as GPIO only PROC_SELECT# pull up resistor to PCH VccDFTERM rail.
GNT1#/GPIO51 Pull-up resistors are not required on these signals. &
If pull-ups are used, they should be tied to the Vcc3_3power rail. DF_TVS
Ivy Bridge No change.
DF_TVS DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor.
HAD_DOCK_EN# This signal controls the external Intel HD Audio docking isolation logic. This is
/GPIO[33] an active-low-signal. When deasserted the external docking switch is in isolate mode. The POR for Ivy Bridge mobile parts is now 1.05 V. There is no
When asserted the external docking switch electrically connects the Intel HD Audio Sandy Bridge + Ivy Bridge longer a need for a separate VR for the processor at 1.0 V and
dock signals to the corresponding Panther Point signals. This signal can instead VCCIO_SEL the PCH at 1.05 V. A single VR may be shared for both.
be used as GPIO33.
Ivy Bridge No change.
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
GPIO15 Low (0) Sandy Bridge + Ivy Bridge VCCSA[0:1] are the select pin of VCCSA's power control.
Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality
High (1) VCCSA_VID[0:1]
Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality Ivy Bridge No change.
3 3
Power Plane Processor Strapping Chief River Schematic Checklist Rev.0_72
Configuration (Default value for each bit is Default POP
Power Plane Voltage Actice Status Description Pin Name Strap Description 1 unless specified otherwise) Value Value
5V_S0 5V
3D3V_S0 3.3V CFG[2] PCI-Express Static 1: Normal Operation.
1D8V_S0 1.8V Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1 0
1D5V_S0 1.5V
1D05V_VTT 1.05V Disabled - No Physical Display Port attached to
1V_S0 1V CFG[4] 1: Embedded DisplayPort.
0D85V_S0 0.85V S0 CPU Core Rail 1 1
Graphics Core Rail Enabled - An external Display Port device is
0D75V_S0 0.75V 0: connectd to the EMBEDDED display Port
VCC_CORE 0.3V to 1.3V
VCC_GFXCORE 0 to 1.25V
CFG[6:5] PCI-Express 11: 1x16 PCI Express
1D8V_VGA_S0 1.8V
3D3V_VGA_S0 3.3V Port Bifurcation
10: 2 x8 - PCI Express
1V_VGA_S0 1V Straps 11 10
01: Reserved
00: 1x8, 2x4 PCI Express
2 2
5V_USBX_S3 5V S3
1D5V_S3 1.5V
DDR_VREF_S3 0.75V
USB Table PCIE Table SATA Table
BT+ 6V-14.1V Pair Device PCIE SATA
DCBATOUT 6V-14.1V 0 USB3.0 port1, With Power Share Lane Device Pair Device
5V_S5 5V
5V_AUX_S5 5V All S states AC Brick Mode only 1 USB3.0 port2 , Debug Port
3D3V_S5 3.3V 1 NC 0 HDD1
2 USB3.0 port3
3D3V_AUX_S5 3.3V 2 NC 1 mSATA
3 USB3.0 port4
3 NC 2 NC
4 Touch Panel
3D3V_LAN_S5 3.3V WOL_EN Legacy WOL 4 WLAN 3 NC
5 NC
5 NC 4 ODD
6 NC
3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting 6 Onboard LAN 5 NC
Deep Sleep states 7 NC
7 NC
8 WWAN
8 WWAN
3D3V_AUX_S5 3.3V G3, Sx Powered by Li Coin Cell 9 NC
1 in G3 and +V3ALW in Sx 10 Card reader
<Core Design>
1
11 WLAN
Wistron Corporation
12 CAMERA 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
13 NC
Title
Table of Content
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 3 of 106
 5 4 3 2 1
SSID = CPU

Layout Note:
Signal Routing Guideline:
Vinafix.com PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
D D
VCCP_CPU
CPU1A 1 OF 9
G3 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
19 DMI_TXN[3:0] PEG_ICOMPO G1
DMI_TXN0 M2 G4
DMI_TXN1 DMI_RX#0 PEG_RCOMPO
P6 DMI_RX#1
DMI_TXN2 P1
DMI_TXN3 DMI_RX#2
P10 DMI_RX#3 PEG_RX#0 H22
J21
Layout Note: 19 DMI_TXP[3:0]
DMI_TXP0 N3
PEG_RX#1
B22
DMI_TXP1 DMI_RX0 PEG_RX#2
DMI trace length 2000~8000mil P7 DMI_RX1 PEG_RX#3 D21

DMI
DMI_TXP2 P3 A19
DMI_TXP3 DMI_RX2 PEG_RX#4
P11 DMI_RX3 PEG_RX#5 D17
19 DMI_RXN[3:0] PEG_RX#6 B14
DMI_RXN0 K1 D13
DMI_TX#0 PEG_RX#7 PEG_RXN[7..0] 83
DMI_RXN1 M8 A11 PEG_RXN7
DMI_RXN2 DMI_TX#1 PEG_RX#8 PEG_RXN6
N4 DMI_TX#2 PEG_RX#9 B10
DMI_RXN3 R2 G8 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN4
19 DMI_RXP[3:0] PEG_RX#11 A8
DMI_RXP0 K3 B6 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
M7 DMI_TX1 PEG_RX#13 H8
DMI_RXP2 P4 E5 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
T3 DMI_TX3 PEG_RX#15 K7

PEG_RX0 K22
PEG_RX1 K19
19 FDI_TXN[7:0] PEG_RX2 C21
C FDI_TXN0
FDI_TXN1
U7
W11
FDI0_TX#0 PEG_RX3 D19
C19
C
FDI_TXN2 FDI0_TX#1 PEG_RX4
W1 FDI0_TX#2 PEG_RX5 D16
FDI_TXN3 AA6 C13
FDI_TXN4 FDI0_TX#3 PEG_RX6
W6 D12
Layout Note: FDI_TXN5 V4
FDI1_TX#0 PEG_RX7
C11 PEG_RXP7
PEG_RXP[7..0] 83
FDI_TXN6 FDI1_TX#1 PEG_RX8 PEG_RXP6
FDI trace length 2000~6500mil

PCI EXPRESS -- GRAPHICS

Y2 FDI1_TX#2 PEG_RX9 C9
FDI_TXN7 AC9 F8 PEG_RXP5
FDI1_TX#3 PEG_RX10

Intel(R) FDI
C8 PEG_RXP4
PEG_RX11 PEG_RXP3
19 FDI_TXP[7:0] PEG_RX12 C5
FDI_TXP0 U6 H6 PEG_RXP2
FDI_TXP1 FDI0_TX0 PEG_RX13 PEG_RXP1
W10 FDI0_TX1 PEG_RX14 F6
FDI_TXP2 W3 K6 PEG_RXP0
FDI_TXP3 FDI0_TX2 PEG_RX15
AA7 FDI0_TX3
FDI_TXP4 W7 G22
FDI_TXP5 FDI1_TX0 PEG_TX#0
T4 FDI1_TX1 PEG_TX#1 C23
FDI_TXP6 AA3 D23
FDI_TXP7 FDI1_TX2 PEG_TX#2
AC8 FDI1_TX3 PEG_TX#3 F21
PEG_TX#4 H19
FDI_FSYNC0 AA11 C17
19 FDI_FSYNC0 FDI0_FSYNC PEG_TX#5
FDI_FSYNC1 AC12 K15
19 FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
PEG_TX#7 F17 PEG_TXN[7..0] 83
FDI_INT U11 F14 PEG_C_TXN7 1 2 C401 SCD22U10V2KX-1GP PEG_TXN7
19 FDI_INT FDI_INT PEG_TX#8
A15 PEG_C_TXN6 SG
1 2 C402 SCD22U10V2KX-1GP PEG_TXN6
FDI_LSYNC0 AA10 PEG_TX#9
J14 PEG_C_TXN5 SG
1 2 C403 SCD22U10V2KX-1GP PEG_TXN5
19 FDI_LSYNC0
FDI_LSYNC1 AG8 FDI0_LSYNC PEG_TX#10
H13 PEG_C_TXN4 SG
1 2 C404 SCD22U10V2KX-1GP PEG_TXN4
19 FDI_LSYNC1 FDI1_LSYNC PEG_TX#11
M10 PEG_C_TXN3 SG
1 2 C405 SCD22U10V2KX-1GP PEG_TXN3
PEG_TX#12
F10 PEG_C_TXN2 SG
1 2 C406 SCD22U10V2KX-1GP PEG_TXN2
PEG_TX#13
D9 PEG_C_TXN1 SG
1 2 C407 SCD22U10V2KX-1GP PEG_TXN1
PEG_TX#14
J4 PEG_C_TXN0 SG
1 2 C408 SCD22U10V2KX-1GP PEG_TXN0
B VCCP_CPU R402 1 2 24D9R2F-L-GP DP_COMP AF3 EDP_COMPIO
PEG_TX#15 SG B
AD2 EDP_ICOMPO PEG_TX0 F22
AG11 EDP_HPD# PEG_TX1 A23
PEG_TX2 D24
PEG_TX3 E21
AG4 G19
Layout Note: AF4
EDP_AUX# PEG_TX4
B18
EDP_AUX PEG_TX5
Signal Routing Guideline: PEG_TX6 K17
eDP

EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_TX7 G17 PEG_TXP[7..0] 83
AC3 E14 PEG_C_TXP7 1 2 C417 SCD22U10V2KX-1GP PEG_TXP7
EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils. AC4
EDP_TX#0 PEG_TX8
C15 PEG_C_TXP6 SG
1 2 C418 SCD22U10V2KX-1GP PEG_TXP6
AE11
EDP_TX#1 PEG_TX9
K13 PEG_C_TXP5 SG
1 2 C419 SCD22U10V2KX-1GP PEG_TXP5
AE7
EDP_TX#2 PEG_TX10
G13 PEG_C_TXP4 SG
1 2 C420 SCD22U10V2KX-1GP PEG_TXP4
EDP_TX#3 PEG_TX11
K10 PEG_C_TXP3 SG
1 2 C421 SCD22U10V2KX-1GP PEG_TXP3
AC1
PEG_TX12
G10 PEG_C_TXP2 SG
1 2 C422 SCD22U10V2KX-1GP PEG_TXP2
AA4
EDP_TX0 PEG_TX13
D8 PEG_C_TXP1 SG
1 2 C423 SCD22U10V2KX-1GP PEG_TXP1
AE10
EDP_TX1 PEG_TX14
K4 PEG_C_TXP0 SG
1 2 C424 SCD22U10V2KX-1GP PEG_TXP0
AE6
EDP_TX2 PEG_TX15 SG
EDP_TX3

IVY-BRIDGE-GP-NF
71.00IVY.A0U
Layout Note:
PEG trace length 1500~9000mil

A <Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU(PCIE/DMI/FDI)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 4 of 106
 5 4 3 2 1
SSID = CPU

Vinafix.com
D CPU1B 2 OF 9
D
J3 CLK_EXP_P CLK_EXP_P 20
BCLK CLK_EXP_N
BCLK# H2 CLK_EXP_N 20

MISC

CLOCKS
22 H_SNB_IVB# H_SNB_IVB# F49 RN503
PROC_SELECT# CLK_DP_P_R 1
DPLL_REF_CLK AG3 4
AG1 CLK_DP_N_R 2 3
TP501 1 SKTOCC#_R C57
DPLL_REF_CLK# VCCP_CPU Layout Note:
TPAD14-OP-GP PROC_DETECT# SRN1KJ-7-GP Checking the connector pin's LAYOUT

VCCP_CPU
TP502 1 H_CATERR# C49 R507
R501 TPAD14-OP-GP CATERR# 4K99R2F-L-GP

THERMAL
1 2 H_PROCHOT# 1 2

62R2J-GP H_PECI A48 AT30 SM_DRAMRST# SM_DRAMRST# 37

22,27 H_PECI PECI SM_DRAMRST#
R505
0R2J-2-GP R513 BF44 SM_RCOMP_0 R506 1 2 140R2F-GP
SM_RCOMP0

DDR3
MISC
1 2 1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP_1 R508 1 2 25D5R2F-GP
86 H_PROCHOT#_L DY 27,40 H_PROCHOT# PROCHOT# SM_RCOMP1
BG43 SM_RCOMP_2 R511 1 2 200R2F-L-GP
56R2J-4-GP SM_RCOMP2

H_THERMTRIP# D45
22 H_THERMTRIP# THERMTRIP# Layout Note:
Layout Note: Signal Routing Guideline:
N53 XDP_PRDY# XDP_PRDY# 71 SM_RCOMP keep routing length less than 500 mils.
PRDY#
C R501, R513 place near to CPU PREQ# N55 XDP_PREQ# XDP_PREQ# 71 Trace width = 15mil C
L56 XDP_TCLK
TCK XDP_TMS VCCP_CPU
TMS L55

PWR MANAGEMENT
J58 XDP_TRST#
TRST#

JTAG & BPM

19 H_PM_SYNC H_PM_SYNC C48 M60 XDP_TDI
PM_SYNC TDI XDP_TDO RN501
TDO L59
X02_0611 XDP_TDI 1 8
XDP_TMS 2 7
1 R504 2 H_CPUPW RGD_R B46 XDP_TDO 3 6
22 H_CPUPW RGD
0R0402-PAD-2-GP UNCOREPWRGOOD
K58 XDP_DBRESET# XDP_DBRESET# 19 4 XDP 5
DBR#
1 R503 2
10KR2J-3-GP SRN51J-1-GP
37 VDDPW RGOOD VDDPW RGOOD BE45 G58 XDP_BPM0 XDP_BPM0 71
SM_DRAMPWROK BPM#0 XDP_BPM1 RN502
BPM#1 E55 XDP_BPM1 71
E59 XDP_BPM2 XDP_BPM2 71 XDP_TRST# 1 4
BPM#2 XDP_BPM3 XDP_TCLK
G55 2 3
BPM#3
G59 XDP_BPM4
XDP_BPM3
XDP_BPM4
71
71
XDP
BUF_CPU_RST# BPM#4 XDP_BPM5 SRN51J-GP
18,27,31,65,66,71,83 PLT_RST# 1 2 D44 RESET# BPM#5 H60 XDP_BPM5 71
J59 XDP_BPM6 XDP_BPM6 71
BPM#6
1

R510 J61 XDP_BPM7 XDP_BPM7 71

BPM#7
1

1K5R2F-2-GP
R509 C501
698R2F-GP DY SC220P50V2KX-3GP
2
2

IVY-BRIDGE-GP-NF
71.00IVY.A0U
B Layout Note:
B
C501 place near to CPU

A <Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU(THERMAL/CLOCK/PM)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 5 of 106
 5 4 3 2 1

SSID = CPU

CPU1D 4 OF 9
CPU1C
Vinafix.com 3 OF 9
15 M_B_DQ[63:0]
M_B_DQ[63:0]
M_A_DQ[63:0] M_B_DQ0 AL4
14 M_A_DQ[63:0] SB_DQ0
D M_A_DQ0 AG6 M_B_DQ1 AL1 BA34 D
M_A_DQ1 SA_DQ0 M_B_DQ2 SB_DQ1 SB_CK0 M_B_DIMB_CLK_DDR0 15
AJ6 SA_DQ1 SA_CK0 AU36 M_A_DIMA_CLK_DDR0 14 AN3 SB_DQ2 SB_CK#0 AY34 M_B_DIMB_CLK_DDR#0 15
M_A_DQ2 AP11 AV36 M_B_DQ3 AR4 AR22
M_A_DQ3 SA_DQ2 SA_CK#0 M_A_DIMA_CLK_DDR#0 14 M_B_DQ4 SB_DQ3 SB_CKE0 M_B_DIMB_CKE0 15
AL6 SA_DQ3 SA_CKE0 AY26 M_A_DIMA_CKE0 14 AK4 SB_DQ4
M_A_DQ4 AJ10 M_B_DQ5 AK3
M_A_DQ5 SA_DQ4 M_B_DQ6 SB_DQ5
AJ8 SA_DQ5 AN4 SB_DQ6
M_A_DQ6 AL8 M_B_DQ7 AR1
M_A_DQ7 SA_DQ6 M_B_DQ8 SB_DQ7
AL7 SA_DQ7 AU4 SB_DQ8
M_A_DQ8 AR11 M_B_DQ9 AT2 BA36
M_A_DQ9 SA_DQ8 M_B_DQ10 SB_DQ9 SB_CK1 M_B_DIMB_CLK_DDR1 15
AP6 SA_DQ9 SA_CK1 AT40 M_A_DIMA_CLK_DDR1 14 AV4 SB_DQ10 SB_CK#1 BB36 M_B_DIMB_CLK_DDR#1 15
M_A_DQ10 AU6 AU40 M_B_DQ11 BA4 BF27
M_A_DQ11 SA_DQ10 SA_CK#1 M_A_DIMA_CLK_DDR#1 14 M_B_DQ12 SB_DQ11 SB_CKE1 M_B_DIMB_CKE1 15
AV9 SA_DQ11 SA_CKE1 BB26 M_A_DIMA_CKE1 14 AU3 SB_DQ12
M_A_DQ12 AR6 M_B_DQ13 AR3
M_A_DQ13 SA_DQ12 M_B_DQ14 SB_DQ13
AP8 SA_DQ13 AY2 SB_DQ14
M_A_DQ14 AT13 M_B_DQ15 BA3
M_A_DQ15 SA_DQ14 M_B_DQ16 SB_DQ15
AU13 SA_DQ15 BE9 SB_DQ16
M_A_DQ16 BC7 M_B_DQ17 BD9 BE41
M_A_DQ17 SA_DQ16 M_B_DQ18 SB_DQ17 SB_CS#0 M_B_DIMB_CS#0 15
BB7 SA_DQ17 SA_CS#0 BB40 M_A_DIMA_CS#0 14 BD13 SB_DQ18 SB_CS#1 BE47 M_B_DIMB_CS#1 15
M_A_DQ18 BA13 BC41 M_B_DQ19 BF12
M_A_DQ19 SA_DQ18 SA_CS#1 M_A_DIMA_CS#1 14 M_B_DQ20 SB_DQ19
BB11 SA_DQ19 BF8 SB_DQ20
M_A_DQ20 BA7 M_B_DQ21 BD10
M_A_DQ21 SA_DQ20 M_B_DQ22 SB_DQ21
BA9 SA_DQ21 BD14 SB_DQ22
M_A_DQ22 BB9 M_B_DQ23 BE13
M_A_DQ23 SA_DQ22 M_B_DQ24 SB_DQ23
AY13 SA_DQ23 BF16 SB_DQ24 SB_ODT0 AT43 M_B_DIMB_ODT0 15
M_A_DQ24 AV14 AY40 M_B_DQ25 BE17 BG47
M_A_DQ25 SA_DQ24 SA_ODT0 M_A_DIMA_ODT0 14 M_B_DQ26 SB_DQ25 SB_ODT1 M_B_DIMB_ODT1 15
AR14 SA_DQ25 SA_ODT1 BA41 M_A_DIMA_ODT1 14 BE18 SB_DQ26
M_A_DQ26 AY17 M_B_DQ27 BE21
M_A_DQ27 SA_DQ26 M_B_DQ28 SB_DQ27
AR19 SA_DQ27 BE14 SB_DQ28
M_A_DQ28 BA14 M_B_DQ29 BG14
C M_A_DQ29 SA_DQ28 M_B_DQ30 SB_DQ29 C
AU14 SA_DQ29 BG18 SB_DQ30 M_B_DQS#[7:0] 15
M_A_DQ30 BB14 M_A_DQS#[7:0] 14 M_B_DQ31 BF19 AL3 M_B_DQS#0
M_A_DQ31 SA_DQ30 M_A_DQS#0 M_B_DQ32 SB_DQ31 SB_DQS#0 M_B_DQS#1
BB17 SA_DQ31 SA_DQS#0 AL11 BD50 SB_DQ32 SB_DQS#1 AV3
M_A_DQ32 BA45 AR8 M_A_DQS#1 M_B_DQ33 BF48 BG11 M_B_DQS#2
M_A_DQ33 SA_DQ32 SA_DQS#1 M_A_DQS#2 M_B_DQ34 SB_DQ33 SB_DQS#2 M_B_DQS#3
AR43 SA_DQ33 SA_DQS#2 AV11 BD53 SB_DQ34 SB_DQS#3 BD17
M_A_DQ34 AW48 AT17 M_A_DQS#3 M_B_DQ35 BF52 BG51 M_B_DQS#4
M_A_DQ35 SA_DQ34 SA_DQS#3 M_A_DQS#4 M_B_DQ36 SB_DQ35 SB_DQS#4 M_B_DQS#5
BC48 SA_DQ35 SA_DQS#4 AV45 BD49 SB_DQ36 SB_DQS#5 BA59
M_A_DQ36 BC45 AY51 M_A_DQS#5 M_B_DQ37 BE49 AT60 M_B_DQS#6
SA_DQ36 SA_DQS#5 SB_DQ37 SB_DQS#6

DDR SYSTEM MEMORY B

M_A_DQ37 AR45 AT55 M_A_DQS#6 M_B_DQ38 BD54 AK59 M_B_DQS#7
SA_DQ37 SA_DQS#6 SB_DQ38 SB_DQS#7
DDR SYSTEM MEMORY A

M_A_DQ38 AT48 AK55 M_A_DQS#7 M_B_DQ39 BE53

M_A_DQ39 SA_DQ38 SA_DQS#7 M_B_DQ40 SB_DQ39
AY48 SA_DQ39 BF56 SB_DQ40
M_A_DQ40 BA49 M_B_DQ41 BE57
M_A_DQ41 SA_DQ40 M_B_DQ42 SB_DQ41
AV49 SA_DQ41 BC59 SB_DQ42
M_A_DQ42 BB51 M_B_DQ43 AY60
M_A_DQ43 SA_DQ42 M_B_DQ44 SB_DQ43
AY53 SA_DQ43 BE54 SB_DQ44
M_A_DQ44 BB49 M_A_DQS[7:0] 14 M_B_DQ45 BG54 M_B_DQS[7:0] 15
M_A_DQ45 SA_DQ44 M_A_DQS0 M_B_DQ46 SB_DQ45 M_B_DQS0
AU49 SA_DQ45 SA_DQS0 AJ11 BA58 SB_DQ46 SB_DQS0 AM2
M_A_DQ46 BA53 AR10 M_A_DQS1 M_B_DQ47 AW59 AV1 M_B_DQS1
M_A_DQ47 SA_DQ46 SA_DQS1 M_A_DQS2 M_B_DQ48 SB_DQ47 SB_DQS1 M_B_DQS2
BB55 SA_DQ47 SA_DQS2 AY11 AW58 SB_DQ48 SB_DQS2 BE11
M_A_DQ48 BA55 AU17 M_A_DQS3 M_B_DQ49 AU58 BD18 M_B_DQS3
M_A_DQ49 SA_DQ48 SA_DQS3 M_A_DQS4 M_B_DQ50 SB_DQ49 SB_DQS3 M_B_DQS4
AV56 SA_DQ49 SA_DQS4 AW45 AN61 SB_DQ50 SB_DQS4 BE51
M_A_DQ50 AP50 AV51 M_A_DQS5 M_B_DQ51 AN59 BA61 M_B_DQS5
M_A_DQ51 SA_DQ50 SA_DQS5 M_A_DQS6 M_B_DQ52 SB_DQ51 SB_DQS5 M_B_DQS6
AP53 SA_DQ51 SA_DQS6 AT56 AU59 SB_DQ52 SB_DQS6 AR59
M_A_DQ52 AV54 AK54 M_A_DQS7 M_B_DQ53 AU61 AK61 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS7 M_B_DQ54 SB_DQ53 SB_DQS7
AT54 SA_DQ53 AN58 SB_DQ54
M_A_DQ54 AP56 M_B_DQ55 AR58
M_A_DQ55 SA_DQ54 M_B_DQ56 SB_DQ55
AP52 SA_DQ55 AK58 SB_DQ56
M_A_DQ56 AN57 M_B_DQ57 AL58
M_A_DQ57 SA_DQ56 M_B_DQ58 SB_DQ57
AN53 SA_DQ57 AG58 SB_DQ58
B M_A_DQ58 M_B_DQ59 B
AG56 SA_DQ58 AG59 SB_DQ59
M_A_DQ59 AG53 M_B_DQ60 AM60
M_A_DQ60 SA_DQ59 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] 15
AN55 SA_DQ60 M_A_A[15:0] 14 AL59 SB_DQ61 SB_MA0 BF32
M_A_DQ61 AN52 BG35 M_A_A0 M_B_DQ62 AF61 BE33 M_B_A1
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AG55 SA_DQ62 SA_MA1 BB34 AH60 SB_DQ63 SB_MA2 BD33
M_A_DQ63 AK56 BE35 M_A_A2 AU30 M_B_A3
SA_DQ63 SA_MA2 M_A_A3 SB_MA3 M_B_A4
SA_MA3 BD35 SB_MA4 BD30
AT34 M_A_A4 AV30 M_B_A5
SA_MA4 M_A_A5 SB_MA5 M_B_A6
SA_MA5 AU34 SB_MA6 BG30
BB32 M_A_A6 15 M_B_BS0 BG39 BD29 M_B_A7
SA_MA6 M_A_A7 SB_BS0 SB_MA7 M_B_A8
14 M_A_BS0 BD37 SA_BS0 SA_MA7 AT32 15 M_B_BS1 BD42 SB_BS1 SB_MA8 BE30
14 M_A_BS1 BF36 AY32 M_A_A8 15 M_B_BS2 AT22 BE28 M_B_A9
SA_BS1 SA_MA8 M_A_A9 SB_BS2 SB_MA9 M_B_A10
14 M_A_BS2 BA28 SA_BS2 SA_MA9 AV32 SB_MA10 BD43
BE37 M_A_A10 AT28 M_B_A11
SA_MA10 M_A_A11 SB_MA11 M_B_A12
SA_MA11 BA30 SB_MA12 AV28
BC30 M_A_A12 15 M_B_CAS# AV43 BD46 M_B_A13
SA_MA12 M_A_A13 SB_CAS# SB_MA13 M_B_A14
14 M_A_CAS# BE39 SA_CAS# SA_MA13 AW41 15 M_B_RAS# BF40 SB_RAS# SB_MA14 AT26
14 M_A_RAS# BD39 AY28 M_A_A14 15 M_B_W E# BD45 AU22 M_B_A15
SA_RAS# SA_MA14 M_A_A15 SB_WE# SB_MA15
14 M_A_W E# AT41 SA_WE# SA_MA15 AU26

IVY-BRIDGE-GP-NF
IVY-BRIDGE-GP-NF 71.00IVY.A0U
71.00IVY.A0U

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 6 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

Vinafix.com
CFG2
CPU1E 5 OF 9
D D

1
PEG Static Lane Reversal
R702
1KR2J-1-GP 1: Normal Operation; Lane #
71 CFG0 CFG0 B50 N59 BCLK_ITP 1 TP728 TPAD14-OP-GP SG CFG[2] definition matches socket pin map definition
TPAD14-OP-GP TP701 CFG1 CFG0 BCLK_ITP BCLK_ITP# TP729 TPAD14-OP-GP
1 C51 N58 1

2
CFG1 BCLK_ITP#
CFG2 B54 0:Lane Reversed
TPAD14-OP-GP TP702 CFG3 CFG2
1 D53 CFG3
TPAD14-OP-GP TP723 1 CFG4 A51 N42
CFG5 CFG4 RSVD30
C53 CFG5 RSVD31 L42
CFG6 C55 L45
TPAD14-OP-GP TP703 CFG7 CFG6 RSVD32
1 H49 CFG7 RSVD33 L47
A55 CFG8
H51 CFG9
K49 CFG10 RSVD34 M13
K53 CFG11 RSVD35 M14 Display Port Presence Strap
F53 CFG12 RSVD36 U14
G53 W14 1: Disabled; No Physical Display Port
CFG13 RSVD37
L51 CFG14 RSVD38 P13 CFG[4] attached to Embedded Display Port
F51 CFG15
TPAD14-OP-GP TP712 1 CFG16 D52 0: Enabled; An external Display Port device is
CFG16
L53 CFG17 RSVD39 AT49 connected to the Embedded Display Port
RSVD40 K24

TPAD14-OP-GP TP725 1VCC_VAL_SENSE H43

RESERVED
TPAD14-OP-GP TP726 VCC_VAL_SENSE
1VSS_VAL_SENSE K43 VSS_VAL_SENSE RSVD41 AH2
RSVD42 AG13
RSVD43 AM14
TPAD14-OP-GP TP722 1VAXG_VAL_SENSE H45 AM15
TPAD14-OP-GP TP724 VAXG_VAL_SENSE RSVD44
C 1VSSAXG_VAL_SENSE K45 VSSAXG_VAL_SENSE
CFG5 C

N50 CFG6 PCIE Port Bifurcation Straps

TPAD14-OP-GP TP727 RSVD45
1VCC_DIE_SENSE F48 VCC_DIE_SENSE

1
TPAD14-OP-GP TP730 1VSS_DIE_SENSE G48 RSVD47 R701 R704 CFG[6:5] 11: 1x16 PCI Express
H48
K48
RSVD6 DY 1KR2J-1-GP SG 1KR2J-1-GP
10: 2 x8 - PCI Express
RSVD7 TP_DC_TEST_A4 TP714 TPAD14-OP-GP
A4 1

2
DC_TEST_A4
DC_TEST_C4 C4 01: Reserved
BA19 D3 DC_TEST_C4_D3
RSVD8 DC_TEST_D3 TP_DC_TEST_D1 TP715 TPAD14-OP-GP
AV19 RSVD9 DC_TEST_D1 D1 1 00: 1x8, 2x4 PCI Express
AT21 A58 TP_DC_TEST_A58 1 TP716 TPAD14-OP-GP
RSVD10 DC_TEST_A58
BB21 RSVD11 DC_TEST_A59 A59
BB19 C59 TP_DC_TEST_A59_C59
RSVD12 DC_TEST_C59
AY21 RSVD13 DC_TEST_A61 A61
BA22 C61 TP_DC_TEST_A61_C61
RSVD14 DC_TEST_C61 TP_DC_TEST_D61 TP717 TPAD14-OP-GP
AY22 RSVD15 DC_TEST_D61 D61 1
AU19 RSVD16 DC_TEST_BD61 BD61 TP_DC_TEST_BD61 1 TP718 TPAD14-OP-GP
AU21 RSVD17 DC_TEST_BE61 BE61
BD21 RSVD18 DC_TEST_BE59 BE59 TP_DC_TEST_BE59_BE61
BD22 RSVD19 DC_TEST_BG61 BG61
BD25 RSVD20 DC_TEST_BG59 BG59 DC_TEST_BG59_BG61
BD26 RSVD21 DC_TEST_BG58 BG58 TP_DC_TEST_BG58 1 TP719 TPAD14-OP-GP
BG22 BG4 TP_DC_TEST_BG4 1 TP720 TPAD14-OP-GP
RSVD22 DC_TEST_BG4
BE22 RSVD23 DC_TEST_BG3 BG3
BG26 BE3 DC_TEST_BE3_BG3
RSVD24 DC_TEST_BE3
BE26 RSVD25 DC_TEST_BG1 BG1
BF23 BE1 DC_TEST_BE1_BG1
B RSVD26 DC_TEST_BE1 TP_DC_TEST_BD1 TP721 TPAD14-OP-GP B
BE24 RSVD27 DC_TEST_BD1 BD1 1

IVY-BRIDGE-GP-NF
71.00IVY.A0U

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RESERVED)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 7 of 106

5 4 3 2 1
 5 4 3 2 1

SSID = CPU
1u Cap x13

CPU1F POWER 6 OF 9
22u Cap x3
10u Cap x 9 VCCP_CPU

8.5A
VCC_CORE AF46
VCCIO1
AG48
X01_0412 33A VCCIO3
VCCIO4
AG50

C862
SC1U6D3V2KX-GP

C864
SC1U6D3V2KX-GP

C869
SC1U6D3V2KX-GP
Vinafix.com
A26 AG51 VCCIO Output Decoupling Recommendation:

1
VCC1 VCCIO5
A29 AJ17 330u x 2(Remove)
VCC2 VCCIO6
A31 AJ21
VCC_CORE A34
VCC3 VCCIO7
AJ25
DY DY DY 10u x 10(0603)

2
VCC4 VCCIO8
22u Cap x20 A35
VCC5 VCCIO9
AJ43 1u x 26(0402)
D A38 AJ47 D
VCC6 VCCIO10
A39 AK50
VCC7 VCCIO11
A42 AK51
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
VCC8 VCCIO12
C801

C804

C805

C806

C807

C808

C809

C810
C26 AL14 VCCPQ Output Decoupling Recommendation:
1

1
VCC9 VCCIO13
C819

C820

C27 AL15 1u x 1(0402)

VCC10 VCCIO14
C32 AL16
DY C34
VCC11 VCCIO15
AL20

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
2

2
VCC12 VCCIO16

C877
SC1U6D3V2KX-GP
C37 AL22

1
VCC13 VCCIO17

C871

C872

C873
C39 AL26
VCC14 VCCIO18
C42 AL45
D27
VCC15 VCCIO19
AL48 DY Voltage Rail Voltage(V) Iccmax(A)

2
VCC16 VCCIO20
D32 AM16
VCC17 VCCIO21
D34 AM17
VCC18 VCCIO22
D37 AM21 VCC_CORE(ULV) 0.3~1.52 33
VCC19 VCCIO23
D39 AM43
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

PEG IO AND DDR IO

VCC20 VCCIO24
C822

C823

C824

C828
D42 AM47 VAXG(ULV) 0~1.52 29
1

1
VCC21 VCCIO25
C811

C812

C813

C816

C818
E26 AN20
VCC22 VCCIO26

C863
SC10U6D3V3MX-GP

C879
SC10U6D3V3MX-GP

C880
SC10U6D3V3MX-GP

C881
SC10U6D3V3MX-GP

C882
SC10U6D3V3MX-GP
E28 AN42 VCCIO 1.05 8.5

1
VCC23 VCCIO27
E32 AN45
2

2
VCC24 VCCIO28
E34 AN48 Added, cause the VDDQ 1.5 5
E37
VCC25 VCCIO29
1.05V far away CPU
DY

2
VCC26
E38
VCC27
VCCSA 0.9 4

CORE SUPPLY
F25
VCC28
F26 VCCPLL 1.8 1.2
VCC29 VCCP_CPU
F28
VCC30
Layout Note: 10u x 12 Cap place during CPU & IMVP F32
VCC31 X01_0424
F34
VCC32
F37 AA14
VCC33 VCCIO30
F38 AA15
SC10U6D3V5KX-1GP

VCC34 VCCIO31
SC10U6D3V5KX-1GP

F42 AB17
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

VCC35 VCCIO32

SC10U6D3V3MX-GP

C885
SC1U6D3V2KX-GP

C883
SC1U6D3V2KX-GP

C884
SC1U6D3V2KX-GP

C886
SC1U6D3V2KX-GP

C888
SC1U6D3V2KX-GP

C887
SC1U6D3V2KX-GP

C889
SC1U6D3V2KX-GP

C890
SC1U6D3V2KX-GP

C891
SC1U6D3V2KX-GP
C817

C814

C815

G42 AB20
1

1
VCC36 VCCIO33
C802

C803

C830

C832

C847
H25 AC13
VCC37 VCCIO34
H26 AD16
H28
VCC38 VCCIO35
AD18
DY
2

2
VCC39 VCCIO36
H29 AD21
VCC40 VCCIO37
H32 AE14
VCC41 VCCIO38
H34 AE15
VCC42 VCCIO39
H35 AF16
VCC43 VCCIO40
H37 AF18
VCC44 VCCIO41
Layout Note: 2.2u x 10 Cap place under CPU H38
VCC45 VCCIO42
AF20
H40 AG15
VCC46 VCCIO43

C895
SC10U6D3V3MX-GP

C897
SC10U6D3V3MX-GP

C893
SC10U6D3V3MX-GP

C896
SC10U6D3V3MX-GP
C J25 AG16 C
SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

1
VCC47 VCCIO44
C827

C840

C841

C842

C844

C850

J26 AG17
1

VCC48 VCCIO45
J28 AG20
J29
VCC49 VCCIO46
AG21
DY DY DY DY
DY DY

2
VCC50 VCCIO47
J32 AJ14
2

VCC51 VCCIO48
J34 AJ15
VCC52 VCCIO49
J35
VCC53
J37
VCC54
J38
VCC55
J40
VCC56
J42
VCC57
K26 W16
VCC58 VCCIO50
K27 W17
VCC59 VCCIO51
K29
VCC60
K32
VCC61
K34
VCC62
K35
VCC63
K37
VCC64
K39
VCC66 H_SNB_IVB#_PWRCTRL TP801 TPAD14-OP-GP
K42 BC22 1
VCC67 VCCIO_SEL
L25
VCC68
VCC Output Decoupling Recommendation: L28
VCC69
CRB is DY
1.9m ohm loadline design:(for SV) L33
VCC70
470u x 4(Remove)
L36
VCC71 +V1.05S_VCCPQE_R
X02_0611 VCCP_CPU VCCP_CPU
L40 R812
VCC72
22u x 20(0805) N26
VCC73

QUIET
RAILS
2.2u x 35(0402) N30 AM25 1 2
VCC74 VCCPQE1 0R0402-PAD-2-GP
N34 AN22
Layout Note:

1
VCC75 VCCPQE2
N38

1
VCC76 C826 R803, R804, R805 need close to CPU
2.9m ohm loadline design:(for ULV/LV) SC1U6D3V2KX-GP R805 R804
Alert# signal must be routed between the Clock and Data

2
75R2F-2-GP 130R2F-1-GP
330u x 3(Remove) lines to reduce the cross talk between them
22u x 12(0805) R803

2
2.2u x 16(0402) 43R2J-GP
A44 H_CPU_SVIDALRT# 1 2
VIDALERT# VR_SVID_ALERT# 42
B43 H_CPU_SVIDCLK
VIDSCLK H_CPU_SVIDCLK 42 Need place Pull Hi

SVID
C44 H_CPU_SVIDDAT
VIDSOUT H_CPU_SVIDDAT 42
at IMVP page
VCC_CORE
B B
Layout Note:

1
R801 1. PH/PL resisors place close CPU
100R2F-L1-GP-U 2. SENSE signal recommend differential routing
3. VCC_SENSE 25ohm~34ohm

2
F43 VCCSENSE

SENSE LINES
VCC_SENSE VCCSENSE 42
G43 VSSSENSE VSSSENSE 42
VSS_SENSE

1
VCCP_CPU
R802
100R2F-L1-GP-U

1
AN16
VCCIO_SENSE R807
AN17

2
VSS_SENSE_VCCIO
10R2F-L-GP

VCCIO_SENSE 45

2
VSSIO_SENSE 45

1
IVY-BRIDGE-GP-NF
71.00IVY.A0U R806
10R2F-L-GP
Layout Note:

2
1. PH/PL resisors place close CPU
2. SENSE signal recommend differential routing
3. VCCIO_SENSE_VCCIO 55 ohm

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_CORE)
Size Document Number Rev
A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 8 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = CPU Layout Note: Voltage Rail Voltage(V) Iccmax(A)

CPU1G POWER 7 OF 9
+V_SM_VREF_CNT should have 10 mil trace width
VCC_CORE(ULV) 0.3~1.52 33
+V_SM_VREF_CNT
VCC_GFXCORE X01_0424 29A VAXG(ULV) 0~1.52 29
X01_0424 SM_VREF AY43
AA46 VCCIO 1.05 8.5
Vinafix.com

VREF
VAXG1 RN902
AB47

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
VAXG2

C904

C911

C919

C920

C921

C922

C923

C962

C963

C964
AB50 VAXG3 SA_DIMM_VREFDQ BE7 DDR_W R_VREFA 3 2 VDDQ 1.5 5

1
AB51 BG7 DDR_W R_VREFB 4 1
AB52
VAXG4 SB_DIMM_VREFDQ DY VCCSA 0.9 4
D
DY DY DY DY AB53
VAXG5 D

2
VAXG6 SRN1KJ-7-GP
22u Cap x 20 AB55 VCCPLL 1.8 1.2
VAXG7
AB56 VAXG8
10u Cap x 6 AB58 VAXG9
AB59 VAXG10
1u Cap x 7 AC61 VAXG11 1D5V_S0
AD47 VAXG12
X01_0424 AD48
AD50
VAXG13
VAXG14
5A
AD51 AJ28

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
VAXG15 VDDQ1

- 1.5V RAILS
C955

C956

C957

C958

C959

C960

C961

C965

C966

C967
AD52 VAXG16 VDDQ2 AJ33
1

1
AD53 VAXG17 VDDQ3 AJ36
AD55 AJ40
DY DY DY VAXG18 VDDQ4

1
C944
SC1U6D3V2KX-GP

C945
SC1U6D3V2KX-GP

C946
SC1U6D3V2KX-GP

C947
SC1U6D3V2KX-GP

C948
SC1U6D3V2KX-GP

C949
SC1U6D3V2KX-GP

C950
SC1U6D3V2KX-GP

C951
SC1U6D3V2KX-GP

C952
SC1U6D3V2KX-GP

C953
SC1U6D3V2KX-GP
AD56 AL30
2

2
VAXG19 VDDQ5
AD58 AL34
AD59
VAXG20 VDDQ6
AL38 DY DY DY DY DY DY DY DY

2
VAXG21 VDDQ7
AE46 VAXG22 VDDQ8 AL42
N45 VAXG23 VDDQ9 AM33
X01_0424 P47 VAXG24 VDDQ10 AM36
X01_0424 P48 VAXG25 VDDQ11 AM40
P50 VAXG26 VDDQ12 AN30
X02_0613 P51 VAXG27 VDDQ13 AN34
X02_0613 P52 VAXG28 VDDQ14 AN38
P53 AR26

DDR3
VAXG29 VDDQ15
P55 AR28

GRAPHICS
VAXG30 VDDQ16

1
C936
SC10U6D3V3MX-GP

C937
SC10U6D3V3MX-GP

C938
SC10U6D3V3MX-GP

C939
SC10U6D3V3MX-GP

C940
SC10U6D3V3MX-GP

C941
SC10U6D3V3MX-GP

C942
SC10U6D3V3MX-GP

C943
SC10U6D3V3MX-GP
C901

C902

C903

C905

C907

C908
P56 AR30
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
VAXG31 VDDQ17
1

1
P61 AR32
T48
VAXG32 VDDQ18
AR34 DY DY DY DY DY
DY DY DY

2
C VAXG33 VDDQ19 C
T58 AR36
2

2
VAXG34 VDDQ20
T59 VAXG35 VDDQ21 AR40
T61 VAXG36 VDDQ22 AV41
U46 VAXG37 VDDQ23 AW26
V47 VAXG38 VDDQ24 BA40
V48 VAXG39 VDDQ25 BB28
V50 VAXG40 VDDQ26 BG33
V51
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
VAXG41
V52 VAXG42
VDDQ Output Decoupling Recommendation:
V53 VAXG43 330u x 1(Remove)
1

1
C912

C913

C914

C915

C916

C917

C918
V55
V56
VAXG44 10u x 8(0603)
DY DY DY DY DY DY DY V58
VAXG45 1u x 10(0402)
2

VAXG46
V59 VAXG47
W50 VAXG48
W51 VAXG49
W52 VAXG50
VCCDQ Output Decoupling Recommendation:
W53 VAXG51 1u x 1(0402)
W55 VAXG52
W56 VAXG53
VCC_GFXCORE W61 VAXG54
Y48 VAXG55
Y61 VAXG56
Layout Note:
1

1. PH/PL resisors place close CPU R903 +V1.5S_VCCD_Q 1D5V_S0

2. SENSE signal recommend differential routing 100R2F-L1-GP-U
R909

QUIET RAILS
AM28 2 1

SENSE
LINES
2

B VCC_AXG_SENSE F45 VCCDQ1 B

42 VCC_AXG_SENSE VAXG_SENSE VCCDQ2 AN26
42 VSS_AXG_SENSE VSS_AXG_SENSE G45 0R0402-PAD-2-GP
VSSAXG_SENSE

1
C954
SC1U6D3V2KX-GP
X02_0611
1

R904

2
VCCAXG Output Decoupling Recommendation: 100R2F-L1-GP-U VCCSA Power Select
3.9m ohm loadline design:(for GT2)
1.8V RAIL
2

470u x 2(remove) BB3 Voltage(V) VID[0] VID[1]

22u x 6(0805) VCCPLL1
BC1 VCCPLL2
10u x 6(0603) 1D8V_S0 BC4
1u x 11(0402) 1.2A VCCPLL3
0.9 0 0

VDDQ_SENSE BC43 TP_VDDQ_SENSE 1 TP901 TPAD14-OP-GP LV & ULV

1

1
C924
SC1U6D3V2KX-GP

C925
SC1U6D3V2KX-GP

4.6m ohm loadline design:(for GT1) BA43 TP_VDDQ_VSS 1 TP902 TPAD14-OP-GP 0.85
VSS_SENSE_VDDQ
SENSE LINES

330u x 2(remove) 0 1
DY L17
2

22u x 5(0805) L21

VCCSA1 Others
10u x 6(0603) VCCSA2
N16 VCCSA3 0.8
1u x 6(0402) N20 VCCSA4
0D85V_S0 N22
4A
SA RAIL

VCCSA5 0.775 1 0
P17 VCCSA6
P20 VCCSA7 VCCSA_SENSE U10 VCCSA_SENSE 48
R16 VCCSA8
1

1
C930
SC10U6D3V3MX-GP

C929
SC10U6D3V3MX-GP

C928
SC10U6D3V3MX-GP

C927
SC10U6D3V3MX-GP

C926
SC10U6D3V3MX-GP

VCCPLL Output Decoupling Recommendation: R18 VCCSA9

0.75 1 1
330u x 1(Remove) R21
DY DY DY DY DY U15
VCCSA10
VCCSA VID
2

1u x 2(0402) V16
VCCSA11
A VCCSA12 <Core Design> A
V17 D48 VCCSA_SEL0
VCCSA13 VCCSA_VID0 VCCSA_SEL0 48
lines

V18 D49 VCCSA_SEL1

VCCSA14 VCCSA_VID1 VCCSA_SEL1 48
VCCSA Output Decoupling Recommendation:
330u x 1(Remove)
V21
W20
VCCSA15
VCCSA16
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
10u x 5(0603)
1

1
C935
SC1U6D3V2KX-GP

C934
SC1U6D3V2KX-GP

C933
SC1U6D3V2KX-GP

C932
SC1U6D3V2KX-GP

C931
SC1U6D3V2KX-GP

Taipei Hsien 221, Taiwan, R.O.C.

1u x 5(0402)
DY DY DY Title
2

IVY-BRIDGE-GP-NF
71.00IVY.A0U
CPU (VCC_GFXCORE)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 9 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
CPU1H 8 OF 9
CPU1I 9 OF 9

A13 AM38 BG17 M4

A17
A21
VSS1
VSS2
VSS3
Vinafix.com VSS91
VSS92
VSS93
AM4
AM42
BG21
BG24
VSS181
VSS182
VSS183
VSS250
VSS251
VSS252
M58
M6
A25 VSS4 VSS94 AM45 BG28 VSS184 VSS253 N1
D A28 VSS5 VSS95 AM48 BG37 VSS185 VSS254 N17 D
A33 VSS6 VSS96 AM58 BG41 VSS186 VSS255 N21
A37 VSS7 VSS97 AN1 BG45 VSS187 VSS256 N25
A40 VSS8 VSS98 AN21 BG49 VSS188 VSS257 N28
A45 VSS9 VSS99 AN25 BG53 VSS189 VSS258 N33
A49 VSS10 VSS100 AN28 BG9 VSS190 VSS259 N36
A53 VSS11 VSS101 AN33 C29 VSS191 VSS260 N40
A9 VSS12 VSS102 AN36 C35 VSS192 VSS261 N43
AA1 VSS13 VSS103 AN40 C40 VSS193 VSS262 N47
AA13 VSS14 VSS104 AN43 D10 VSS194 VSS263 N48
AA50 VSS15 VSS105 AN47 D14 VSS195 VSS264 N51
AA51 VSS16 VSS106 AN50 D18 VSS196 VSS265 N52
AA52 VSS17 VSS107 AN54 D22 VSS197 VSS266 N56
AA53 VSS18 VSS108 AP10 D26 VSS198 VSS267 N61
AA55 VSS19 VSS109 AP51 D29 VSS199 VSS268 P14
AA56 VSS20 VSS110 AP55 D35 VSS200 VSS269 P16
AA8 VSS21 VSS111 AP7 D4 VSS201 VSS270 P18
AB16 VSS22 VSS112 AR13 D40 VSS202 VSS271 P21
AB18 AR17 D43 P58
AB21
AB48
VSS23
VSS24
VSS25
VSS113
VSS114
VSS115
AR21
AR41
D46
D50
VSS203
VSS204
VSS205
VSS VSS272
VSS273
VSS274
P59
P9
AB61 VSS26 VSS116 AR48 D54 VSS206 VSS275 R17
AC10 VSS27 VSS117 AR61 D58 VSS207 VSS276 R20
AC14 VSS28 VSS118 AR7 D6 VSS208 VSS277 R4
AC46 VSS29 VSS119 AT14 E25 VSS209 VSS278 R46
AC6 VSS30 VSS120 AT19 E29 VSS210 VSS279 T1
AD17 VSS31 VSS121 AT36 E3 VSS211 VSS280 T47
AD20 VSS32 VSS122 AT4 E35 VSS212 VSS281 T50
AD4 AT45 E40 T51
C AD61
AE13
VSS33
VSS34
VSS35
VSS VSS123
VSS124
VSS125
AT52
AT58
F13
F15
VSS213
VSS214
VSS215
VSS282
VSS283
VSS284
T52
T53
C

AE8 VSS36 VSS126 AU1 F19 VSS216 VSS285 T55

AF1 VSS37 VSS127 AU11 F29 VSS217 VSS286 T56
AF17 VSS38 VSS128 AU28 F35 VSS218 VSS287 U13
AF21 VSS39 VSS129 AU32 F40 VSS219 VSS288 U8
AF47 VSS40 VSS130 AU51 F55 VSS220 VSS289 V20
AF48 VSS41 VSS131 AU7 G51 VSS221 VSS290 V61
AF50 VSS42 VSS132 AV17 G6 VSS222 VSS291 W13
AF51 VSS43 VSS133 AV21 G61 VSS223 VSS292 W15
AF52 VSS44 VSS134 AV22 H10 VSS224 VSS293 W18
AF53 VSS45 VSS135 AV34 H14 VSS225 VSS294 W21
AF55 VSS46 VSS136 AV40 H17 VSS226 VSS295 W46
AF56 VSS47 VSS137 AV48 H21 VSS227 VSS296 W8
AF58 VSS48 VSS138 AV55 H4 VSS228 VSS297 Y4
AF59 VSS49 VSS139 AW13 H53 VSS229 VSS298 Y47
AG10 VSS50 VSS140 AW43 H58 VSS230 VSS299 Y58
AG14 VSS51 VSS141 AW61 J1 VSS231 VSS300 Y59
AG18 VSS52 VSS142 AW7 J49 VSS232
AG47 VSS53 VSS143 AY14 J55 VSS233
AG52 VSS54 VSS144 AY19 K11 VSS234
AG61 VSS55 VSS145 AY30 K21 VSS235
AG7 VSS56 VSS146 AY36 K51 VSS236

NCTF TEST PIN：

A5,A57,BC61,BG5
AH4 AY4 K8 A5

BG57,C3,E1,E61
VSS57 VSS147 VSS237 VSS_NCTF_1#A5
AH58 VSS58 VSS148 AY41 L16 VSS238 VSS_NCTF_2#A57 A57
AJ13 VSS59 VSS149 AY45 L20 VSS239 VSS_NCTF_3#BC61 BC61
AJ16 VSS60 VSS150 AY49 L22 VSS240 VSS_NCTF_8#BG5 BG5
AJ20 VSS61 VSS151 AY55 L26 VSS241 VSS_NCTF_9#BG57 BG57
AJ22 VSS62 VSS152 AY58 L30 VSS242 VSS_NCTF_10#C3 C3
B B
AJ26 VSS63 VSS153 AY9 L34 VSS243 VSS_NCTF_13#E1 E1
AJ30 VSS64 VSS154 BA1 L38 VSS244 VSS_NCTF_14#E61 E61

NCTF
AJ34 VSS65 VSS155 BA11 L43 VSS245
AJ38 VSS66 VSS156 BA17 L48 VSS246
AJ42 VSS67 VSS157 BA21 L61 VSS247 VSS_NCTF_4 BD3
AJ45 VSS68 VSS158 BA26 M11 VSS248 VSS_NCTF_5 BD59
AJ48 VSS69 VSS159 BA32 M15 VSS249 VSS_NCTF_6 BE4
AJ7 VSS70 VSS160 BA48 VSS_NCTF_7 BE58
AK1 VSS71 VSS161 BA51 VSS_NCTF_11 C58
AK52 VSS72 VSS162 BB53 VSS_NCTF_12 D59
AL10 VSS73 VSS163 BC13
AL13 VSS74 VSS164 BC5
AL17 VSS75 VSS165 BC57
AL21 BD12 IVY-BRIDGE-GP-NF
VSS76 VSS166
AL25 BD16
AL28
VSS77 VSS167
BD19
71.00IVY.A0U
VSS78 VSS168
AL33 VSS79 VSS169 BD23
AL36 VSS80 VSS170 BD27
AL40 VSS81 VSS171 BD32
AL43 VSS82 VSS172 BD36
AL47 VSS83 VSS173 BD40
AL61 VSS84 VSS174 BD44
AM13 VSS85 VSS175 BD48
AM20 VSS86 VSS176 BD52
AM22 VSS87 VSS177 BD56
AM26 VSS88 VSS178 BD8
AM30 VSS89 VSS179 BE5
AM34 VSS90 VSS180 BG13
A <Core Design> A

Wistron Corporation
IVY-BRIDGE-GP-NF 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
71.00IVY.A0U
Title

CPU (VSS)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 10 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

XDP
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 11 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 12 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C
(Blanking) C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 13 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY 6 M_A_A[15:0]

DM1

M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2
M_A_A2 A1 NP2
96
M_A_A3 A2
95 110 M_A_RAS# 6
M_A_A4 A3 RAS#
92 113 M_A_WE# 6
M_A_A5 A4 WE#
91 115 M_A_CAS# 6
M_A_A6 A5 CAS# SA0_DIMA
M_A_A7
90
A6 SA1_DIMA
Note:
86 114 M_A_DIMA_CS#0 6
M_A_A8 A7 CS0# SA0 DIM0 = 0, SA1_DIM0 = 0
89 121 M_A_DIMA_CS#1 6
M_A_A9 A8 CS1#
85 SO-DIMMA SPD Address is 0xA0

1
M_A_A10 A9
107 73 M_A_DIMA_CKE0 6
A10/AP CKE0
M_A_A11 SO-DIMMA TS Address is 0x30
Vinafix.com
84 74 M_A_DIMA_CKE1 6 R1401 R1402
M_A_A12 A11 CKE1 0R0402-PAD-2-GP 0R0402-PAD-2-GP
83
M_A_A13 A12
119 101 M_A_DIMA_CLK_DDR0 6
M_A_A14 A13 CK0
80 103 M_A_DIMA_CLK_DDR#0 6

2
M_A_A15 A14 CK0#
78
A15
D 79 102 M_A_DIMA_CLK_DDR1 6 D
6 M_A_BS2 A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 6
CK1#
109
6 M_A_BS0 BA0
108 11
6 M_A_BS1 BA1 DM0
6 M_A_DQ[63:0] 28
M_A_DQ0 DM1
5 46
DDR_VREF_S3 M_A_DQ1 DQ0 DM2
7 63
M_A_DQ2 DQ1 DM3
15 136
Layout Note: M_A_DQ3 17
DQ2 DM4
153
2

M_A_DQ4 DQ3 DM5

Place these caps 4
DQ4 DM6
170
X02_0611 R1405 M_A_DQ5 6 187
0R0402-PAD-2-GP
close to VREF_CA M_A_DQ6 DQ5 DM7
16
M_A_DQ7 DQ6
18 200 PCH_SMBDATA 15,20,65,66,69
M_VREF_CA_DIMMA M_A_DQ8 DQ7 SDA
21 202
1

DQ8 SCL PCH_SMBCLK 15,20,65,66,69

M_A_DQ9 23
M_A_DQ10 DQ9 3D3V_S0
33 198
M_A_DQ11 DQ10 EVENT#
35
M_A_DQ12 DQ11
C1427

C1426

22 199
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

M_A_DQ13 DQ12 VDDSPD

24
M_A_DQ14 DQ13 SA0_DIMA
C1428

34 197
DY
SC2D2U10V3KX-1GP

2
M_A_DQ15 DQ14 SA0 SA1_DIMA C1401
36 201
2

DQ15 SA1

EC1401
SCD1U10V2KX-5GP

EC1402
SCD1U10V2KX-5GP
M_A_DQ16 39 SCD1U10V2KX-5GP
M_A_DQ17 41
DQ16
77 DY DY DY

1
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 1D5V_S3
53 125
M_A_DQ20 DQ19 NC#/TEST
40
M_A_DQ21 DQ20
X02_0615 X02_0615 42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ23 52
DQ22
DQ23
VDD2
VDD3
81 RF
M_A_DQ24 57 82
DDR_VREF_S3 M_A_DQ25 DQ24 VDD4
59 87
Layout Note: M_A_DQ26 67
DQ25 VDD5
88
M_A_DQ27 DQ26 VDD6
Place these caps 69 93
2

M_A_DQ28 DQ27 VDD7

close to VREF_DQ 56 94
R1404 M_A_DQ29 DQ28 VDD8 1D5V_S3
X02_0611 58
DQ29 VDD9
99
0R0402-PAD-2-GP M_A_DQ30 68 100
M_A_DQ31 DQ30 VDD10
70 105
M_VREF_DQ_DIMMA M_A_DQ32 DQ31 VDD11
129 106
1

M_A_DQ33 DQ32 VDD12

131 111
M_A_DQ34 DQ33 VDD13
141 112

ST330U2VDM-4-GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
M_A_DQ35 DQ34 VDD14

TC1401

C1403

C1404

C1405

C1406

C1407

C1408
143 117

1
M_A_DQ36 DQ35 VDD15
C1411

C1429

C 130 118 C
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

DQ36 VDD16

EC1403
SCD1U16V2KX-3GP

EC1404
SCD1U16V2KX-3GP
M_A_DQ37 132 123
M_A_DQ38 DQ37 VDD17 DY DY DY
C1423

140 124
DY
SC2D2U10V3KX-1GP

2
M_A_DQ39 DQ38 VDD18
142
2

M_A_DQ40 DQ39
147 2
M_A_DQ41 DQ40 VSS
149 3
M_A_DQ42 DQ41 VSS
157 8
M_A_DQ43 DQ42 VSS
159 9
M_A_DQ44 146
DQ43
DQ44
VSS
VSS
13 RF
X02_0615 X02_0615 M_A_DQ45 148 14
M_A_DQ46 DQ45 VSS
158 19
0D75V_S0 M_A_DQ47 DQ46 VSS
160 20

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
M_A_DQ48 DQ47 VSS

C1414

C1415

C1416

C1417
163 25

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

1
M_A_DQ49 DQ48 VSS
165 26
M_A_DQ50 DQ49 VSS
175 31
M_A_DQ51 DQ50 VSS
177 32

2
M_A_DQ52 DQ51 VSS
164 37
Layout Note:
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

M_A_DQ53 DQ52 VSS

C1419

C1420

C1418

166 38
1

M_A_DQ54 DQ53 VSS

Place these caps 174
DQ54 VSS
43
M_A_DQ55 176 44
DY close to VTT1 and M_A_DQ56 181
DQ55 VSS
48
2

VTT2. M_A_DQ57 DQ56 VSS

183
DQ57 VSS
49 X02_0615
M_A_DQ58 191 54
M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 60
M_A_DQ61 182
DQ60 VSS
61
Layout Note:
M_A_DQ62 DQ61 VSS
192
DQ62 VSS
65 Place these Caps near SO-DIMMA.
M_A_DQ63 194 66
DQ63 VSS
6 M_A_DQS#[7:0] 71
M_A_DQS#0 VSS
10 72
M_A_DQS#1 DQS0# VSS
27 127
M_A_DQS#2 DQS1# VSS 1D5V_S0 1D5V_S3
45 128
M_A_DQS#3 DQS2# VSS
62 133
M_A_DQS#4 DQS3# VSS
135 134
M_A_DQS#5 DQS4# VSS
152 138 1 2
M_A_DQS#6 DQS5# VSS
169 139
M_A_DQS#7 DQS6# VSS EC1421
186 144
DQS7# VSS SCD1U16V2KX-3GP
6 M_A_DQS[7:0] 145
M_A_DQS0 VSS
12 150
M_A_DQS1 DQS0 VSS
29 151
M_A_DQS2 DQS1 VSS
47 155 1 2
B M_A_DQS3 DQS2 VSS B
64 156
M_A_DQS4 DQS3 VSS
137 161
M_A_DQS5 DQS4 VSS EC1424
154 162
M_A_DQS6 DQS5 VSS SCD1U16V2KX-3GP
171 167
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
6 M_A_DIMA_ODT0
120
ODT0 VSS
178
Layout Note:
6 M_A_DIMA_ODT1 ODT1 VSS
VSS
179 For S3 reduction circuit's 1D5V return pass.
M_VREF_CA_DIMMA 126 184
VREF_CA VSS
1 185
Layout Note: M_VREF_DQ_DIMMA VREF_DQ VSS
189
VSS
All VREF traces should 15,37 DDR3_DRAMRST#
30
RESET# VSS
190
have width=20mil; 195
VSS
196
spacing=20 mil VSS
0D75V_S0 203 205
VTT1 VSS
204 206
VTT2 VSS

DDR3-204P-90-GP
62.10017.U81
2nd = 62.10017.P31
H =5.2 mm

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1
Size Document Number Rev
A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 14 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY DM2

6 M_B_A[15:0]
M_B_A0 98 NP1
M_B_A1 A0 NP1
97 NP2
M_B_A2 A1 NP2
96
M_B_A3 A2
95 110 M_B_RAS# 6
M_B_A4 A3 RAS#
92 113 M_B_WE# 6
M_B_A5 A4 WE#
M_B_A6
91
A5 CAS#
115 M_B_CAS# 6 Note:
90
M_B_A7 A6 SO-DIMMB SPD Address is 0xA4
86 114 M_B_DIMB_CS#0 6
M_B_A8 A7 CS0#
89 121 M_B_DIMB_CS#1 6 SO-DIMMB TS Address is 0x34
M_B_A9 A8 CS1#
85
M_B_A10 A9

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107 73 M_B_DIMB_CKE0 6
M_B_A11 A10/AP CKE0
84 74 M_B_DIMB_CKE1 6
M_B_A12 A11 CKE1
83
M_B_A13 A12
119 101 M_B_DIMB_CLK_DDR0 6
M_B_A14 A13 CK0
80 103 M_B_DIMB_CLK_DDR#0 6
DDR_VREF_S3 M_B_A15 A14 CK0#
D 78 D
A15
79 102 M_B_DIMB_CLK_DDR1 6
6 M_B_BS2 A16/BA2 CK1
104 M_B_DIMB_CLK_DDR#1 6
CK1#
109
2

6 M_B_BS0 BA0
108 11
R1505 6 M_B_BS1 BA1 DM0
X02_0611 6 M_B_DQ[63:0] DM1
28
0R0402-PAD-2-GP M_B_DQ0 5 46
M_B_DQ1 DQ0 DM2
7 63
M_VREF_CA_DIMMB M_B_DQ2 DQ1 DM3
15 136
1

M_B_DQ3 DQ2 DM4

17 153
M_B_DQ4 DQ3 DM5 3D3V_S0
4 170
Layout Note: M_B_DQ5 6
DQ4 DM6
187
M_B_DQ6 DQ5 DM7
C1523

C1522

Place these caps 16

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

M_B_DQ7 DQ6
close to VREF_CA 18 200 PCH_SMBDATA 14,20,65,66,69

1
M_B_DQ8 DQ7 SDA
C1524

21 202
DY
SC2D2U10V3KX-1GP

DQ8 SCL PCH_SMBCLK 14,20,65,66,69

M_B_DQ9 23 R1501
2

M_B_DQ10 DQ9 3D3V_S0 10KR2J-3-GP

33 198
M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199

2
M_B_DQ13 DQ12 VDDSPD
24

2
M_B_DQ14 DQ13 SA0_DIMB
34 197
DQ14 SA0 DY

EC1501
SCD1U10V2KX-5GP

EC1502
SCD1U10V2KX-5GP
X02_0615 X02_0615 M_B_DQ15 36 201 SA1_DIMB C1501
M_B_DQ16 39
DQ15 SA1 SCD1U10V2KX-5GP DY DY SA1_DIMB

1
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1 SA0_DIMB
51 122
M_B_DQ19 DQ18 NC#2 1D5V_S3
53 125
DDR_VREF_S3 M_B_DQ20 DQ19 NC#/TEST
40

1
M_B_DQ21 DQ20
42 75
M_B_DQ22 DQ21 VDD1 R1502
50 76
M_B_DQ23 52
DQ22 VDD2
81 RF 0R0402-PAD-2-GP
2

M_B_DQ24 DQ23 VDD3

57 82
R1503 M_B_DQ25 DQ24 VDD4
X02_0611 59 87

2
0R0402-PAD-2-GP M_B_DQ26 DQ25 VDD5
67 88
Layout Note: M_B_DQ27 69
DQ26 VDD6
93
M_VREF_DQ_DIMMB M_B_DQ28 DQ27 VDD7
Place these caps 56 94
1

M_B_DQ29 DQ28 VDD8

close to VREF_DQ 58 99
M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10 1D5V_S3
70 105
M_B_DQ32 DQ31 VDD11
C1515

C1517

129 106
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

M_B_DQ33 DQ32 VDD12

131 111
M_B_DQ34 DQ33 VDD13
C1516

141 112
DY
SC2D2U10V3KX-1GP

M_B_DQ35 DQ34 VDD14

C 143 117 C
2

M_B_DQ36 DQ35 VDD15

130 118

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP
2

2
DQ36 VDD16

EC1503
SCD1U16V2KX-3GP

EC1504
SCD1U16V2KX-3GP
M_B_DQ37

C1503

C1504

C1507

C1508

C1509
132 123

SC10U6D3V5KX-1GP
1

1
M_B_DQ38 DQ37 VDD17

C1510
140 124

1
M_B_DQ39 DQ38 VDD18
142
DY DY DY

1
M_B_DQ40 DQ39
147 2

2
M_B_DQ41 DQ40 VSS
X02_0615 X02_0615 149 3

2
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS
146 13
M_B_DQ45 DQ44 VSS
148 14
M_B_DQ46 158
DQ45
DQ46
VSS
VSS
19 RF
0D75V_S0 M_B_DQ47 160 20
M_B_DQ48 DQ47 VSS
163 25
Layout Note: M_B_DQ49 DQ48 VSS

C1511

C1512

C1513

EC1514
165 26

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

1
M_B_DQ50 DQ49 VSS
Place these caps 175
DQ50 VSS
31
M_B_DQ51 177 32
close to VTT1 and M_B_DQ52 DQ51 VSS
C1518

C1519

C1521

164 37
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

2
1

VTT2. M_B_DQ53 DQ52 VSS

166 38
M_B_DQ54 DQ53 VSS
174 43
DY M_B_DQ55 176
DQ54 VSS
44
2

M_B_DQ56 DQ55 VSS

181 48
M_B_DQ57 DQ56 VSS
183 49
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182
DQ61 VSS
61 X02_0615
M_B_DQ62 192 65
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS
6 M_B_DQS#[7:0] 71
M_B_DQS#0 VSS
10 72
M_B_DQS#1 27
DQS0# VSS
127
Layout Note:
M_B_DQS#2 DQS1# VSS
45
DQS2# VSS
128 Place these Caps near SO-DIMMB.
M_B_DQS#3 62 133
M_B_DQS#4 DQS3# VSS
135 134
M_B_DQS#5 DQS4# VSS
152 138
M_B_DQS#6 DQS5# VSS
169 139
M_B_DQS#7 DQS6# VSS
186 144
DQS7# VSS
6 M_B_DQS[7:0] 145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
B M_B_DQS2 DQS1 VSS B
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
137 161
M_B_DQS5 DQS4 VSS
154 162
M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
VSS
116 173
6 M_B_DIMB_ODT0 ODT0 VSS
120 178
6 M_B_DIMB_ODT1 ODT1 VSS
179
VSS
M_VREF_CA_DIMMB 126 184
VREF_CA VSS
M_VREF_DQ_DIMMB 1 185
VREF_DQ VSS
189
Layout Note: 30
VSS
190
14,37 DDR3_DRAMRST# RESET# VSS
All VREF traces should VSS
195
have width=20mil; 196
VSS
0D75V_S0 203 205
spacing=20 mil VTT1 VSS
204 206
VTT2 VSS

DDR3-204P-119-GP-U
62.10017.Z81
2nd = 62.10017.N41
H =5.2 mm

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2
Size Document Number Rev
A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 15 of 106
5 4 3 2 1
 5 4 3 2 1

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D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 16 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

Vinafix.com
D D

3D3V_S0

RN1701 4 OF 10 3D3V_S0
PCH1D
1 4 L_CTRL_DATA 27 L_BKLT_EN J47 AP43
L_CTRL_CLK L_BKLTEN SDVO_TVCLKINN
2 3 49 LVDS_VDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45

SRN2K2J-1-GP 49 L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42

3
4
SDVO_STALLP AM40
LVDS_DDC_CLK_R T40 RN1706
49 LVDS_DDC_CLK_R
49 LVDS_DDC_DATA_R LVDS_DDC_DATA_R K47 L_DDC_CLK
AP39 SRN2K2J-1-GP
Layout Note:
L_DDC_DATA SDVO_INTN
SDVO_INTP AP40 Close HDMI port
RN1702 L_CTRL_CLK T45
L_BKLT_EN L_CTRL_DATA L_CTRL_CLK
2 3 P39

2
1
LVDS_VDD_EN L_CTRL_DATA
1 4
LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK 51
SRN100KJ-6-GP TPAD14-OP-GP TP1701 1 LVDS_VBG AF36 M39
LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA 51

1
AE48
Layout Note: R1701 AE47
LVD_VREFH
AT49
2K37R2F-GP LVD_VREFL DDPB_AUXN
Place near PCH; DDPB_AUXP AT47
trace spacing=20mil DDPB_HPD AT40 HDMI_PCH_DET 51
2 49 LVDSA_CLK# AK39 LVDSA_CLK#

LVDS
49 LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42 HDMI_DATA2_R# 51
DDPB_0P AV40 HDMI_DATA2_R 51
49 LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45 HDMI_DATA1_R# 51
C AM47 AV46 C
49 LVDSA_DATA1# LVDSA_DATA#1 DDPB_1P HDMI_DATA1_R 51

Digital Display Interface

49 LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48 HDMI_DATA0_R# 51
AJ48 LVDSA_DATA#3 DDPB_2P AU47 HDMI_DATA0_R 51
DDPB_3N AV47 HDMI_CLK_R# 51
49 LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49 HDMI_CLK_R 51
49 LVDSA_DATA1 AM49 LVDSA_DATA1
49 LVDSA_DATA2 AK49 LVDSA_DATA2
AJ47 P46
LVDSA_DATA3 DDPC_CTRLCLK
P42
Layout Note:
DDPC_CTRLDATA
Layout Note: HDMI trace length to DC CAP. max 10000mil
AF40 LVDSB_CLK#
LVDS signal trace AF39 LVDSB_CLK DDPC_AUXN AP47
length max 14000mil DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
3D3V_S0 AH43 AY45
LVDSB_DATA0 DDPC_1P
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49

3
4
RN1707
SRN2K2J-1-GP N48 CRT_BLUE DDPD_CTRLCLK M43
P49 CRT_GREEN DDPD_CTRLDATA M36
T49 CRT_RED
2
1

B B
DDPD_AUXN AT45

CRT
CRT_DDCCLK T39 AT43
CRT_DDCDATA CRT_DDC_CLK DDPD_AUXP
M40 CRT_DDC_DATA DDPD_HPD BH41

DDPD_0N BB43
M47 CRT_HSYNC DDPD_0P BB45
M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
DAC_IREF_R T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
1

BG42
Layout Note: R1702 DDPD_3P
Place near PCH; 1KR2J-1-GP PANTHER-GP-NF
trace spacing=30mil 71.PANTH.00U
2

Notes:
1K 5%

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (LVDS/CRT/DDI)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 17 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

PCH1E 5 OF 10
RSVD1 AY7
RSVD2 AV7
BG26 AU3
Vinafix.com BJ26
BH25
TP1
TP2
TP3
RSVD3
RSVD4 BG4

BJ16 TP4 RSVD5 AT10

D BG16 TP5 RSVD6 BC8 D
AH38 TP6
AH37 TP7 RSVD7 AU2
AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3
C18 TP10 RSVD10 AT1
N30 TP11 RSVD11 AY3
H3 TP12 RSVD12 AT5
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1
AM5 TP15 RSVD15 BB1
Y13 TP16 RSVD16 BA3
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8

RSVD
RSVD21 BD4
RSVD22 BF6
Layout Note: B21 AV5
Trace Length : M20
TP21
TP22
RSVD23
RSVD24 AV10 USB Table
PCH ~~9000mil~~Cap~~1000mil~~CONN AY16 TP23
BG46 TP24 RSVD25 AT8 Pair Device
RSVD26 AY5 0 USB3.0 port1, With Power Share
RSVD27 BA2
USB3_RX1_N BE28 1 USB3.0 port2, Debug Port
USB3.0/2.0 Mapping Table 62
63
USB3_RX1_N
USB3_RX2_N
USB3_RX2_N BC30
USB3RN1
USB3RN2 RSVD28 AT12
USB3_RX3_N BE32 BF3 2 USB3.0 port3
C 82 USB3_RX3_N USB3_RX4_N USB3RN3 RSVD29 C
USB 3.0 Port USB 2.0 port 82 USB3_RX4_N BJ32 USB3RN4 DB
USB3_RX1_P BC28 3 USB3.0 port4
62 USB3_RX1_P USB3_RX2_P USB3RP1
Port 1 Port 0 BE30
63
82
USB3_RX2_P
USB3_RX3_P
USB3_RX3_P BF32
USB3RP2
USB3RP3
USB2.0 Signal Group 4 Touch Panel
Port 2 Port 1 USB3_RX4_P BG32 C24 USB_PN0 62
82 USB3_RX4_P USB3_TX1_N USB3RP4 USBP0N
62 USB3_TX1_N AV26 USB3TN1 USBP0P A24 USB_PP0 62 5 NC
Port 3 Port 2 63 USB3_TX2_N USB3_TX2_N BB26 C25 USB_PN1 63
USB3_TX3_N USB3TN2 USBP1N
82 USB3_TX3_N AU28 USB3TN3 USBP1P B25 USB_PP1 63 6 NC
Port 4 Port 3 82 USB3_TX4_N USB3_TX4_N AY30 C26 USB_PN2 82
USB3_TX1_P USB3TN4 USBP2N
62 USB3_TX1_P AU26 USB3TP1 USBP2P A26 USB_PP2 82 7 NC
63 USB3_TX2_P USB3_TX2_P AY26 K28 USB_PN3 82
USB3_TX3_P USB3TP2 USBP3N
82 USB3_TX3_P AV28 USB3TP3 USBP3P H28 USB_PP3 82 8 WWAN
82 USB3_TX4_P USB3_TX4_P AW30 E28 USB_PN4 82
3D3V_S0 USB3TP4 USBP4N
USBP4P D28 USB_PP4 82 9 NC
RN1803 C28
SRN10KJ-6-GP USBP5N
USBP5P A28 10 Card reader
8 1 PCH_GPIO50 C29
PCH_GPIO54 USBP6N
7 2 USBP6P B29 11 WLAN
6 3 PCH_GPIO02 INT_PIRQA# K40 N28
INT_PIRQB# PIRQA# USBP7N
5 4 K38 PIRQB# USBP7P M28 12 CAMERA

PCI
INT_PIRQC# H38 L30 USB_PN8 66
INT_PIRQD# PIRQC# USBP8N
G38 PIRQD# USBP8P K30 USB_PP8 66 13 NC
USBP9N G30
PCH_GPIO50 C46 E30
REQ1#/GPIO50 USBP9P

USB
PCH_GPIO52 C44 C30 USB_PN10 82
TPAD14-OP-GP TP1808 BBS_BIT1 PCH_GPIO54 REQ2#/GPIO52 USBP10N
1 E40 REQ3#/GPIO54 USBP10P A30 USB_PP10 82
USBP11N L32 USB_PN11 65
TPAD14-OP-GP TP1809 1 BBS_BIT0 BBS_BIT1 D47 K32 USB_PP11 65
BBS_BIT0 21 TPAD14-OP-GP TP1806 PCH_GPIO53 GNT1#/GPIO51 USBP11P
1 E42 GNT2#/GPIO53 USBP12N G32 USB_PN12 49
B PCI_GNT3# B
F46 GNT3#/GPIO55 USBP12P E32 USB_PP12 49
USBP13N C32
USBP13P A32
PCH_GPIO02 G42 PIRQE#/GPIO2
56 SATA_ODD_DA# G40 PIRQF#/GPIO3
C42 C33 USB_RBIAS 1 2
Boot Bios Strap
65 BLUETOOTH_EN
69 KB_LED_BL_DET D44
PIRQG#/GPIO4 USBRBIAS# R1811 Layout Note:
PIRQH#/GPIO5 22D6R2F-L1-GP 1. USBRBIAS/# use 50ohm single-ended impedance
USBRBIAS B33 spacing to other signal=15mil
GNT1#/GPIO51 SATA1GP/GPIO19 Boot BIOS Location TPAD14-OP-GP TP1802 1 PCI_PME# K10 PME# 2. Length < 500mil
PCI_PLTRST# C6 A14 USB_OC#0_1 USB_OC#0_1 62,63
0 0 LPC PLTRST# OC0#/GPIO59 USB_OC#2_3
OC1#/GPIO40 K20 USB_OC#2_3 82
B17 USB_OC#4_5
CLK_PCI_LPC OC2#/GPIO41 USB_OC#6_7
71 CLK_PCI_LPC H49 CLKOUT_PCI0 OC3#/GPIO42 C16
0 1 Reserved 20 CLK_PCI_FB R1805 1 2 22R2J-2-GP CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16 USB_OC#8_9
27 CLK_PCI_KBC R1806 1 2 22R2J-2-GP CLK_PCI_KBC_R J48 A16 USB_OC#10_11
CLKOUT_PCI2 OC5#/GPIO9 USB_OC#12_13
K42 CLKOUT_PCI3 OC6#/GPIO10 D14
1 0 Reserved H40 CLKOUT_PCI4 OC7#/GPIO14 C14 PCH_GPIO14
2

EC1802 EC1804
1 1 SPI(Default) PANTHER-GP-NF RN1802
DY DY
SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

SRN8K2J-2-GP-U
USB_OC#2_3 1 10 3D3V_S5
PCH_GPIO14 2 9 USB_OC#12_13
USB_OC#6_7 3 8 USB_OC#8_9
2 1 PCI_GNT3# USB_OC#0_1 4 7 USB_OC#10_11
DY 3D3V_S5 5 6 USB_OC#4_5
A R1801 <Core Design> A
4K7R2J-2-GP
X02_0611
RN1801
SRN8K2J-2-GP-U Wistron Corporation
A16 Swap Override jumper 1 2 PCI_PLTRST# PCH_GPIO52 1 10 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
5,27,31,65,66,71,83 PLT_RST# 3D3V_S0
R1823 INT_PIRQB# 2 9 INT_PIRQD# Taipei Hsien 221, Taiwan, R.O.C.
1

0R0402-PAD-2-GP SATA_ODD_DA# 3 8
1

PCI_GNT#3 Low = A16 swap override/Top-Block R1816 INT_PIRQA# 4 7 INT_PIRQC# Title

100KR2J-1-GP C1801 6 BLUETOOTH_EN
Swap Override enabled
High = Default
DY DY SCD1U16V2ZY-2GP
3D3V_S0 5
PCH (PCI/USB/NVRAM)
2

X01_0417 Size Document Number Rev

2

A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 18 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

PCH1C 3 OF 10
4 DMI_RXN[3:0] FDI_TXN[7:0] 4
DMI_RXN0 BC24 BJ14 FDI_TXN0
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DMI_RXN1
DMI_RXN2
BE20
BG18
DMI0RXN
DMI1RXN
DMI2RXN
FDI_RXN0
FDI_RXN1
FDI_RXN2
AY14
BE14
FDI_TXN1
FDI_TXN2
DMI_RXN3 BG20 BH13 FDI_TXN3
DMI3RXN FDI_RXN3 FDI_TXN4
D 4 DMI_RXP[3:0] FDI_RXN4 BC12 D
DMI_RXP0 BE24 BJ12 FDI_TXN5
DMI_RXP1 DMI0RXP FDI_RXN5 FDI_TXN6
BC20 DMI1RXP FDI_RXN6 BG10
DMI_RXP2 BJ18 BG9 FDI_TXN7
DMI_RXP3 DMI2RXP FDI_RXN7
BJ20 DMI3RXP FDI_TXP[7:0] 4
BG14 FDI_TXP0
4 DMI_TXN[3:0] DMI_TXN0 FDI_RXP0 FDI_TXP1
AW24 DMI0TXN FDI_RXP1 BB14
DMI_TXN1 AW20 BF14 FDI_TXP2
DMI_TXN2 DMI1TXN FDI_RXP2 FDI_TXP3
BB18 DMI2TXN FDI_RXP3 BG13
DMI_TXN3 AV18 BE12 FDI_TXP4
DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_TXP5
4 DMI_TXP[3:0] DMI_TXP0 FDI_RXP5 FDI_TXP6
AY24 DMI0TXP FDI_RXP6 BJ10
DMI_TXP1 AY20 BH9 FDI_TXP7
DMI_TXP2 DMI1TXP FDI_RXP7
AY18
Layout Note: DMI_TXP3 AU18
DMI2TXP
DMI3TXP
DMI_ZCOMP keep W=4 mils and FDI_INT AW16 FDI_INT FDI_INT 4 DSWODVREN - On Die DSW VR Enable
routing length less than 500 VCCP_CPU
BJ24 AV12 FDI_FSYNC0 FDI_FSYNC0 4 HIGH Enabled (DEFAULT)
mils. DMI_ZCOMP FDI_FSYNC0
DMI_IRCOMP keep W=4 mils and R1901 1 2 49D9R2F-GP DMI_COMP_R BG25 BC10 FDI_FSYNC1 FDI_FSYNC1 4
DMI_IRCOMP FDI_FSYNC1 LOW Disabled
routing length less than 500
mils. R1902 1 2 750R2F-GP RBIAS_CPY BH21 AV14 FDI_LSYNC0 FDI_LSYNC0 4
DMI2RBIAS FDI_LSYNC0
BB10 FDI_LSYNC1 FDI_LSYNC1 4
FDI_LSYNC1 RTC_AUX_S5

A18 DSW ODVREN RTC_AUX_S5 DSW ODVREN R1917 1 2 330KR2J-L1-GP

DSWVRMEN
C R1911 1 2 10KR2J-3-GP C
DY

System Power Management

3D3V_S0 TPAD14-OP-GP TP1907 1 SUSACK# C12 E22 PCH_DPW ROK R1927 1 2 PM_RSMRST#
SUSACK# DPWROK 0R0402-PAD-2-GP
R1905 1 2 10KR2J-3-GP X02_0611
K3 B9 PCH_W AKE# R1910 1 2 10KR2J-3-GP 3D3V_S0
5 XDP_DBRESET#
EC1902 SC33P50V2JN-3GP SYS_RESET# WAKE# DY PCH_W AKE#_EC 27
2 1 X02_0611
36 SYS_PW ROK
DY P12 N3 PM_CLKRUN# R1929 1 2 PM_CLKRUN#_EC 27 PM_CLKRUN# R1919 1 2 8K2R2J-3-GP
SYS_PWROK CLKRUN#/GPIO32 0R0402-PAD-2-GP
X02_0611 X02_0611
27,36 S0_PW R_GOOD 1 2 PW ROK L22 G8 PM_SUS_STAT# 1 TP1901 TPAD14-OP-GP
R1921 PWROK SUS_STAT#/GPIO61
1 2 0R0402-PAD-2-GP
0R0402-PAD-2-GP R1916 X02_0611
1 2 MEPW ROK L10 N14 SUS_CLK R1925 1 2 PCH_SUSCLK_KBC
45,46,47,93 RUNPW ROK
R1907 DY 0R2J-2-GP APWROK SUSCLK/GPIO62 0R0402-PAD-2-GP
PCH_SUSCLK_KBC 27

2
37 PM_DRAM_PW RGD B13 D10 PM_SLP_S5# 1 TP1902 TPAD14-OP-GP
DRAMPWROK SLP_S5#/GPIO63 EC1901
X02_0611 SC4D7P50V2CN-1GP DY

1
27 RSMRST#_KBC R1924 1 2 PM_RSMRST# C21 H4 PM_SLP_S4# PM_SLP_S4# 27,46
0R0402-PAD-2-GP RSMRST# SLP_S4#

SUS_PW R_ACK K16 F4 PM_SLP_S3# PM_SLP_S3# 27,36,37,47

SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3#

27 PM_PW RBTN# PM_PW RBTN# E20 G10 PM_SLP_A# 1 TP1903 TPAD14-OP-GP

PWRBTN# SLP_A#

27 AC_PRESENT AC_PRESENT H20 G16 PM_SLP_SUS# 1 TP1904 TPAD14-OP-GP

B ACPRESENT/GPIO31 SLP_SUS# B

BATLOW # E10 AP14 H_PM_SYNC H_PM_SYNC 5

BATLOW#/GPIO72 PMSYNCH

PM_RI# A10 K14 PM_SLP_LAN# 1 TP1905 TPAD14-OP-GP

RI# SLP_LAN#/GPIO29

PANTHER-GP-NF
Sequence: 71.PANTH.00U
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

3D3V_S5

RN1901
8 1 BATLOW #
7 2 PM_RI#
6 3 SUS_PW R_ACK
5 4 PCH_W AKE#

SRN10KJ-6-GP

R1909 1 2 100KR2J-1-GP AC_PRESENT

R1920 2 1 10KR2J-3-GPPM_SLP_LAN#
DY
A <Core Design> A

R1908 2 1 10KR2J-3-GP PM_RSMRST# Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R1926 1 2 100KR2J-1-GP SYS_PW ROK
R1904 1
DY 2 100KR2J-1-GP PW ROK Title

PCH (DM I/FDI/PM)

Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 19 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PCH S5 power rail CLKREQ#:

3D3V_S0
RN2018
3D3V_S5

1 4 PCIE_CLK_REQ2# PCIE_CLK_RQ2# S0 power rail CLKREQ#: SMB_CLK 4 1 RN2003

PCIECLKRQ[0]# 2 3 CLK_PCIE_REQ1# PCIE_CLK_RQ1# 3D3V_S5 SMB_DATA 3 2 SRN2K2J-1-GP
3D3V_S5
PCIECLKRQ[7:3]# PCIECLKRQ[2:1]#

1
RN2001 SRN10KJ-5-GP
1 8 PCIE_CLK_REQ6# R2004 SML0_DATA 1 8 RN2004
2 7 CLK_PCIE_W LAN_REQ# PCIE_CLK_RQ3# PCH1B 2 OF 10 UMA 10KR2J-3-GP SML0_CLK 2 7 SRN2K2J-2-GP
3 6 PCIE_CLK_REQ0# PCIE_CLK_RQ0# 10P 4R SML1_CLK 3 6
4 5 PCIE_CLK_REQ4# PCIE_CLK_RQ4# BG34 SML1_DATA 4 5
Vinafix.com

2
PERN1 EC_SW I# PEG_CLKREQ#_R
BJ34 PERP1 SMBALERT#/GPIO11 E12 EC_SW I# 27
SRN10KJ-6-GP AV32 PETN1 NC

1
RN2002 AU32 H14 SMB_CLK PCIE_CLK_RQ6#
EC_SW I# PETP1 SMBCLK R2005 PCH_GPIO74 R2011 1 10KR2J-3-GP
D 1 8 2 D
2 7 PCIE_CLK_LAN_REQ# PCIE_CLK_RQ5# BE34 C9 SMB_DATA 10KR2J-3-GP
3 6 CLK_PCIE_REQ7# PCIE_CLK_RQ7# BF34
PERN2 SMBDATA DY DRAMRST_CNTRL_PCH 1 2
CLK_PEG_B_REQ# PERP2 R2009 1KR2J-1-GP
4 5 BB32 NC

2
PETN2
AY32 PETP2

SMBUS
SRN10KJ-6-GP A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 37
SML0ALERT#/GPIO60 3D3V_S0
BG36 PERN3
BJ36 C8 SML0_CLK RN2007
PERP3 SML0CLK
AV34 NC 2 3
AU34
PETN3
G12 SML0_DATA 1 4
CRB : 1K
PETP3 SML0DATA Layout Note:
65 PCIE_RXN4 BF36 Can Place Far away PCH SRN2K2J-1-GP CEKLT: 10K
PERN4
65 PCIE_RXP4 BE36 PERP4
C2005 1 2 SCD1U16V2KX-3GP PCIE_TXN4_C AY34 C13 PCH_GPIO74
65 PCIE_TXN4
C2006 1 2 SCD1U16V2KX-3GP PCIE_TXP4_C BB34
PETN4 WLAN SML1ALERT#/PCHHOT#/GPIO74
X02_0615
65 PCIE_TXP4 PETP4
E14 SML1_CLK
SML1CLK/GPIO58 SML1_CLK 27,28,86 Q2001

PCI-E*
BG37 PERN5
BH37 M16 SML1_DATA SMB_DATA 6 D S 1
PERP5 SML1DATA/GPIO75 SML1_DATA 27,28,86 PCH_SMBDATA 14,15,65,66,69
X02_0615 AY36 PETN5 NC
BB36 PETP5 5 G G 2

BJ38 4 S D 3
31 PCIE_RXN6 PERN6
31 PCIE_RXP6 BG38 PERP6
C2001 2 SCD1U16V2KX-3GP PCIE_TXN6_C CL_CLK TP2001 TPAD14-OP-GP

Controller
31 PCIE_TXN6 1 AU36 PETN6 LAN CL_CLK1 M7 1 2N7002BKS-GP-U
31 PCIE_TXP6 C2002 1 2 SCD1U16V2KX-3GP PCIE_TXP6_C AV36 PETP6 84.2N702.E3F PCH_SMBCLK 14,15,65,66,69

Link
BG40 T11 CL_DATA 1 TP2002 TPAD14-OP-GP
PERN7 CL_DATA1 SMB_CLK
BJ40 PERP7 NC
Layout Note: X02_0615 AY40 PETN7
C BB40 P10 CL_RST# 1 TP2003 TPAD14-OP-GP C
PETP7 CL_RST1# XTAL25_IN
Layout trace < 14000mil 1 2
BE38 X2001
BC38
PERN8 Layout Note: C2008
AW38
PERP8 NC CLKOUT termination 1 4 SC15P50V2JN-2-GP
PETN8

2
AY38 PETP8 A00_0803 place close to PCH <500mil
R2003 R2006
M10 PEG_CLKREQ#_R 1 2 PEG_CLKREQ# 83 1M1R2J-GP
PEG_A_CLKRQ#/GPIO47 0R0402-PAD-2-GP C2007
Y40 CLKOUT_PCIE0N 2 3
Y39 RN2016 SC15P50V2JN-2-GP
NC

1
CLKOUT_PCIE0P CLKOUT_PEG_A_N
CLKOUT_PEG_A_N AB37 1 4 CLK_PCIE_VGA# 83
PCIE_CLK_REQ0# CLKOUT_PEG_A_P XTAL25_OUT XTAL-25MHZ-155-GP

CLOCKS
J2 AB38 2 3 1 2
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P SG CLK_PCIE_VGA 83
SRN0J-6-GP 82.30020.D41
AB49 AV22 CLKOUT_DMI_N 0R0402-PAD-2-GP 2 1 R2016 CLK_EXP_N 5 2nd = 82.30020.G71
CLKOUT_PCIE1N CLKOUT_DMI_N CLKOUT_DMI_P 0R0402-PAD-2-GP 2
AB47 CLKOUT_PCIE1P NC CLKOUT_DMI_P AU22 1 R2017 CLK_EXP_P 5 3rd = 82.30020.G61
Layout Note: CLK_PCIE_REQ1# M1 PCIECLKRQ1#/GPIO18
CLKOUT termination CLKOUT_DP_N AM12 X02_0611
place close to PCH <500mil CLKOUT_DP_P AM13
AA48 3D3V_S0 3D3V_S0
CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P NC
X02_0613 BF18 CLK_BUF_EXP_N 2 3
CLKIN_DMI_N

1
PCIE_CLK_REQ2# V10 BE18 CLK_BUF_EXP_P RN2019 1 4
PCIECLKRQ2#/GPIO20 CLKIN_DMI_P
RN

SRN10KJ-5-GP R2015
RN2012 R2013 10KR2J-3-GP
1 4 CLK_PCH_SRC3_N Y37 BJ30 CLK_BUF_CPYCLK_N 2 3 10KR2J-3-GP SG
65 CLK_PCIE_W LAN#
2 3 CLK_PCH_SRC3_P Y36 CLKOUT_PCIE3N WLAN CLK CLKIN_GND1_N
BG30 CLK_BUF_CPYCLK_P RN2008 1 4
65 CLK_PCIE_W LAN

2
0R4P2R-PAD CLKOUT_PCIE3P CLKIN_GND1_P SRN10KJ-5-GP
B BOARD_ID1 B
65 CLK_PCIE_W LAN_REQ# A8 PCIECLKRQ3#/GPIO25
G24 CLK_BUF_DOT96_N 2 3 22 BOARD_ID2 BOARD_ID2
CLKIN_DOT_96N CLK_BUF_DOT96_P RN2020 1
CLKIN_DOT_96P E24 4

1
Y43 SRN10KJ-5-GP
CLKOUT_PCIE4N R2010
Y45 NC
X02_0613 CLKOUT_PCIE4P
AK7 CLK_BUF_CKSSCD_N 2 3
UMA 10KR2J-3-GP
PCIE_CLK_REQ4# CLKIN_SATA_N CLK_BUF_CKSSCD_P RN2021 1
L12 PCIECLKRQ4#/GPIO26 CLKIN_SATA_P AK5 4
RN

SRN10KJ-5-GP

2
RN2014
1 4 CLK_PCH_SRC5_N V45 K45 CLK_BUF_REF14 R2008 1 2
31 CLK_PCIE_LAN#
2 3 CLK_PCH_SRC5_P V46
CLKOUT_PCIE5N LAN REFCLK14IN 10KR2J-3-GP
31 CLK_PCIE_LAN CLKOUT_PCIE5P
0R4P2R-PAD CLK CLK_PCI_FB BIOS UMA/DIS Strap pin
31 PCIE_CLK_LAN_REQ# L14 PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK H45 CLK_PCI_FB 18

AB42 CLKOUT_PEG_B_N XTAL25_IN V47 XTAL25_IN BOARD_ID1 BOARD_ID2

AB40 V49 XTAL25_OUT
CLKOUT_PEG_B_P NC XTAL25_OUT
CLK_PEG_B_REQ# E6 PX(AMD) 0 0
Layout Note: PEG_B_CLKRQ#/GPIO56 R2007
Layout trace < 14000mil XCLK_RCOMP Y47 XCLK_RCOMP 1 2 +VCCDIFFCLKN
V40 DIS 0 1
CLKOUT_PCIE6N 90D9R2F-1-GP
V42 CLKOUT_PCIE6P NC
PCIE_CLK_REQ6# T13 PCIECLKRQ6#/GPIO45
UMA 1 0
V38 K43 JTAG_TCK 1 TP2009 TPAD14-OP-GP
FLEX CLOCKS

CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 Optimus(NV) 1 1

V37 CLKOUT_PCIE7P NC
A F47 PCH_GPIO65 1 TP2005 TPAD14-OP-GP <Core Design> A
CLK_PCIE_REQ7# CLKOUTFLEX1/GPIO65
K12 PCIECLKRQ7#/GPIO46
H47 PCH_GPIO66 1 TP2006 TPAD14-OP-GP
TPAD14-OP-GP TP2007 PCIE_CLK_XDP_N_R CLKOUTFLEX2/GPIO66
TPAD14-OP-GP TP2008
1
1 PCIE_CLK_XDP_P_R
AK14
AK13
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49 BOARD_ID1 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
PANTHER-GP-NF
Title
71.PANTH.00U
PCH (PCI-E/SMBUS/CLOCK/CL)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 20 of 106
5 4 3 2 1
 5 4 3 2 1

Layout Note:
SSID = PCH Layout Note: Place near PCH
RTC_AUX_S5 Place it at the open door location. A00_0803
RN2102 RN2101
1 4 RN
2 3 Integrated SUS 1V VRM Enable LPC_LAD2_PCH 1 8 LPC_AD2

2
LPC_LAD3_PCH 2 7 LPC_AD3

1
SRN20KJ-1-GP C2104 G2101 Low = External VRs LPC_LAD1_PCH 3 6 LPC_AD1
Vinafix.com INTVRMEN LPC_LAD0_PCH 4 5 LPC_AD0

SC1U6D3V2KX-GP
GAP-OPEN
High = Internal VRs* 0R8P4R-PAD-1-GP

1
D 27 RTCRST_ON D
PCH1A 1 OF 10 LPC_AD[3..0]
LPC_AD[3..0] 27,71
X02_0615
RTC_X1 A20 C38 LPC_LAD0_PCH LPC_AD0

G
Q2102 RTCX1 FWH0/LAD0 LPC_LAD1_PCH LPC_AD1
FWH1/LAD1 A38

LPC
RTC_X2 C20 B37 LPC_LAD2_PCH X02_0611 LPC_AD2
RTCX2 FWH2/LAD2 LPC_LAD3_PCH LPC_AD3
FWH3/LAD3 C37
S D RTC_RST# D20 R2136
RTCRST#
1

FWH4/LFRAME# D36 LPC_LFRAME#_PCH 1 2 LPC_FRAME# 27,71

R2122 SRTC_RST# G22 0R0402-PAD-2-GP
2N7002BK-GP R2104 SRTCRST#
10KR2J-3-GP LDRQ0# E36

RTC
84.07002.I31 C2103 2 1 SM_INTRUDER# K22 K36 KB_DET# 69
SC1U6D3V2KX-GP 1M1R2J-GP INTRUDER# LDRQ1#/GPIO23
2

RTC_AUX_S5 1 2 PCH_INTVRMEN C17 V5 INT_SERIRQ 27

2
INTVRMEN SERIRQ
R2105
330KR2F-L-GP AM3 SATA_RXN0 56
HDA_BITCLK SATA0RXN
N34 AM1
HDA_BCLK SATA0RXP SATA_RXP0 56
HDD1

SATA 6G
SATA0TXN AP7 SATA_TXN0 56
HDA_SYNC L34 AP5 SATA_TXP0 56
HDA_SYNC SATA0TXP

29 HDA_SPKR T10 SPKR SATA1RXN AM10 SATA_RXN1 66

AM8

R2123 Layout Note: HDA_RST# K34 HDA_RST#

SATA1RXP
SATA1TXN AP11
SATA_RXP1
SATA_TXN1
66
66 mSATA
SATA1TXP AP10 SATA_TXP1 66
33R2J-2-GP Place close together.
2 1 HDA_SDOUT For RNxxxx later. 29 HDA_SDIN0 E34 AD7
29 HDA_CODEC_SDOUT HDA_SDIN0 SATA2RXN
SATA2RXP AD5
R2125 G34 AH5
C 33R2J-2-GP Layout Note: HDA_SDIN1 SATA2TXN
AH4 C
HDA_RST# SATA2TXP
29 HDA_CODEC_RST# 2 1 HDA_SDO and HDA_BCLK must be C34 HDA_SDIN2

IHDA
length matched to within 500 mils SATA3RXN AB8
R2126 A34 AB10
33R2J-2-GP HDA_SDIN3 SATA3RXP
SATA3TXN AF3
2 1 HDA_BITCLK R2107 AF1
29 HDA_CODEC_BITCLK 1KR2J-1-GP HDA_SDOUT SATA3TXP
A36 HDA_SDO

SATA
27 ME_UNLOCK 1 2 SATA4RXN Y7 SATA_RXN4 56
SATA4RXP Y5 SATA_RXP4 56
TPAD14-OP-GP TP2105 1PCH_GPIO33 C36 AD3

3D3V_S5 TPAD14-OP-GP TP2106

HDA_DOCK_EN#/GPIO33 SATA4TXN
SATA4TXP AD1
SATA_TXN4
SATA_TXP4
56
56 ODD
Flash Descriptor Security Overide/ 1PCH_GPIO13 N32 HDA_DOCK_RST#/GPIO13
Y3
Intel ME Debug Mode SATA5RXN
Y1
Layout Note:
SATA5RXP
Low = Default * SATA5TXN AB3 HDD < 6000mil, mSATA < 6000mil, ODD < 12500mil
HDA_SDOUT R2111 1 2 51R2J-2-GP PCH_JTAG_TCK_BUF J3 AB1
High = Enable DY JTAG_TCK SATA5TXP
Layout Note: R2118 1 2 210R2F-L-GP PCH_JTAG_TMS H7 Y11 VCCP_CPU
DY JTAG_TMS SATAICOMPO

JTAG
Place at the separated point
R2119 1 2 210R2F-L-GP PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2 37D4R2F-GP
DY JTAG_TDI SATAICOMPI
R2120 1 2 210R2F-L-GP PCH_JTAG_TDO H1 VCCP_CPU
DY JTAG_TDO
AB12
3D3V_S0 SATA3RCOMPO
AB13 SATA3_COMP R2113 1 2 49D9R2F-GP
SATA3COMPI
R2106 1 2 1KR2J-1-GP HDA_SPKR
DY 27,60 SPI_CLK_R 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP
R2108 33R2J-2-GP SPI_CLK SATA3RBIAS
B B
No Reboot Strap 27,60 SPI_CS0#_R 1 2 PCH_SPI_CS0# Y14 SPI_CS0#
R2109 33R2J-2-GP
Low = Default * T1 SPI_CS1# Layout Note:

SPI
HDA_SPKR High = No Reboot P3 SATA_LED# SATA_LED# 68
SATALED#
Place close PCH(<500mil)
27,60 SPI_SI_R 1 2 PCH_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14 PCH_GPIO21
R2110 33R2J-2-GP
+3VS_+1.5VS_HDA_IO 1 2 PCH_SPI_SO U3 P1 BBS_BIT0
27,60 SPI_SO_R SPI_MISO SATA1GP/GPIO19 BBS_BIT0 18
R2115 33R2J-2-GP
R2103 1 2 1KR2J-1-GP HDA_SYNC
PANTHER-GP-NF
71.PANTH.00U 3D3V_S0
PLL ODVR VOLTAGE
36,37 RUN_ENABLE RN2103
Low = 1.8V INT_SERIRQ 1 4
HDA_SYNC High = 1.5V PCH_GPIO21 2 3
* X02_0615
G

Q2101 SRN10KJ-5-GP

R2124
29 HDA_CODEC_SYNC 2 1 HDA_CODEC_SYNC_R S D HDA_SYNC
2

33R2J-2-GP RTC_X1
R2117 2N7002BK-GP
1M1R2J-GP 84.07002.I31 1 2 RTC_X2
R2101 10MR2J-L-GP
1

X2101
A HDA_CODEC_BITCLK HDA_CODEC_SDOUT <Core Design> A

HDA_SYNC: 1 4
2

This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V
DY EC2102
DY EC2103 Wistron Corporation
SC15P50V2JN-2-GP
1

1
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
C2101

VccVRM supply mode. 1K external pull-up resistor is required on this

1

1
SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

2 3 C2102 Taipei Hsien 221, Taiwan, R.O.C.

signal on the board. Signal may have leakage paths via powered off devices (Audio SC15P50V2JN-2-GP
2

2
Codec) and hence contend with the external pull-up. A blocking FET is Title

recommended in such a case to isolate HDA_SYNC from the Audio Codec device X-32D768KHZ-65-GP PCH (SPI/RTC/LPC/SATA/IHDA)
until after the Strap sampling is complete. 82.30001.A41 Size Document Number Rev
A3 A00
2nd = 82.30001.841 BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 21 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PCH
PCH1F 6 OF 10

PCH_GPIO00 T7 C40 SATA_ODD_PW RGT SATA_ODD_PW RGT 56

BMBUSY#/GPIO0 TACH4/GPIO68

Vinafix.com 27 EC_SMI# EC_SMI# A42 TACH1/GPIO1 TACH5/GPIO69 B41 BOARD_ID2 BOARD_ID2 20

PCH_GPIO06 H36 C41 PCH_GPIO70 1 TP2204 TPAD14-OP-GP
3D3V_S0 TACH2/GPIO6 TACH6/GPIO70
D D
RN2203 27 EC_SCI# EC_SCI# E38 A40 PCH_GPIO71 1 TP2205 TPAD14-OP-GP
SRN10KJ-5-GP TACH3/GPIO7 TACH7/GPIO71
1 4 H_A20GATE_PCH PCH_GPIO08 C10
H_RCIN# GPIO8
2 3 X02_0611
60 RTC_DET# RTC_DET# C4 LAN_PHY_PWR_CTRL/GPIO12 R2205
PCH_GPIO15 G2 P4 H_A20GATE_PCH 1 2 H_A20GATE 27
3D3V_S0 GPIO15 A20GATE 0R0402-PAD-2-GP
AU16 H_PECI_R R2203 1 2 0R2J-2-GP
RN2205 56 SATA_ODD_PRSNT# SATA_ODD_PRSNT# U2
PECI DY H_PECI 5,27 VCCP_CPU
SRN10KJ-5-GP SATA4GP/GPIO16 H_RCIN#
RCIN# P5 H_RCIN# 27
1 4 SATA_ODD_PRSNT#

GPIO
2 3 PCH_GPIO00 27,92,93 DGPU_PW ROK DGPU_PW ROK D40 AY11 H_CPUPW RGD H_CPUPW RGD 5 R2202 1 2 2K2R2J-2-GP
TACH0/GPIO17 PROCPWRGD

CPU/MISC
49 DBC_EN DBC_EN T5 AY10 PCH_THERMTRIP_R R2204 1 2 390R2J-1-GP H_THERMTRIP# 5
SCLOCK/GPIO22 THRMTRIP#

49 COLOR_ENGINE COLOR_ENGINE E8 T14 INIT3_3V# 1 TP2201 TPAD14-OP-GP

3D3V_S0 GPIO24 INIT3_3V#
RN2206 TPAD14-OP-GP TP2203 1 PCH_GPIO27 E16 AY1 DF_TVS 1D8V_S0
SRN10KJ-6-GP GPIO27 DF_TVS
1 8 PCH_GPIO49 PLL_ODVR_EN P8 GPIO28

1
2 7 MSATA_DET# AH8
PCH_GPIO38 MSATA_DET# TS_VSS1 R2207
3 6 66 MSATA_DET# K1 STP_PCI#/GPIO34
4 5 DBC_EN AK11 2K2R2J-2-GP
TPAD14-OP-GP TP2206 PCH_GPIO35 TS_VSS2
1 K4 GPIO35
AH10 R2209

2
PCH_GPIO36 TS_VSS3
V8 SATA2GP/GPIO36
3D3V_S0 AK10 DF_TVS 1 2
TS_VSS4 H_SNB_IVB# 5
C RN2201 PCH_GPIO37 M5 1KR2J-1-GP C
SRN10KJ-6-GP SATA3GP/GPIO37 Layout Note:
1 8 EC_SMI# PCH_GPIO38 N2 P37 Check these fuor balls are connected firstly, then to GND
EC_SCI# SLOAD/GPIO38 NC_1
2 7
3 6 PCH_GPIO06 83 DGPU_HOLD_RST# DGPU_HOLD_RST# M3
DGPU_PW ROK SDATAOUT0/GPIO39
4 5
93 DGPU_PW R_EN# DGPU_PW R_EN# V13 BG2 PCH_NCTF_BG2 1 TP2217 TPAD14-OP-GP
SDATAOUT1/GPIO48 VSS_NCTF_15#BG2
PCH_GPIO49 V3 BG48 PCH_NCTF_BG48 1 TP2214 TPAD14-OP-GP
SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16#BG48
PCH_GPIO57 D6 BH3 PCH_NCTF_BH3 1 TP2218 TPAD14-OP-GP
GPIO57 VSS_NCTF_17#BH3
BH47 PCH_NCTF_BH47 1 TP2213 TPAD14-OP-GP
3D3V_S5 VSS_NCTF_18#BH47
A4 VSS_NCTF_1#A4 VSS_NCTF_19#BJ4 BJ4

NCTF
RN2204 A44 BJ44
SRN10KJ-5-GP VSS_NCTF_2#A44 VSS_NCTF_20#BJ44
1 4 RTC_DET# A45 BJ45
PCH_GPIO57 VSS_NCTF_3#A45 VSS_NCTF_21#BJ45
2 3
A46 VSS_NCTF_4#A46 VSS_NCTF_22#BJ46 BJ46

2 1 COLOR_ENGINE A5 BJ5
R2221 DY 10KR2J-3-GP VSS_NCTF_5#A5 VSS_NCTF_23#BJ5
A6 VSS_NCTF_6#A6 VSS_NCTF_24#BJ6 BJ6

A4,A44,A45,A46,A5,A6,B3,B47,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
2 1 PCH_GPIO08

BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
R2224 DY 10KR2J-3-GP TPAD14-OP-GP TP2220 1 PCH_NCTF_B3 B3 C2 PCH_NCTF_C2 1 TP2219 TPAD14-OP-GP
PCH_GPIO15 VSS_NCTF_7#B3 VSS_NCTF_25#C2
2 1
R2201 DY 1KR2J-1-GP TPAD14-OP-GP TP2216 1 PCH_NCTF_B47 B47 C48 PCH_NCTF_C48 1 TP2215 TPAD14-OP-GP
B VSS_NCTF_8#B47 VSS_NCTF_26#C48 B

D49,E1,E49,F1,F49
RN2202 BD1 D1
SRN10KJ-5-GP VSS_NCTF_9#BD1 VSS_NCTF_27#D1

NCTF TEST PIN:

1 4 PCH_GPIO36 BD49 D49
PCH_GPIO37 VSS_NCTF_10#BD49 VSS_NCTF_28#D49
2 3
BE1 VSS_NCTF_11#BE1 VSS_NCTF_29#E1 E1

BE49 VSS_NCTF_12#BE49 VSS_NCTF_30#E49 E49

BF1 VSS_NCTF_13#BF1 VSS_NCTF_31#F1 F1

3D3V_S0
BF49 VSS_NCTF_14#BF49 VSS_NCTF_32#F49 F49

R2225 2 1 DGPU_PW R_EN#

DY 10KR2J-3-GP PANTHER-GP-NF
R2226 2 1 DGPU_HOLD_RST# 71.PANTH.00U
DY 10KR2J-3-GP
R2227 2 1 DGPU_PW R_EN#
10KR2J-3-GP
R2228 2 1 DGPU_HOLD_RST#
10KR2J-3-GP

2 1 PLL_ODVR_EN
R2212 DY 1KR2J-1-GP

A <Core Design> A

PLL ON DIE VR ENABLE

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Weakly internal pull up 20k. Taipei Hsien 221, Taiwan, R.O.C.
GPIO28 High - Enable
(PLL_ODVR_EN) Title
LOW - Disable
PCH (GPIO/CPU)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 22 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PCH Voltage Rail Voltage(V) Iccmax(A)

V_PROC_IO 1.05 0.001
V5REF 5 0.001
NO CRT , these CAPs might be remove. V5REF_Sus 5 0.001
PCH1G POWER 7 OF 10 3D3V_S0
VCCP_CPU
Vinafix.com X02_0615 X02_0704 Vcc3_3 3.3 0.228

SCD01U50V2KX-1GP
1.7A 0.001A
AA23 U48 VccADAC 3.3 0.063

SC10U6D3V3MX-GP
VCCCORE1 VCCADAC
D AC23 VCCCORE2 D

1
SCD1U16V2KX-3GP
C2301

C2302

C2303

C2304

C2315
AD21 C2313 C2314 VccADPLLA 1.05 0.08

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP

CRT
VCCCORE3

1
AD23 VCCCORE4 VSSADAC U47
DY X02_0611 VccADPLLB 1.05 0.08
AF21

2
VCC CORE
VCCCORE5
AF23
2

2
VCCCORE6 3D3V_S0 VccCore 1.05 1.7
AG21 VCCCORE7 R2304
AG23 VCCCORE8 0.001A
AG24 AK36 +3VS_VCCA_LVDS 1 2 VccDMI 1.1 0.047
VCCCORE9 VCCALVDS
AG26 VCCCORE10
AG27 VCCCORE11 VSSALVDS AK37 0R0603-PAD-2-GP VccIO 1.05 3.711
AG29 VCCCORE12
AJ23 VCCCORE13
VccASW 1.05 0.903
1D8V_S0

LVDS
AJ26 VCCCORE14 VCCTX_LVDS1 AM37 R2301
AJ27 VCCCORE15 0.04A VccSPI 3.3 0.01
AJ29 AM38 +1.8VS_VCCTX_LVDS 1 2

SC22U6D3V5MX-2GP
SCD01U50V2KX-1GP
VCCCORE16 VCCTX_LVDS2
AJ31 VCCCORE17
VccDSW3_3 3.3 0.001
VCCP_CPU

C2318
AP36 0R0603-PAD-2-GP
VCCTX_LVDS3

1
C2316
SCD01U50V2KX-1GP

C2317
VccDFTERM 1.8 0.002
VCCTX_LVDS4 AP37
AN19 VccRTC 3.3 6uA

2
VCCIO28
VccSus3_3 3.3 0.095
TPAD14-OP-GP TP2303 1 VCCAPLLEXP BJ22 X02_0615 3D3V_S0
VCCAPLLEXP
X02_0615 VccSusHDA 3.3 0.01
VCC3_3_6 V33

HVCMOS
AN16 VCCIO15
VccVRM 1.5 0.167

1
AN17 VCCIO16
C2319 VccClkDMI 1.05 0.07
V34 SCD1U16V2KX-3GP X02_0611

2
VCC3_3_7
C VccSSC 1.05 0.095 C
AN21 VCCIO17 X02_0615
VccDIFFCLKN 1.05 0.055
VCCP_CPU AN26 VCCVRM 1D5V_S0
VCCIO18 R2307
3.711A 0.167A VccALVDS 3.3 0.001
AN27 VCCIO19 VCCVRM3 AT16 1 2
0R0402-PAD-2-GP VccTX_LVDS 1.8 0.04
1D05VS_VCC_DMI VCCP_CPU
C2305

C2306

C2307

C2308

C2309

AP21
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
SC10U6D3V5KX-1GP

VCCIO20 R2306
1

0.047A
AP23 VCCIO21 VCCDMI1 AT20 1 2 Refer to chipset EDS V.0.7
0R0402-PAD-2-GP
2

1
DMI
AP24 VCCIO22

VCCIO
C2320
AP26 AB36 SC1U6D3V2KX-GP

2
VCCIO23 VCCCLKDMI
AT24 VCCIO24 VCCP_CPU
R2308
+1.05VS_VCC_DMI_CCI
0.07A
X02_0615 AN33 VCCIO25 1 2
0R0402-PAD-2-GP

1
AN34 VCCIO26 VCCDFTERM1 AG16
3D3V_S0 C2321
0.228A SC1U6D3V2KX-GP

2
BH29 VCC3_3_3 VCCDFTERM2 AG17
C2310

DFT / SPI
SCD1U16V2KX-3GP
1

VCCVRM AJ16
VCCDFTERM3 1D8V_S0
2

B
AP16 VCCVRM2 0.002A B
VCCDFTERM4 AJ17

1
TPAD14-OP-GP TP2302 1VCCFDIPLL BG6 VCCAFDIPLL C2322
X02_0615 VCCP_CPU SCD1U16V2KX-3GP

2
AP17 VCCIO27
V1 X02_0615
FDI

1D05VS_VCC_DMI VCCSPI 3D3V_S5

AU20 VCCDMI2 0.01A

PANTHER-GP-NF 1
71.PANTH.00U C2323
SC1U6D3V2KX-GP
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (POWER1)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 23 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PCH
PCH1J POWER 10 OF 10 VCCP_CPU

TP2401 1 VCCACLK AD49 N26

3D3V_S5 TPAD14-OP-GP VCCACLK VCCIO29
0.001A

1
VCCIO30 P26
DG: none 3D3V_S5 T16 C2438
VCCDSW3_3 SC1U6D3V2KX-GP
P28
CRB: 10uH
Vinafix.com

2
VCCIO31
X02_0615

1
3D3V_S0 C2416 TP2405 DCPSUSBYP
0.228A SCD1U16V2KX-3GP TPAD14-OP-GP
1 V12 DCPSUSBYP VCCIO32 T27
3D3V_S5 5V_S5
L2401
D T29 D

2
+V3.3S_VCC_CLKF33 +V3.3S_VCC_CLKF33 VCCIO33 3D3V_S5
1 2 T38 VCC3_3_5

2
0.095A

1
IND-10UH-238-GP VCCP_CPU T23 D2401
TP2403 +VCCAPLL_CPY_PCH VCCSUS3_3_7
68.1001E.10N DY 1 BH23 VCCAPLLDMI2 83.R0304.A8F CH751H-40PT-GP

1
2nd = 68.10050.10Y C2401 C2402 TPAD14-OP-GP T24 C2424 2nd = 83.R3004.A8F

2
SC10U6D3V5KX-1GP SC1U10V2KX-1GP VCCSUS3_3_8 SCD1U16V2KX-3GP R2408
AL29

1
VCCIO14
V23 X02_0615 1 2

2
VCCSUS3_3_9

USB
TPAD14-OP-GP TP2402 1 +VCCSUS1 AL24 V24 3D3V_S5 10R2J-2-GP
DCPSUS3 VCCSUS3_3_10

1
C2426
P24 SCD1U16V2KX-3GP
VCCSUS3_3_6
(0.1uFx1)

2
1
VCCP_CPU AA19 C2425 X02_0615
VCCASW1 SCD1U16V2KX-3GP
0.903A VCCIO34 T26 VCCP_CPU
AA21 X02_0615

2
VCCASW2
0.001A

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C2406
SC1U6D3V2KX-GP

C2405
SC1U6D3V2KX-GP

C2419
SC1U6D3V2KX-GP
AA24 M26 +5VA_PCH_VCC5REFSUS
VCCASW3 V5REF_SUS
1

1
3D3V_S0 5V_S0
C2403

C2404
AA26
DY

Clock and Miscellaneous

VCCASW4 +VCCA_USBSUS
AN23
2

2
DCPSUS4
AA27 VCCASW5

2
VCCSUS3_3_1 AN24 3D3V_S5
AA29 VCCASW6 DY C2437
SC1U10V2KX-1GP 83.R0304.A8F
D2402
CH751H-40PT-GP

2
AA31 VCCASW7 2nd = 83.R3004.A8F
0.001A R2407

1
AC26 P34 +5VS_PCH_VCC5REF 1 2
VCCASW8 V5REF
C AC27 10R2J-2-GP C
VCCASW9

1
VCCP_CPU N20 3D3V_S5
VCCSUS3_3_2 C2427
0.08A

PCI/GPIO/LPC
L2402 AC29 VCCASW10
N22 SC1U10V2KX-1GP

2
+1.05VS_VCCA_A_DPL VCCSUS3_3_3
1 2 AC31 VCCASW11

1
P20 3D3V_S0
VCCSUS3_3_4
1

1
C2408

IND-10UH-238-GP AD29 C2428

SC10U6D3V5KX-1GP

C2407 VCCASW12 SC1U6D3V2KX-GP

68.1001E.10N DY P22

2
VCCSUS3_3_5
2nd = 68.10050.10Y SC1U6D3V2KX-GP AD31 Voltage Rail Voltage(V) Iccmax(A)
2

VCCASW13

1
C2430
W21 AA16 SCD1U16V2KX-3GP V_PROC_IO 1.05 0.001
VCCASW14 VCC3_3_1

2
W23 W16 3D3V_S0 V5REF 5 0.001
VCCASW15 VCC3_3_8
L2403 0.08A X02_0615
W24 VCCASW16 VCC3_3_4 T34 V5REF_Sus 5 0.001
1 2 +1.05VS_VCCA_B_DPL

1
W26 VCCASW17
C2431 Vcc3_3 3.3 0.228
1

1
C2409

IND-10UH-238-GP SCD1U16V2KX-3GP
DY
SC10U6D3V5KX-1GP

68.1001E.10N C2410 W29 X02_0615 3D3V_S0 VccADAC 3.3 0.063

2
VCCASW18
2nd = 68.10050.10Y SC1U6D3V2KX-GP
2

W31 AJ2 VccADPLLA 1.05 0.08

VCCASW19 VCC3_3_2

1
W33 VCCASW20
C2429 VccADPLLB 1.05 0.08
AF13 SCD1U16V2KX-3GP
VCCIO5
X02_0615 X02_0615 VccCore 1.05 1.7

2
+VCCRTCEXT N16 DCPRTC VCCP_CPU VccDMI 1.1 0.047
VCCIO12 AH13
1

C2411 0.167A
SCD1U16V2KX-3GP VCCVRM Y49 VCCVRM4 VCCIO13 AH14 VccIO 1.05 3.711

1
B B
2

C2432 VccASW 1.05 0.903

AF14 SC1U6D3V2KX-GP DY

2
VCCIO6
+1.05VS_VCCA_A_DPL BD47 VCCADPLLA
VccSPI 3.3 0.01

SATA
VCCAPLLSATA AK1
X02_0611 +1.05VS_VCCA_B_DPL BF47 VCCADPLLB
VccDSW3_3 3.3 0.001
VCCP_CPU +V1.05S_VCCAPLL_SATA3 1 TP2404
+VCCDIFFCLKN AF11 TPAD14-OP-GP VccDFTERM 1.8 0.002
R2412 VCCVRM1 VCCVRM
0.055A +VCCDIFFCLK AF17 VCCIO7
1 2 AF33 VCCDIFFCLKN1
VccRTC 3.3 6uA
AF34 VCCDIFFCLKN2 VCCIO2 AC16
1

0R0603-PAD-2-GP AG34 VCCDIFFCLKN3

VccSus3_3 3.3 0.095
C2414 AC17 VCCP_CPU
VCCIO3
SC1U6D3V2KX-GP VccSusHDA 3.3 0.01
2

+V1.05S_SSCVCC AG33 AD17

VCCSSC VCCIO4
VccVRM 1.5 0.167

1
X02_0615 +VCCSST V16 C2435 VccClkDMI 1.05 0.07
DCPSST
1

X02_0615 C2415 VCCP_CPU SC1U6D3V2KX-GP

2
SCD1U16V2KX-3GP VccSSC 1.05 0.095
T17 T21
2

TP2406 DCPSUS DCPSUS1 VCCASW22 VccDIFFCLKN 1.05 0.055

X02_0611 1 V19 DCPSUS2
TPAD14-OP-GP
MISC

VCCP_CPU X02_0615 V21 VccALVDS 3.3 0.001

VCCP_CPU VCCASW23
R2403 0.001A
CPU

BJ8 VccTX_LVDS 1.8 0.04

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

V_PROC_IO
C2418

C2420

1 2 +VCCDIFFCLK T19
VCCASW21
1

+3VS_+1.5VS_HDA_IO
1

0R0402-PAD-2-GP C2417 3D3V_S5 Refer to chipset EDS V.0.7

A R2402 <Core Design> A
C2412 SC4D7U6D3V3KX-GP 0.01A
2

HDA

SC1U6D3V2KX-GP A22 P32 1 2

RTC
2

RTC_AUX_S5 VCCRTC VCCSUSHDA

Wistron Corporation
1

6uA 0R0402-PAD-2-GP
VCCP_CPU PANTHER-GP-NF 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
R2404 0.095A C2433 Taipei Hsien 221, Taiwan, R.O.C.
71.PANTH.00U X02_0611
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

2
C2421

C2422

1 2 +V1.05S_SSCVCC X02_0615 SCD1U16V2KX-3GP

1

X02_0615 Title
1

0R0402-PAD-2-GP C2436
C2413 SC1U6D3V2KX-GP VCCSUSHDA need to be at either 3.3V or 1.5V. PCH (POWER2)
2

SC1U6D3V2KX-GP All the CODEC I/O Voltages need to be at the same Size Document Number Rev
2

A3 A00
level either 3.3 V or 1.5 V. BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 24 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PCH
PCH1I 9 OF 10

AY4 VSS159 VSS259 H46

AY42 VSS160 VSS260 K18
AY46 VSS161 VSS261 K26
AY8 VSS162 VSS262 K39
B11 K46
Vinafix.com B15
B19
VSS163
VSS164
VSS165
VSS263
VSS264
VSS265
K7
L18
B23 VSS166 VSS266 L2
D B27 VSS167 VSS267 L20 D
PCH1H 8 OF 10 B31 L26
VSS168 VSS268
H5 VSS0 B35 VSS169 VSS269 L28
B39 VSS170 VSS270 L36
AA17 VSS1 VSS80 AK38 B7 VSS171 VSS271 L48
AA2 VSS2 VSS81 AK4 F45 VSS172 VSS272 M12
AA3 VSS3 VSS82 AK42 BB12 VSS173 VSS273 P16
AA33 VSS4 VSS83 AK46 BB16 VSS174 VSS274 M18
AA34 VSS5 VSS84 AK8 BB20 VSS175 VSS275 M22
AB11 VSS6 VSS85 AL16 BB22 VSS176 VSS276 M24
AB14 VSS7 VSS86 AL17 BB24 VSS177 VSS277 M30
AB39 VSS8 VSS87 AL19 BB28 VSS178 VSS278 M32
AB4 VSS9 VSS88 AL2 BB30 VSS179 VSS279 M34
AB43 VSS10 VSS89 AL21 BB38 VSS180 VSS280 M38
AB5 VSS11 VSS90 AL23 BB4 VSS181 VSS281 M4
AB7 VSS12 VSS91 AL26 BB46 VSS182 VSS282 M42
AC19 VSS13 VSS92 AL27 BC14 VSS183 VSS283 M46
AC2 VSS14 VSS93 AL31 BC18 VSS184 VSS284 M8
AC21 VSS15 VSS94 AL33 BC2 VSS185 VSS285 N18
AC24 VSS16 VSS95 AL34 BC22 VSS186 VSS286 P30
AC33 VSS17 VSS96 AL48 BC26 VSS187 VSS287 N47
AC34 VSS18 VSS97 AM11 BC32 VSS188 VSS288 P11
AC48 VSS19 VSS98 AM14 BC34 VSS189 VSS289 P18
AD10 VSS20 VSS99 AM36 BC36 VSS190 VSS290 T33
AD11 VSS21 VSS100 AM39 BC40 VSS191 VSS291 P40
AD12 VSS22 VSS101 AM43 BC42 VSS192 VSS292 P43
AD13 VSS23 VSS102 AM45 BC48 VSS193 VSS293 P47
AD19 VSS24 VSS103 AM46 BD46 VSS194 VSS294 P7
AD24 VSS25 VSS104 AM7 BD5 VSS195 VSS295 R2
C AD26 AN2 BE22 R48 C
VSS26 VSS105 VSS196 VSS296
AD27 VSS27 VSS106 AN29 BE26 VSS197 VSS297 T12
AD33 VSS28 VSS107 AN3 BE40 VSS198 VSS298 T31
AD34 VSS29 VSS108 AN31 BF10 VSS199 VSS299 T37
AD36 VSS30 VSS109 AP12 BF12 VSS200 VSS300 T4
AD37 VSS31 VSS110 AP19 BF16 VSS201 VSS301 W34
AD38 VSS32 VSS111 AP28 BF20 VSS202 VSS302 T46
AD39 VSS33 VSS112 AP30 BF22 VSS203 VSS303 T47
AD4 VSS34 VSS113 AP32 BF24 VSS204 VSS304 T8
AD40 VSS35 VSS114 AP38 BF26 VSS205 VSS305 V11
AD42 VSS36 VSS115 AP4 BF28 VSS206 VSS306 V17
AD43 VSS37 VSS116 AP42 BD3 VSS207 VSS307 V26
AD45 VSS38 VSS117 AP46 BF30 VSS208 VSS308 V27
AD46 VSS39 VSS118 AP8 BF38 VSS209 VSS309 V29
AD8 VSS40 VSS119 AR2 BF40 VSS210 VSS310 V31
AE2 VSS41 VSS120 AR48 BF8 VSS211 VSS311 V36
AE3 VSS42 VSS121 AT11 BG17 VSS212 VSS312 V39
AF10 VSS43 VSS122 AT13 BG21 VSS213 VSS313 V43
AF12 VSS44 VSS123 AT18 BG33 VSS214 VSS314 V7
AD14 VSS45 VSS124 AT22 BG44 VSS215 VSS315 W17
AD16 VSS46 VSS125 AT26 BG8 VSS216 VSS316 W19
AF16 VSS47 VSS126 AT28 BH11 VSS217 VSS317 W2
AF19 VSS48 VSS127 AT30 BH15 VSS218 VSS318 W27
AF24 VSS49 VSS128 AT32 BH17 VSS219 VSS319 W48
AF26 VSS50 VSS129 AT34 BH19 VSS220 VSS320 Y12
AF27 VSS51 VSS130 AT39 H10 VSS221 VSS321 Y38
AF29 VSS52 VSS131 AT42 BH27 VSS222 VSS322 Y4
AF31 VSS53 VSS132 AT46 BH31 VSS223 VSS323 Y42
AF38 VSS54 VSS133 AT7 BH33 VSS224 VSS324 Y46
B B
AF4 VSS55 VSS134 AU24 BH35 VSS225 VSS325 Y8
AF42 VSS56 VSS135 AU30 BH39 VSS226 VSS328 BG29
AF46 VSS57 VSS136 AV16 BH43 VSS227 VSS329 N24
AF5 VSS58 VSS137 AV20 BH7 VSS228 VSS330 AJ3
AF7 VSS59 VSS138 AV24 D3 VSS229 VSS331 AD47
AF8 VSS60 VSS139 AV30 D12 VSS230 VSS333 B43
AG19 VSS61 VSS140 AV38 D16 VSS231 VSS334 BE10
AG2 VSS62 VSS141 AV4 D18 VSS232 VSS335 BG41
AG31 VSS63 VSS142 AV43 D22 VSS233 VSS337 G14
AG48 VSS64 VSS143 AV8 D24 VSS234 VSS338 H16
AH11 VSS65 VSS144 AW14 D26 VSS235 VSS340 T36
AH3 VSS66 VSS145 AW18 D30 VSS236 VSS342 BG22
AH36 VSS67 VSS146 AW2 D32 VSS237 VSS343 BG24
AH39 VSS68 VSS147 AW22 D34 VSS238 VSS344 C22
AH40 VSS69 VSS148 AW26 D38 VSS239 VSS345 AP13
AH42 VSS70 VSS149 AW28 D42 VSS240 VSS346 M14
AH46 VSS71 VSS150 AW32 D8 VSS241 VSS347 AP3
AH7 VSS72 VSS151 AW34 E18 VSS242 VSS348 AP1
AJ19 VSS73 VSS152 AW36 E26 VSS243 VSS349 BE16
AJ21 VSS74 VSS153 AW40 G18 VSS244 VSS350 BC16
AJ24 VSS75 VSS154 AW48 G20 VSS245 VSS351 BG28
AJ33 VSS76 VSS155 AV11 G26 VSS246 VSS352 BJ28
AJ34 VSS77 VSS156 AY12 G28 VSS247
AK12 VSS78 VSS157 AY22 G36 VSS248
AK3 VSS79 VSS158 AY28 G48 VSS249
H12 VSS250
PANTHER-GP-NF H18 VSS251
71.PANTH.00U H22 VSS252
A H24 VSS253 <Core Design> A
H26 VSS254
H30 VSS255
H32
H34
VSS256
VSS257
Wistron Corporation
F3 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS258 Taipei Hsien 221, Taiwan, R.O.C.

Title
PANTHER-GP-NF
71.PANTH.00U PCH (VSS)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 25 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 26 of 106
5 4 3 2 1
 SSID = KBC 5 4 3 2 1
VBAT PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE VBAT MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
A00_0803 X00 100.0K 10.0K 3.0V DMB50 100.0K 10.0K(64.10025.6DL) 3.0V
TBD 100.0K 13.7K(64.13725.6DL) 2.902V

1
3D3V_AUX_KBC VBAT 3D3V_S0 X01 100.0K 20.0K 2.75V TBD 100.0K 17.8K(64.17825.6DL) 2.801V
R2724 R2710 TBD 100.0K 22.1K(64.22125.6DL) 2.702V
X02_0611 47KR2F-GP X02 100.0K 33.0K 2.48V 10KR2F-2-GP TBD 100.0K 27.0K(64.27025.6DL) 2.598V
R2702 TBD 100.0K 32.4K(64.32425.6DL) 2.492V
A00 100.0K 47.0K 2.24V TBD 100.0K 37.4K(64.37425.6DL) 2.402V

2
1 2 VBAT TBD 100.0K 43.2K(64.43225.6DL) 2.304V
PCB_VER_AD Reserved 100.0K 64.9K 2.0V TBD 100.0K 49.9K(64.49925.6DL) 2.201V
2

1
0R0603-PAD-2-GP C2702 MODEL_ID_DET TBD 100.0K 57.6K(64.57625.6DL) 2.093V

1
Vinafix.com
R2771 SCD1U16V2KX-3GP C2703 Reserved 100.0K 76.8 1.87V TBD 100.0K 64.9K(64.64925.6DL) 2.001V
DY

1
2D2R3-1-U-GP SC2D2U10V3KX-1GP R2726 TBD 100.0K 73.2K(64.73225.6DL) 1.905V

1
100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V R2739 TBD 100.0K 82.5K(64.82525.6DL) 1.808V

1
3D3V_AUX_KBC_VCC C2717 100KR2F-L1-GP TBD 100.0K 93.1K(64.93125.6DL) 1.709V
DY
1

SCD1U10V2KX-5GP Reserved 100.0K 143.0K 1.358V C2718 TBD 100.0K 107K(64.10735.6DL) 1.594V
DY

2
D SCD1U10V2KX-5GP TBD 100.0K 120K(64.12035.6DL) 1.499V
D

2
Reserved 100.0K 174.0K 1.204V TBD 100.0K 137K(64.13735.6DL) 1.392V
X02_0615 TBD 100.0K 154K(64.15435.6DL) 1.299V
EC_AGND Reserved 100.0K 215.0K 1.048V TBD 100.0K 200K(64.20035.6DL) 1.099V
SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP
C2704

C2705

C2706

C2707

C2708

C2710
EC_AGND TBD 100.0K 232K(64.23236.6DL) 0.994V
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
3D3V_AUX_S5
1

1
C2701

C2709
SCD1U16V2KX-3GP

EC_VBKUP1 2
DY DY DY R2794
RTC_AUX_S5
2

2
0R0402-PAD-2-GP

X02_0611

115

102

114
C2711

19
46
76
88

75
4
U2701A 1 0F 2 SC220P50V2KX-3GP
1 2 U2701B 2 0F 2
DY

VCC1
VCC2
VCC3
VCC4
VCC5

VSBY

VBKUP
AVCC

VDD
KCOL[0..16] 69
X02_0615 X02_0615
X02_0615 X02_0615 EC_AGND X02_0611 31 53 KCOL0
R2778 28 FAN_TACH1 GPIO56/TA1 KBSOUT0/GPOB0/JENK#
63 52 KCOL1
40 AD_IA 31 PCIE_WAKE# GPIO14/TB1 KBSOUT1/GPIOB1/TCK
104 7 PLT_RST#_EC 1 2 0R0402-PAD-2-GP 64 51 KCOL2
VREF LRESET#/GPIOF7 PLT_RST# 5,18,31,65,66,71,83 19,36,37,47 PM_SLP_S3# GPIO1/TB2 KBSOUT2/GPIOB2/TMS
X02_0615 2 50 KCOL3
LCLK/GPIOF5 CLK_PCI_KBC 18 KBSOUT3/GPIOB3/TDI
EC_AGND C2714 1 2 SCD1U16V2KX-3GP 97 3 LPC_FRAME# 21,71 LPC_AD[3..0] 21,71 68 PWRLED# 32 49 KCOL4
PCB_VER_AD GPIO90/AD0 LFRAME#/GPIOF6 LPC_AD3 GPIO15/A_PWM KBSOUT4/GPOB4/JEN0# KCOL5
98 1 29 KBC_BEEP 118 48
GPIO91/AD1 LAD3/GPIOF4 LPC_AD2 GPIO21/B_PWM KBSOUT5/GPIOB5/TDO KCOL6
38 PSID_EC 99 128 82 INSTANT_LAUNCH#_LED# 62 47
AMB_TEMP GPIO92/AD2 LAD2/GPIOF3 LPC_AD1 GPIO13/C_PWM KBSOUT6/GPIOB6/RDY# KCOL7
100 127 69 KB_BL_CTRL 65 43
GPIO93/AD3 LAD1/GPIOF2 LPC_AD0 GPIO32/D_PWM KBSOUT7/GPIOB7 KCOL8
66,68 AOAC_WWAN_EN# 108 126 82 AUDIO_PRESENT#_LED# 22 42
GPIO5/AD4 LAD0/GPIOF1 GPIO45/E_PWM KBSOUT8/GPIOC0 KCOL9
38 AC_IN_KBC# 96 125 INT_SERIRQ 21 19 PCH_WAKE#_EC 81 41
GPIO4/AD5 SERIRQ/GPIOF0 GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS# KCOL10
X02_0619 R2793 62 USBCHARGER_CB0 95
GPIO3/AD6 GPIO11/CLKRUN#
8 PM_CLKRUN#_EC 19 82 MOBILITY_CENTER#_LED# 66
GPIO33/H_PWM KBSOUT10&P80_CLK/GPIOC2
40
MODEL_ID_DET 94 9 16 39 KCOL11
GPIO7/AD7 GPIO65/SMI# L_BKLT_EN 17 68 CHG_AMBER_LED# GPIO40/F_PWM KBSOUT11&P80_DAT/GPIOC3
2 1 29 ECSCI#_KBC 38 KCOL12
49 KBC_BKLT DY 101
ECSCI#/GPIO54
124 MOBILITY_CENTER# 82
KBSOUT12/GPIO64
37 KCOL13
0R2J-2-GP 28 FAN1_DAC GPIO94/DA0 GPIO10/LPCPD# KBSOUT13/GPIO63 KCOL14
40 AD_IA_HW 105 121 H_A20GATE 22 21 ME_UNLOCK 23 36
GPIO95/DA1 GPIO85/GA20 GPIO46/CIRRXM/TRIST# KBSOUT14/GPIO62 KCOL15
82 AUDIO_PRESENT# 106 122 H_RCIN# 22 65,66 AOAC_PCIE_WAKE# 113 35
GPIO96/DA2 KBRST#/GPIO86 GPIO87/CIRRXM/SIN_CR KBSOUT15/GPIO61/XOR_OUT KCOL16
36,42 IMVP_PWRGD 107 65 E51_TxD 111 34
GPIO97/DA3 GP/I/O83/SOUT_CR/TRIST# GPIO60/KBSOUT16 USB_DET#
33
GPIO57/KBSOUT17
KROW[0..7] 69
3G_EN 79 27 77 54 KROW0
66 3G_EN GPIO02 GPIO52/PSDAT3/RDY# BLON_OUT 49 19 PCH_SUSCLK_KBC GPIO0/EXTCLK KBSIN0/GPIOA0/N2TCK
ECSMI#_KBC 6 25 AD_IA_HW2 30 55 KROW1
GPIO24 GPIO50/PSCLK3/TDO AD_IA_HW2 40 29 AMP_MUTE# GPIO55/CLKOUT/IOX_DIN_DIO KBSIN1/GPIOA1/N2TMS
69 CAP_LED# 109 11 PWR_CHG_AD_OFF 38 56 KROW2
GPIO30/F_WP# GPIO27/PSDAT2 ECRST# KBSIN2/GPIOA2 KROW3
36 S5_ENABLE 14 10 INSTANT_LAUNCH# 82 85 57
GPIO34/CIRRXL GPIO26/PSCLK2 VCC_POR# KBSIN3/GPIOA3 KROW4
15 71 58
68 BATT_WHITE_LED#
39 BAT_IN# 80
GPIO36
GPIO41/F_WP#
GPIO35/PSDAT1
GPIO37/PSCLK1
72
TPDATA 69
TPCLK 69
TP VCCP_CPU R2721 KBSIN4/GPIOA4
KBSIN5/GPIOA5
59 KROW5
17 1 43R2J-GP2 PECI 13 60 KROW6
C 70 LID_CLOSE#
19 RSMRST#_KBC
19,46 PM_SLP_S4#
20
21
GPIO42/TCK
GPIO43/TMS
70
5,22 H_PECI
1
R2720
2 EC_VTT 12
PECI
VTT
KBSIN6/GPIOA6
KBSIN7/GPIOA7
61 KROW7 C
BAT_SCL 39,40
Charger

1
GPIO44/TDI GPIO17/SCL1/N2TCK 0R0402-PAD-2-GP C2716
62 USBCHG_EN 26 69 BAT_SDA 39,40
GPIO51/N2TCK GPIO22/SDA1/N2TMS

SCD1U16V2KX-3GP
ECSWI#_KBC 123 67 NPCE885PA0DX-1-GP
65 WIFI_RF_EN 82
GPIO67/N2TMS GPIO73/SCL2
68
SML1_CLK 20,28,86 PCH

2
GPIO75 GPIO74/SDA2 SML1_DATA 20,28,86
65,68 AOAC_WLAN_EN# 83
GPIO76 GPIO23/SCL3
119 PM_LAN_ENABLE 31 X02_0611
Layout Note: 19,36 S0_PWR_GOOD 84
GPIO77 GPIO31/SDA3
120 RTCRST_ON 21 X02_0611
24 PROCHOT_EC
Need very close to EC GPIO47/SCL4
28 LCD_TST_EN 49
Layout Note:
EC_SPI_CS#_C GPIO53/SDA4
21,60 SPI_CS0#_R
33R2J-2-GP 1 R2736 2 90
F_CS0#
X02_0611 1 R2792 2 LCD_TST 49 Need very close to EC
33R2J-2-GP 1 R2719 2 EC_SPI_CLK_C 92 0R0402-PAD-2-GP R2764 1 2 ECSCI#_KBC
21,60 SPI_CLK_R F_SCK 22 EC_SCI#
33R2J-2-GP 1 R2725 2 EC_SPI_DI_C 86 74 PSL_OUT# 0R0402-PAD-2-GP
21,60 SPI_SO_R F_SDI&F_SDIO1 PSL_OUT_GPIO71#
33R2J-2-GP 1 R2722 2 EC_SPI_DO_C 87 93 PSL_IN2# X02_0615 R2723 1 2 ECSMI#_KBC
21,60 SPI_SI_R F_SDIO&F_SDIO0 PSL_IN2_GPI06# 22 EC_SMI#
91 73 PSL_IN1# 0R0402-PAD-2-GP
68 TP_LOCK_LED# GPIO81/F_WP# PSL_IN1_GPI70# R2727 1 2 ECSWI#_KBC
20 EC_SWI#
0R0402-PAD-2-GP
19 PM_PWRBTN# 117
GPIO20/TA2/IOX_DIN_DIO
19 AC_PRESENT 112
GP/I/O84/IOX_SCLK/XORTR# KBC_VCORF
63,82 USB_PWR_EN# 110 44
GPO82/IOX_LDSH/TEST# VCORF

1
C2712 PM_CLKRUN#_EC R2730 1 2 0R2J-2-GP
DY BOOST_MODE# 40
AGND
GND1
GND2
GND3
GND4
GND5
GND6

SC1U25V3KX-1-GP
AOAC Ambient temperature detect

2
H_A20GATE R2731 1 2 0R2J-2-GP
NPCE885PA0DX-1-GP DY DGPU_PWROK 22,92,93
18
45
78
89
116
5

EC_AGND 103

VBAT
71.00885.C0G
Layout Note:
X01_0413 Need very close to EC 3D3V_AUX_S5 For System Reset.
1

R2713 X02_0611

1
10KR2F-2-GP ECRST#
R2765 Layout Note: R2705 3D3V_AUX_KBC
1 2 Connect GND and AGND planes via either 10KR2J-3-GP
2

RN2702
0R resistor or connect directly.

2
AMB_TEMP 0R0402-PAD-2-GP C2715 USB_DET# 1 8

1
MOBILITY_CENTER# 2 7

SC1U6D3V2KX-GP
E
EC_AGND 6 5 INSTANT_LAUNCH# 3 6
DY
2

28,36,86 PURE_HW_SHUTDOWN# B AUDIO_PRESENT# 4 5

2
1

R2703 C2726 C2725 RSTSW1

SCD1U16V2KX-3GP

NTC-10K-27-GP Q2701 SW-TACT-130-GP-U SRN100KJ-5-GP

SC100P50V2JN-3GP

1
C
B EC_GPIO47 High Active
MMBT3906-4-GP 3D3V_AUX_KBC
B
2

69.60013.131 84.T3906.A11
1

RN2701
2nd = 69.60011.201 R2740 2nd = 84.03906.F11
3rd = 69.60037.011 0R2J-2-GP BAT_SCL 3 2
1 2 BAT_SDA 4 1
DY 62.40009.731
2nd = 62.40089.441 SRN4K7J-8-GP
EC_AGND 3rd = 62.40009.D71
X02_0615
X02_0611 ECRST# R2707 1 2 10KR2J-3-GP

PROCHOT_EC 3D3V_AUX_KBC
R2733
H_PROCHOT#_EC 1 2
G

H_PROCHOT# 5,40
1

Q2702
R2732 0R0402-PAD-2-GP
Power Switch Logic(PSL)
1

100KR2J-1-GP C2713
S D SC47P50V2JN-3GP AC_IN_KBC# R2714 1 2 100KR2J-1-GP
BAT_IN# R2715 1 DY 2 100KR2J-1-GP
2

OVER_CURRENT_P8# R2717 1 2 100KR2J-1-GP

3D3V_AUX_S5 2N7002BK-GP DY
84.07002.I31
86 OVER_CURRENT_P8# 1 2 PCH_WAKE#_EC
2

X02_0615 R2728
X02_0611 R2704 0R0402-PAD-2-GP
330KR2J-L1-GP 3D3V_S0
3D3V_AUX_S5 X02_0615 3D3V_AUX_S5
X02_0611
R2767
1

C2722
2

1 2 PSL_IN2# FAN_TACH1 R2708 1 2 10KR2J-3-GP

68 KBC_PWRBTN#
R2734 1 2
0R0402-PAD-2-GP 330KR2J-L1-GP 3D3V_WLAN_AOAC R2799 Stuff if LID_CLOES# is open drain.
SCD1U16V2KX-3GP
R2768 3D3V_S5
S
1

R2716 R2735
1 2 PSL_IN1#
40 AC_IN#
2

PSL_OUT# 1 2 KBC_ON#_GATE_L 1 2 KBC_ON#_GATE G G 2 LID_CLOSE# R2799 1 2 100KR2J-1-GP

0R0402-PAD-2-GP R2791 R2706
DY 0R2J-2-GP 100KR2J-1-GP 3D3V_WLAN_AOAC 3G_EN R2712 1 2 10KR2J-3-GP
1KR2J-1-GP 20KR2J-L2-GP Q2703 D
D2702 DY
DMP2130L-7-GP 2
1

1
D

84.02130.031
2ND = 84.03413.A31 AOAC_PCIE_WAKE# 2 1AOAC_PCIE_WAKE#_R 3 3D3V_WWAN_AOAC
DY DY
A 3D3V_AUX_KBC R2701
100KR2J-1-GP
1 A
D2707 CH715FPT-GP
1 USB_DET# 3D3V_AUX_KBC 3D3V_LAN_S5
83.R0304.B81
3 2nd = 83.00040.E81 <Core Design>
62 USBDET_CON#
1

2 KBC_ON#_GATE_L R2709
10KR2J-3-GP R2711 Wistron Corporation
G

BAT54CPT-GP Q2704 100KR2J-1-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
83.R2003.E81 Taipei Hsien 221, Taiwan, R.O.C.
2

2ND = 83.00054.Q81
1

S D S5_ENABLE PCIE_WAKE# Title

2N7002BK-GP
KBC Nuvoton NPCE885
X02_0615 Size Document Number Rev
84.07002.I31 A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 27 of 106

5 4 3 2 1
 5 4 3 2 1

SSID = Thermal
3D3V_S0
RN2801
2 3
1 4 Fan controller
X02_0628
SRN2K2J-1-GP

3D3V_S0 Vinafix.com R2802

0R2J-2-GP
U2802 5V_S0

1 2 FON# 1 8
D
Q2804
5V_S0
DY 2
FSM# GND
7 D
THM_SML1_DATA FAN_VCC VIN GND
20,27,86 SML1_DATA 6 D S 1 3 VOUT GND 6

1
27 FAN1_DAC 4 5 C2803 C2804
VSET GND

SCD1U16V2KX-3GP
C2814
5 G G 2

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP
1

1
C2813

2
SCD1U16V2KX-3GP 4 S D 3 APL5606AKI-TRG-GP
74.05606.A71

2
2N7002BKS-GP-U 2nd = 74.02113.0E1
84.2N702.E3F THM_SML1_CLK Layout Note:
X02_0615 Need 10 mil trace width.
X02_0615
20,27,86 SML1_CLK X02_0615
84.03904.L06
2ND = 84.03904.P11
NCT7718_DXP X01_0504
U2801 X02_0611
3

1
1 8 THM_SML1_CLK FAN1
VDD SCL R2807
1 C2816 C2812 2 7 THM_SML1_DATA 4
Q2803 SC470P50V3JN-2GP SC2200P50V2KX-2GP D+ SDA ALERT# FAN_TACH1_C
3 6 1 2 1
DY 27 FAN_TACH1
2

2
PMBS3904-1-GP D- ALERT# 0R0402-PAD-2-GP
4 5

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
2

T_CRIT# GND

1
C2808

C2815
NCT7718_DXN 2
FAN_VCC 3
2.System Sensor, Put on palm rest NCT7718W -GP DY DY 5

2
74.07718.0B9

2
R2813 ACES-CON3-13-GP

1
THERM_SYS_SHDN# 1 2 T_CRIT# C2809 D2802 20.F1295.003
Layout Note:

1
C 0R0402-PAD-2-GP SC4D7U6D3V3KX-GP C
DY DY

CH551H-30PT-GP
3D3V_S0 Signal Routing Guideline: C2810 2nd = 20.F1841.003
X02_0611 DY

2
SC2200P50V2KX-2GP
Layout Note: Trace width = 15mil

2
C2812 close U2801 ALERT# R2815 1 2 18K7R2F-GP

T_CRIT# R2814 1 2 2KR2F-3-GP

83.R5003.C8F
Layout Note: 2ND = 83.R5003.H8H
3rd = 83.5R003.08F
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

FAN_TACH1_C 1 AFTP2801

FAN_VCC 1 AFTP2802

3D3V_S0

EMI

FAN_VCC
G

B Q2802 B

27,36,86 PURE_HW _SHUTDOW N# D S THERM_SYS_SHDN#

1
EC2801
2N7002BK-GP DY SCD1U16V2KX-3GP

2
1

C2811 84.07002.I31
SCD1U10V2KX-5GP
DY
2

X02_0615

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Thermal NCT7718W/Fan Controllor P2793
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 28 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO X02_0611

+AVDD 5V_S0 +PVDD 5V_S0
R2940 R2935
X02_0615
AUD_DVDDCORE 1 2 1 2
0R0603-PAD-2-GP
Layout Note:

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
1

C2941

C2940

C2952

C2949
0R0805-PAD-2-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

1
C2951

C2950
Signal Routing Guideline: X01_0420 C2939 X02_0611
Close to Codec Vinafix.com SC10U6D3V5KX-1GP C2937

2
SC10U6D3V5KX-1GP

2
3D3V_S0 U2901
D X01_0420 X01_0420 D
X02_0615 1 DVDD_CORE AVDD1 27
AVDD2 38

3 45

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
DVDD_IO PVDD

1
C2943

C2936
PVDD 39 +PVDD X02_0615

C2942
9 13 AUD_SENSE_A

2
DVDD SENSE_A AUD_SENSE_B
SENSE_B 14 X02_0615
28 MIC_IN_L_R C2947 1 2 SC1U16V3KX-5GP MIC_IN_R 58
PORTA_L
PORTA_R 29
23 AUD_VREFOUT_A
HDA_CODEC_BITCLK VREFOUT_A AUD_VREFOUT_A 58
21 HDA_CODEC_BITCLK 6 BITCLK
31 AUD_HP1_JACK_L
HDA_CODEC_SDOUT PORTB_L AUD_HP1_JACK_R AUD_HP1_JACK_L 58
21 HDA_CODEC_SDOUT 5 SDATA_OUT PORTB_R 32 AUD_HP1_JACK_R 58
HDA_CODEC_SYNC 10 19
21 HDA_CODEC_SYNC SYNC PORTC_L
PORTC_R 20
21 HDA_SDIN0 1 R2908 2 HDA_CODEC_SDIN0 8 SDATA_IN VREFOUT_C/GPIO4 24
33R2J-2-GP
HDA_CODEC_RST# 11 15
21 HDA_CODEC_RST# RESET# PORTE_L
PORTE_R 16
3D3V_S0 R2928
R2902 1 2 0R2J-2-GP 10KR2J-3-GP 17
DY 1 2
PORTF_L
18
D2902 EAPD# PORTF_R
27 AMP_MUTE# 1 2 83.R0304.A8F 47 EAPD
CH751H-40PT-GP 2nd = 83.R3004.A8F 40 AUD_SPK_L+
R2926 PORTD_+L AUD_SPK_L+ 58
49 AUD_DMIC_CLK 1 2 33R2J-2-GP AUD_DMIC_CLK_R 2 DMIC_CLK/GPIO1 PORTD_-L 41 AUD_SPK_L-
AUD_SPK_L- 58
C R2941 1 2 AUD_DMIC_IN0_R 4 C
49 AUD_DMIC_IN0 0R0402-PAD-2-GP DMIC_0/GPIO2 AUD_SPK_R+
PORTD_+R 44 AUD_SPK_R+ 58
A00_0803 48 43 AUD_SPK_R-
SPDIFOUT0/GPIO3 PORTD_-R AUD_SPK_R- 58
46 DMIC1/GPIO0/SPDIFOUT1
MONO_OUT 25 X02_0615
PUMP_CAPP 36 12 AUD_PC_BEEP C2953 1 2 SCD1U16V2KX-3GP SB_SPKR_R 1 2 HDA_SPKR 21
CAP+ PCBEEP C2954 1 2 SCD1U16V2KX-3GP KBC_BEEP_R R2948 1 2100KR2J-1-GP KBC_BEEP 27
R2949 100KR2J-1-GP
C2935 1 VREFFILT 21 AUD_VREFFLT
SC4D7U6D3V3KX-GP 22 AUD_CAP2
CAP2

2
PUMP_CAPN 35 34 AUD_V_B
2

CAP- V- AUD_VREG R2946 R2947

VREG_+2.5V 37
10KR2J-3-GP 10KR2J-3-GP
7
Layout Note: DVSS

SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

1
Signal Routing Guideline: 42 PVSS AVSS1 26

C2944

C2955

C2945
Close to Codec AVSS2 30

1
49 GND AVSS2 33
C2938
Azalia I/F EMI SC10U6D3V5KX-1GP

2
92HD94B2X5NLGXW CX8-GP X01_0420
HDA_CODEC_SDOUT 71.92H94.B03
1

R2918
47R2J-2-GP
DY
B B
2
1 PCH_AZ_CODEC_SDOUT1

+AVDD +AVDD
C2924
DY SCD1U10V2KX-5GP
2

2
R2929 R2937
2K49R2F-GP 10KR2J-3-GP
2

1
1 2 AUD_SENSE_A AUD_SENSE_B
58 AUD_HP1_JD#
R2919 R2931 20KR2F-L-GP
1

47R2J-2-GP
HDA_CODEC_BITCLK_C 1 2 HDA_CODEC_BITCLK 1 2 C2946
DY 58 EXT_MIC_JD# SC1000P50V3JN-GP-U
2

A HDA_CODEC_RST# R2901 39K2R2F-L-GP <Core Design> A

AUD_DMIC_CLK
AUD_DMIC_IN0
Layout Note:
Wistron Corporation
SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

Close to pin 13
1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

EC2907

EC2913

EC2914

EC2915

Taipei Hsien 221, Taiwan, R.O.C.

DY DY DY DY
2

Title
AUDIO CODEC
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 29 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserve
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 30 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = LOM
3D3V_LAN_S5 3D3V_LAN_S5

3D3V_S5 Q3106 3D3V_LAN_S5

DMP2130L-7-GP

1
2
1
RN3101
R3102 SRN10KJ-5-GP S
10KR2J-3-GP
Vinafix.com DY D

D
C3132

G
SCD1U16V2KX-3GP
R3103 R3116

1Q402_14
3

1
10KR2J-3-GP C3130 C3133 C3134

CLK_LAN_REQ#_EN
D 10KR2J-3-GP X02_0615 84.02130.031 D

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
SC1U10V2KX-1GP

2
X01_0417

2
1 2PM_LAN_ENABLE_R

2 3 PLT_RST#_LAN R3117
84.03904.L06
5,18,27,65,66,71,83 PLT_RST# DY 20KR2J-L2-GP
Q3102

LAN_ENABLE_R_C
2ND = 84.03904.P11 27 PM_LAN_ENABLE
PMBS3904-1-GP

2
Q3101
PMBS3904-1-GP 1 2 R3122 X02_0615 X02_0615

G
20 PCIE_CLK_LAN_REQ# 3 2 CLK_LAN_REQ#_R R3113 100KR2J-1-GP
0R0402-PAD-2-GP Q3105
R3106

1
2
DY 1 X02_0611 S D

0R2J-2-GP
2N7002BK-GP
3D3V_LAN_S5 3D3V_LAN_S5 84.07002.I31
U3101
RF
1 VDD33
AVDDL 38
LED0

2
C3101 C3102 C3103 C3104 C3105 C3114 C3113 16 39
Layout Note: AVDD33 LED1

1
SC1U10V2KX-1GP

SCD1U16V2ZY-2GP

EC3102
SCD1U10V2KX-5GP

EC3103
SCD1U10V2KX-5GP

EC3104
SCD1U10V2KX-5GP
19 23
DY DY DY AVDDL LED2
1

3D3V_S0 3D3V_LAN_S5
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U10V2KX-1GP

SCD1U16V2ZY-2GP

SC1KP50V2KX-1GP

Close to pin16 13
DY

1
AVDDL LAN_SMDATA 1 TP3104 TPAD14-OP-GP
31 26
2

2
AVDDL SMDATA LAN_SMCLK
34 25
2

AVDDL SMCLK

1
AVDDVCO 6 AVDDL_REG

1
C 9 R3136 R3137 C
AVDDH
22
AVDDH_REG
8 LAN_XTAL1 C3110 30KR2J-4-GP DY 30KR2J-4-GP
AVDDH XTLI
7 LAN_XTAL0 DY SCD1U10V2KX-4GP

2
XTLO
DVDDL 37

2
DVDDL_REG RBIAS ISOLATn
RBIAS 10
2 PLT_RST#_LAN X02_0704 RBIAS
Layout Note: 33
PERST#
5 ISOLATn
20 CLK_PCIE_LAN REFCLK_P DEBUGMODE

1
Close to pin1 20 CLK_PCIE_LAN# 32 REFCLK_N

2
AVDDL 24 LOM_PPS1 C3111
PPS TP3103 SCD1U16V2KX-3GP R3131
20 PCIE_TXP6 35

2
RX_P TPAD14-OP-GP
20 PCIE_TXN6 36 RX_N TESTMODE 27 2K37R2F-GP

C3107 C3106 SCD1U16V2ZY-2GP 2 1 C3118 PCIE_RXP6_L 30 40 LX

1
20 PCIE_RXP6 TX_P LX
1

C3119 C3112 SCD1U16V2ZY-2GP 2 1 C3117 PCIE_RXN6_L 29

Layout Note: Layout Note: 20 PCIE_RXN6 TX_N
1

2
SC1U10V2KX-1GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

TRXP2 17 LAN_MDI2P 59
Close to pin6 Close to pin13 59 LAN_MDI0P 11 18 LAN_MDI2N 59
2

SCD1U16V2ZY-2GP

TRXP0 TRXN2
59 LAN_MDI0N 12
2

TRXN0
TRXP3 20 LAN_MDI3P 59
59 LAN_MDI1P 14 TRXP1 TRXN3 21 LAN_MDI3N 59
59 LAN_MDI1N 15 TRXN1
NC#28 28
27 PCIE_W AKE# 3 WAKE#
CLK_LAN_REQ#_R 4 41
Layout Note: CLKREQ# GND
Close to pin31
AR8161-BL3A-R-GP
71.08161.A03
AVDDH
B B

DVDDL AVDDL AVDDVCO

C3109 C3108 C3116
SCD1U16V2ZY-2GP

Layout Note: Layout Note: L3102 L3101

1

2
SC1U10V2KX-1GP

SCD1U16V2ZY-2GP

L3103
Close to pin9 Close to pin22 LX 2 1 2 1 2 1
2

IND-4D7UH-253-GP C3127 C3126 C3125 C3123 C3124 MHC1608S601LBP-GP MHC1608S601LBP-GP

SCD1U10V2KX-5GP

1
SCD1U16V2ZY-2GP

SC1U10V2KX-1GP
68.4R71E.10R 68.00335.091 68.00335.091
1

1
SC1KP50V2KX-1GP

SCD1U16V2ZY-2GP

SC10U6D3V5KX-1GP
2nd = 68.4R71G.10G DY DY
EC3101

DY

2
2

2
AVDDVCO Layout Note:
Close to pin37

C3122 C3120 C3121

1

1
SC4D7U6D3V3KX-GP

SCD1U16V2ZY-2GP

SC1U10V2KX-1GP

DY Layout Note:
Close to pin34
2

X3101

LAN_XTAL1 1 4
A <Core Design> A

LAN_XTAL0
2 3
Wistron Corporation
1

C3128
SC18P50V2JN-1-GP 1 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
XTAL-25MHZ-155-GP C3129 Taipei Hsien 221, Taiwan, R.O.C.
2

SC18P50V2JN-1-GP
2

82.30020.D41 Title
2nd = 82.30020.G71
3rd = 82.30020.G61 LOM
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 31 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C
(Blanking) C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 32 of 106

5 4 3 2 1
 A B C D E

Vinafix.com
4 4

3 3

(Blanking)

2 2

1 <Core Design> 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 33 of 106
A B C D E
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 34 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 35 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend
D3602
BAS16-6-GP
2
D3601
19,27 S0_PW R_GOOD 3 BAS16-6-GP
2
Vinafix.com
83.00016.K11
2ND = 83.00016.F11
1
3 PURE_HW _SHUTDOW N# 27,28,86

D 41 3V_5V_EN 1 83.00016.K11 D
2ND = 83.00016.F11
X02_0611

1
1 2 S5_ENABLE 27
R3602
R3614
200KR2J-L1-GP DY R3603
27,42 IMVP_PW RGD 1 2 SYS_PW ROK 19 1KR2J-1-GP

2
1
0R0402-PAD-2-GP
C3612
PS_S3CNTRL SCD01U50V2KX-1GP DY

2
G
Q3603

S D

2N7002BK-GP
84.07002.I31
ROSA Run Power X02_0615

15V_S5
Rds(on) = 11 ~ 14mOhm
5V_S5
AO4468 MAX 11.6A 5V_S0
U3601
SI4178DY-T1-GE3-GP
8 D S 1
C 2 7 D S 2 C
R3604 6 D S 3
100KR2J-1-GP 5 D
84.04178.037 5V_S0
G 2nd = 84.04468.037
1

4
3rd = 84.02659.037 5V_S0 Comsumption

1
3D3V_AUX_S5
1 2 5V_RUN_ENABLE C3603 Peak current 6A
SC10U6D3V5KX-1GP

2
1
R3605
10KR2J-3-GP C3608
1 2 PS_S3CNTRL SCD01U50V2KX-1GP
PS_S3CNTRL 37

2
R3606
100KR2J-1-GP
D G S
Rds(on) =11 ~ 14mOhm
AO4468 MAX 11.6A
D 6

G 5

S 4

Q3602
2N7002BKS-GP-U
3D3V_S5 U3602 3D3V_S0
84.2N702.E3F SI4178DY-T1-GE3-GP
1 S

2 G

3 D

8 D S 1
X02_0615 7 D S 2
S G D 6 D S 3
5 D 3D3V_S0
84.04178.037
G 2nd = 84.04468.037
4

1
B 19,27,37,47 PM_SLP_S3# 3rd = 84.02659.037 3D3V_S0 Comsumption B
C3604
1 2 3.3V_RUN_ENABLE SC10U6D3V5KX-1GP Peak current 2.5A
21,37 RUN_ENABLE

2
1

R3607
10KR2J-3-GP C3605
SCD01U50V2KX-1GP
2

1D5V_S3 1D5V_S0

1D5V_S0
U3606
8 D S 1 TPCA8062-H-GP MAX 28A
7 D S 2
6 D S 3
Rds(on) = 4.1~5.6m Ohm
1

5 D G 4 MAX Current 6A
C3609
<Core Design>
A TPCA8062-H-GP SC10U6D3V5KX-1GP A
2

1 2 1.5V_RUN_ENABLE
84.08062.037
R3630 2nd = 84.00460.037 Wistron Corporation
1

10KR2J-3-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

C3610 Taipei Hsien 221, Taiwan, R.O.C.
SCD01U50V2KX-1GP
2

Title

Power Plane Enable

Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 36 of 106

5 4 3 2 1
 5 4 3 2 1

Close to DIMM
S3 Power Reduction Circuit SM_DRAMPWROK

0D75V_S0 1D5V_S0
Close to CPU
Vinafix.com

1
S3 Power Reduction Circuit Processor VREF_DQ Implementation
R3703 R3704
22R2J-2-GP 220R2J-L2-GP
D
R3707 DY D

0R2J-2-GP

Q3702_D2
1 2
DY

Q3701_D
M_VREF_DQ_DIMMA X02_0615
Q3708 +V_SM_VREF_CNT

D
D
D S Q3702
Q3701 2N7002K-2-GP

2
36 PS_S3CNTRL G
DY 84.2N702.J31
2N7002BK-GP 2ND = 84.2N702.031

G
84.07002.I31
R3705 2N7002BK-GP

S
100KR2J-1-GP 84.07002.I31

S
X02_0615
21,36 RUN_ENABLE 36 PS_S3CNTRL

X02_0611
R3710

45,48 1D05V_VTT_PW RGD 2 1

0R0402-PAD-2-GP Close to CPU
C C
1 2 0D75V_EN S3 Power Reduction Circuit SM_DRAMRST#
19,27,36,47 PM_SLP_S3# R3716 DY 22R2J-2-GP 0D75V_EN 46

1
C3705
SCD1U10V2KX-5GP 1D5V_S3
DY

1
36 PS_S3CNTRL R3706
X02_0615 1KR2J-1-GP
G

Q3704
X02_0615 S3 Power Reduction Circuit

2
S D 0D75V_EN Q3703 SM_DRAMRST#

2N7002BK-GP 5 SM_DRAMRST# S D SM_DRAMRST#_D 1 2 DDR3_DRAMRST# 14,15

84.07002.I31
R3718
1KR2J-1-GP
SM_DRAMPWROK must have a maximum of 15ns rise or fall time 2N7002BK-GP

G
over VDDQ * 0.55± 200mV and the edge must be monotonic 84.07002.I31
20 DRAMRST_CNTRL_PCH

1
C3702
SC100P50V2JN-3GP

2
1
B B
Close to CPU C3703
S3 Power Reduction Circuit SM_DRAMPWROK SCD047U16V2KX-1-GP

2
3D3V_S0
1D5V_S0
1

R3714
10KR2J-3-GP R3702
200R2F-L-GP
U3701 DY
2

19 PM_DRAM_PW RGD PM_DRAM_PW RGD 1 5

2

A VCC
1D05V_VTT_PW RGD 2 B
3 4 VDDPW RGOOD_R 1 2 VDDPW RGOOD 5
GND Y
U74LVC1G08G-AL5-R-GP-U R3719
910R2F-1-GP
73.01G08.EHG
1

2nd = 73.7SZ08.EAH R3722 R3720

750R2F-GP
3rd = 73.7SZ08.DAH DY 39R2J-L-GP
A 4th = 73.01G08.L04 <Core Design> A
2

Q3709

36 PS_S3CNTRL G Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY D VDDPW RGOOD_D Taipei Hsien 221, Taiwan, R.O.C.

S Title

R3717
2N7002K-2-GP
S3 Power Reduction
0R2J-2-GP Size Document Number Rev
PM_DRAM_PW RGD VDDPW RGOOD_R A3 A00
1
DY 2 BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 37 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Support 5V_S5

2
PR3802 84.03904.L06

1
15KR2J-1-GP 2nd = 84.03904.P11 3D3V_S5
Vinafix.com PR3803

2
10KR2J-3-GP

1
PQ3802_1 1 PMBS3904-1-GP 3D3V_S5

1
D
PQ3802 D

2
2
PD3803

1
PR3811 PSID_DISABLE#_R_C BAV99-5-GP-U
100KR2J-1-GP PR3806
2K2R2J-2-GP

Layout Note: X02_0611 83.00099.T11

G
1

3
PQ3801 84.00301.A31 2nd = 83.3X101.011

2
PSID Layout width > 25mil FDV301N-NL-GP 2nd = 84.3K329.031
PR3801
PR3807
PS_ID_R 1 2 PS_ID_R2 D S PS_ID 1 2

D
PSID_EC 27
0R0603-PAD-2-GP 33R2J-2-GP

2
PD3804 PR3808
1 2
DY PESD24VS2UT-GP DY
33R2J-2-GP

3
DCIN1
5 1 AFTP3801
4 +DC_IN AD+
C 3 PU3801 C
2 1 S D 8
AFTP3802 S D

PC3805

PC3803

PC3804
1 1 2 7

SC1U25V5KX-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP
1
S D

PC3801

PC3806
240KR3-GP
3 6

SC10U25V5KX-GP
K
1

1
PR3816 G D

PR3809
6 4 5
7 PD3801 PC3802
8 3K3R6J-GP P6SBMJ24APT-GP SCD1U50V3KX-GP FDMC6675BZ-GP

2
9 1 AFTP3803 83.P6SBM.AAG 84.06675.030

2
2nd = 83.22R03.03G 2nd = 84.07121.037

A
DC-JACK255-GP
22.10261.401 PQ3809_D Id=-9.6A
PQ3805
Qg=-25nC
1

1
R2
X02_0615 PQ3804 E

D
PR3814 C AD_OFF_L B PR3810 Rdson=18~30mohm
100KR2J-1-GP R1 R1
PQ3809 B C AD_OFF_R 47KR3J-L-GP
DY E
G R2 PDTA124EU-1-GP
2

2
2N7002BK-GP PDTC124EU-1-GP 84.00124.K1K
84.07002.I31 84.00124.H1K 2nd = 84.05124.A11
2nd = 84.05124.011
S

PQ3810
G AC_IN#_G
27 PW R_CHG_AD_OFF
B B
27 AC_IN_KBC# D

S
DY
2N7002K-2-GP
1

84.2N702.J31
PR3815
100KR2J-1-GP
DY
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

DCIN Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 38 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Support A00_0806

EG3915
1 2

GAP-CLOSE-PW R-3-GP
Vinafix.com
EG3914
1 2

D GAP-CLOSE-PW R-3-GP D
EG3910
1 2

GAP-CLOSE-PW R-3-GP
EG3911
1 2

GAP-CLOSE-PW R-3-GP
EG3912
1 2
BT+ GAP-CLOSE-PW R-3-GP BT+_G
EG3913
1 2 BT+_G
Batt CONN

K
1
GAP-CLOSE-PW R-3-GP
C3901 PD3903
SC2200P50V2KX-2GP DY 1SMA18AT3G-GP

2
BATT1

A
11
9
8
R3902 1 2100R2J-2-GP PBAT_SMBCLK1 7
27,40 BAT_SCL
R3903 1 2100R2J-2-GP PBAT_SMBDAT1 6
27,40 BAT_SDA
R3904 1 2100R2J-2-GP PBAT_PRES1# 5
27 BAT_IN#
X01_0330 SYS_PRES1# 4
3
Avoiding MB crack on assembling 2

1
C EC3902 C
1 2 SYS_PRES1# EC3901 SC10P50V2JN-4GP 1
DY SC10P50V2JN-4GP DY DY 10

2
R3901 SYS_PRES1#
0R2J-2-GP SYN-CON9-24-GP
20.81755.009
2nd = 20.81771.009
NP2

NP1
6
3

1
4
7

BATSW 1 AFTP3902 1 PBAT_PRES1#

SW -SLIDE77-GP AFTP3903 1 PBAT_SMBDAT1
62.40068.021 AFTP3904 1 PBAT_SMBCLK1
2nd = 62.40018.641 AFTP3905 1 BT+_G

BAT_SCL
BAT_IN#

BAT_SDA

3
B B
3

D3901
D3902 D3903 BAV99-5-GP-U
BAV99-5-GP-U BAV99-5-GP-U
DY
DY DY
1

2
83.00099.T11
1

83.00099.T11 83.00099.T11 2nd = 83.00099.K11

2nd = 83.00099.K11 2nd = 83.00099.K11 3rd = 83.BAV99.D11
3rd = 83.BAV99.D11 3rd = 83.BAV99.D11

3D3V_AUX_KBC

Layout Note:
Place near Battery CONN

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

BATT CONN
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 39 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = Charger

Id= -10A Id=-8.6A

Qg= -22nC AD+_TO_SYS
Qg=-65nC
AD+ Rdson=14~13mohm DCBATOUT Rdson=15~18mohm BT+

Vinafix.com
PU4004 PR4002 PU4006
8 D S 1 1 2 1 S D 8

1
7 D S 2 2 S D 7
D S S D

PR4003

GAP-CLOSE-PWR-3-GP
6 3 D01R3721F-GP-U AD+ 3 6

100KR2J-1-GP
5 D G 4 4 G D 5

1
PG4002
1
D D

2
FDMC6675BZ-GP PG4003 FDMC6675BZ-GP

2
PR4004 84.06675.030 AD+_G_2 GAP-CLOSE-PWR-3-GP 84.06675.030

1
PWR_CHG_REGN 3KR5J-GP
2nd = 84.07121.037 2nd = 84.07121.037

2
2

2
PR4025

10KR2F-2-GP
PR4006

PR4001
470KR2J-2-GP

1
5,27 H_PROCHOT# 0R2J-2-GP

1
2 1
DY

DC_IN_D
X02_0615

2
X02_0615 PR4032

1
100KR2J-1-GP 1 2
D

AD+_G_1
PQ4005 PQ4002
2 3 D S 4 PC4002
SCD1U25V2KX-GP

SC1U25V3KX-1-GP
G PWR_CHG_CMPOUT PWR_CHG_ACOK 2 G G 5

PC4003
1 6 X01_0427

1
S D
PC4004 X02_0704
2

2N7002BK-GP AD+ 2N7002BKS-GP-U SCD1U25V3KX-GP PC4024 BT+_G

DY
S

SC10U25V5KX-GP

SC10U25V5KX-GP
84.07002.I31 PR4015 84.2N702.E3F SCD1U25V3KX-GP

SC10U25V5KX-GP
2

PC4008

PC4009
PWR_CHG_ACN
PWR_CHG_ACP
120KR2J-L-GP

PC4006
1

EC4001

EC4002
SCD1U25V2KX-GP

SCD1U25V2KX-GP
1

1
PC4019
1

9
CHG_AGND SCD1U50V3KX-GP

2
PR4010 CHG_AGND
1

CHG_AGND PD4001

G1

D1

D1

D1

D1
SCD47U25V3KX-1GP

2
PR4007 1 2 PWR_CHG_VCC PR4009 SD103AWS-1-GP PU4002
0R3J-0-U-GP FDMC7200S-GP

Q1
316KR2F-GP
2CHG_PHASE

PC4010
1 K A 1 2 84.07200.A37

1
10R5J-GP PC4007

Q2
2nd = 84.05524.037

SCD047U25V2KX-GP
2

10 D2/S1
2

1
PU4001 SC1U25V3KX-1-GP

PC4011

8 G2

7 S2

6 S2

5 S2
83.1R504.A8F

ACP

ACN
2

1
PWR_CHG_IOUT 20 2nd = 83.1R504.B8F

1
VCC
3D3V_AUX_KBC CHG_AGND
PR4011

2
19K1R2F-GP PWR_CHG_ACDET PWR_CHG_BTST
PR4031

6 17
SCD01U50V2KX-1GP
1

ACDET BTST
Charger Current=1.25A
1

PC4012

PWR_CHG_CMPOUT 16 PWR_CHG_REGN

1
REGN
49K9R2F-L-GP

1
PR4021 PR4020 PR4014 3
2

PR4013 3K3R2F-2-GP 3K3R2F-2-GP 3D3MR2J-GP CMPOUT PWR_CHG_HIDRV PR4033 BT+

18
49K9R2F-L-GP HIDRV D01R3721F-GP-U
1 2
C DY DY 4
PL4001
C
DY
2

2
CMPIN PWR_CHG_PHASE PC4013 BT+_R
19 1 2 1 2
2

2
PWR_CHG_CMPIN PHASE SC3300P50V3KX-1GP
3D3V_AUX_KBC

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
IND-2D2UH-161-GP-U 64.R0105.7FL
CHG_AGND 2 1 PWR_CHG_BAT_SCL 9 15 PWR_CHG_LODRV 68.2R210.20T

PC4025

PC4016

PC4017
2

1
CHG_AGND PG4007 GAP-CLOSE-PWR-3-GP SCL LODRV
27,39 BAT_SCL 2nd = 68.2R21D.10Y
1

PG4009

PG4012
SCD1U25V2KX-GP
PR4017 2 1 PWR_CHG_BAT_SDA 8 X01_0427

2
27,39 BAT_SDA SDA
100KR2J-1-GP PG4008 GAP-CLOSE-PWR-3-GP

1
PC4020
PR4019
13 PWR_CHG_SRP 1 2 10R2F-L-GP
2

PWR_CHG_ILIM SRP
10

1
ILIM PWR_CHG_SRN
12 1 2
1

PR4023 SRN PR4012 7D5R2F-GP

3D3V_AUX_KBC 2 1 PWR_CHG_IFAULT
11 DY
27 BOOST_MODE# DY

2
32K4R2F-1-GP NC#11
DY X02_0611
PR4018
1

0R2J-2-GP
2

PR4022
2

DY PR4026 CHG_AGND
10KR2F-2-GP

PQ4001 100KR2J-1-GP PWR_CHG_IOUT

5 7 1 2

SCD1U25V2KX-GP
PR4035
D

2N7002A-7-GP ACOK# IOUT AD_IA 27

PWR_CHG_CSOP_1
DY

GND

GND
CHG_AGND 0R0402-PAD-2-GP

SC220P50V2JN-3GP
2

PC4021
DY 3D3V_AUX_KBC
1

G PWR_CHG_CMPOUT BQ24727RGRR-GP

8K45R2F-2-GP
1 PR4024
21

14
74.24727.073 A00_0806

1
1 PC4022
PG4011
S

1 2

2
GAP-CLOSE-PWR-3-GP PWR_CHG_CSON_1

SCD1U25V2KX-GP
3D3V_AUX_S5 CHG_AGND
CHG_AGND DY

2
CHG_AGND
1

PC4023
2

1
PR4027
100KR2J-1-GP
3D3V_AUX_S5

2
PWR_CHG_REGN
2

1 CHG_AGND
1

27 AC_IN# CHG_AGND
PR4039 PR4028
100KR2J-1-GP 100KR2J-1-GP
B DY B
2
2

PWR_CHG_ACOK
1

X02_0615
PR4036
D

120KR2F-L-GP PQ4006
DY
2

G AC_IN#

2N7002BK-GP
84.07002.I31
S

X02_0615

EC Code only BQ24707A

PR4030
54K9R2F-L-GP PQ4004
H_PROCHOT# AD_IA_HW AD_IA_HW2 PWR_CHG_CMPIN 1 2 PQ4904_3 3 4
D S CHG_AGND
2 5
65W 0 0 27 AD_IA_HW2 G G AD_IA_HW 27
1 S D 6 PQ4004_6 2 1 PWR_CHG_CMPIN

90W 1 0 2N7002BKS-GP-U PR4038

84.2N702.E3F 19K6R2F-GP
A
130W 0 1 CHG_AGND
A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CHARGER BQ24707A
Size Document Number Rev
A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 40 of 106
5 4 3 2 1
 A B C D E

SSID = PWR.Plane.Regulator_5v3p3v

PWR_5V3D3V_VCLK
A00_0806
3D3V_AUX_S5 PC4104 PC4102 PC4103
DCBATOUT PWR_DCBATOUT_5V DCBATOUT PWR_DCBATOUT_3D3V

1
SC1KP50V2KX-1GP

SCD1U25V3KX-GP

SCD1U25V3KX-GP
1

1
PG4102 PG4137

2
Vinafix.com
1 2 1 2

2
PR4132 PD4102

3PC4102_2 2

3PC4103_2 2
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 0R2J-2-GP BAT54-7-F-GP
PG4103 PG4138 DY
1 2 1 2
DY

2
4 X02_0611 4

3
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PG4104 PG4139 PR4131
PR4127
1 2 1 2 0R2J-2-GP PD4103 PD4101
PWR_5V_EN1 2 1 PWR_5V_EN1_R 2 1 BAT54S-7F-GP BAT54S-7F-GP
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP DY 83.00054.Y81 83.00054.Y81
PG4106 PG4140 0R0402-PAD-2-GP 2nd = 83.0R203.081 2nd = 83.0R203.081

1
1 2 1 2

1
PR4133 15V_S5 15V_PWR 5V_PWR
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 0R0402-PAD-2-GP PG4105
PG4107 PG4141 GAP-CLOSE-PWR-3-GP
1 2 1 2

2
PR4130
1 2 PC4108_1
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP PWR_3D3V_EN2 2 1
PG4135 PG4142 3V_5V_EN 36

1
1 2 1 2 0R0402-PAD-2-GP PC4106
PD4104 SC1U25V3KX-1-GP PC4108 PC4107
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP BZT52C15S-GP SCD1U25V3KX-GP SCD1U25V3KX-GP
83.15R03.C3F DY

2
PG4115 PG4144
1 2 1 2 2nd = 83.15R03.E3F

A
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PG4118
1 2

GAP-CLOSE-PWR-3-GP RF
PG4136 DCBATOUT
1 2 PWR_DCBATOUT_3D3V
PC4112 PC4113

SC10U25V5KX-GP

SCD01U50V2KX-1GP
GAP-CLOSE-PWR-3-GP PWR_DCBATOUT_5V

2
PC4109 PC4110 PC4111 PU4102

EC4101

EC4102

EC4103

EC4104
FDMS3600-02-RJK0215-COLAY-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP
1

1
SC10U25V5KX-GP

SCD1U50V3KX-GP

SC10U25V5KX-GP

DY 84.03664.037 2

1
2nd = 84.06920.037 3 PC4129 PC4130 PC4114 PC4115 PC4116

2
D 1 4
2

8
7
6
5

1
SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U50V3KX-GP
10
D
D
D
D
PU4105 9
FDMC8884-GP-U

12
7

2
84.08884.A37 PU4101 8 6
2nd = 84.00412.037 5 Design Current = 16A

VIN
Design Current = 7.64A 4
G

PR4108 PR4109 SCD1U25V3KX-GP 25.1A<OCP< 29.3A

S
S
S

3 3
12.1A<OCP< 14.2A PC4117 1D5R3F-GP 1D5R3F-GP PC4118
1
2
3

S G 2 1PWR_3D3V_VBST2_1 1 2 PWR_3D3V_VBST2
9 17 PWR_5V_VBST1 1 2PWR_5V_VBST1_1 1 2
SCD1U25V3KX-GP VBST2 VBST1
3D3V_PWR PWR_3D3V_DRVH2 10 16 PWR_5V_DRVH1 5V_PWR
PL4102 DRVH2 DRVH1 PL4101 RF
RF 2 1 PWR_3D3V_LL2 8
SW2 SW1
18 PWR_5V_LL1 1 2
IND-2D2UH-46-GP-U IND-1D5UH-34-GP
1

68.2R210.20B PWR_3D3V_DRVL211 15 PWR_5V_DRVL1 68.1R510.10J

1
DRVL2 DRVL1
2nd = 68.2R21B.10J 2nd = 68.1R51A.10E
PR4110 PR4111
DY
D 8
D 7
D 6
D 5

PG4116 2D2R5F-2-GP 14 PWR_5V_VO1

DY 2D2R5F-2-GP PG4117 PC4120 PT4103 PT4104 EC4105 EC4106 EC4107 EC4108
1

1
EC4112 EC4111 EC4110 EC4109 PT4101 PU4106 VO1
2
1

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

SCD1U10V2KX-4GP

ST220U6D3VDM-20GP

ST220U6D3VDM-20GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
EC4119 FDMC7696-GP PWR_3D3V_FB2 4 2 PWR_5V_FB1
DY

2
VFB2 VFB1
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

ST220U6D3VDM-20GP

84.07696.037
1PWR_3D3V_SNUB

DY DY DY DY

2
2nd = 84.00780.037
2

2
4
G

1PWR_5V_SNUB
PWR_3D3V_EN2 PWR_5V_EN1
S
S
S
S

6 20
EN2 EN1
1
2
3

A00_0806
PWR_3D3V_CS2 5 1 PWR_5V_CS1
CS2 CS1
1

1
PR4103 5V_PWR 5V_S5
PR4102 19 PWR_5V3D3V_VCLK 77.22271.27L 77.22271.27L PG4119
X01_0417 EC4119=PC4119 77.22271.27L PC4121 DY X01_0424 100KR2F-L2-GP VCLK
X01_0424 35K7R2F-L-GP PC4123 2nd = 79.22710.20L 2nd = 79.22710.20L X02_0615 1 2
DY
3D3V_TER

X02_0615 2nd = 79.22710.20L SC330P50V3KX-GP SC560P50V-GP

2
A00_0724 7 21 GAP-CLOSE-PWR-3-GP
2

2
PGOOD GND PG4120
A00_0724

VREG3

VREG5
1 2

GAP-CLOSE-PWR-3-GP
1

1
TPS51225RUKR-GP PG4121
3

13
PR4113 74.51225.073 5V_PWR_2 PR4114 X00_1104 1 2

1
PR4112 0R2J-2-GP 3D3V_PWR_2 0R2J-2-GP
DY DY
PWR_5V3D3V_VREG3

6K65R2F-GP PG4101 PR4121 GAP-CLOSE-PWR-3-GP

1 2 15KR2F-GP PG4122
2

1 2

1 2
PWR_3D3V_FB2_R PWR_5V_FB1_R 1 2
PC4124 GAP-CLOSE-PWR-3-GP

2
SC18P50V2JN-1-GP PC4125 GAP-CLOSE-PWR-3-GP
DY SC18P50V2JN-1-GP DY PG4123
2

2
A00_0806 1 2
SC1U10V2KX-1GP

2 2
PC4126
1

1
GAP-CLOSE-PWR-3-GP
1

3D3V_S5 3D3V_PWR PR4117 PR4115 PG4124

1

PG4108 10KR2F-2-GP PC4127 10KR2F-2-GP

DY PC4128 1 2
SC22U6D3V5MX-2GP

1 2 3D3V_PWR_2 3D3V_AUX_S5
SC4D7U6D3V3KX-GP

3D3V_S5 GAP-CLOSE-PWR-3-GP
2

2
PR4116
GAP-CLOSE-PWR-3-GP PG4125
PG4109 2 1 1 2
1

1 2
PR4119 0R0402-PAD-2-GP GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP 100KR2J-1-GP PG4126
PG4110 1 2
1 2 X02_0611
2

PWR_5V3D3V_PGOOD GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PG4127
PG4111 1 2
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PG4128
PG4112 1 2
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PG4129
PG4113 1 2
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PG4130
PG4114 1 2
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PG4131
PG4143 1 2
1 2
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP PG4132
1 2

GAP-CLOSE-PWR-3-GP
PG4133
1 2
1 GAP-CLOSE-PWR-3-GP 1
PG4134
1 2

GAP-CLOSE-PWR-3-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51123_5V/3D3V
Size Document Number Rev
A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 41 of 106
A B C D E
 5 4 3 2 1

SSID = CPU.Regulator
VCCP_CPU

1 2 Volterra's suggestion:
8 VR_SVID_ALERT# PR4224 DY 75R2F-2-GP
8 H_CPU_SVIDDAT
H_CPU_SVIDDAT 1 2 VCC 26x22uF(0805) 1-PHASE VCC
PR4225 130R2F-1-GP
8 H_CPU_SVIDCLK
H_CPU_SVIDCLK 1 2 boot voltage=0V VCCAXG 23x22uF(0805) for 1-PHASE VCCAXG
PR4226 54D9R2F-L1-GP
48 D85V_PWRGD

PR4211
Vinafix.com

PR4201

PR4228

PR4205

PR4262

PR4209

PR4210
PR4204

PR4207

PR4208

1
1D8V_S0 3D3V_S5

1
825R2F-GP
5V_S5

21D5R2F-1-GP

20KR2F-L-GP

402R2F-GP
D X01_0417 D

825R2F-GP

61K9R2F-GP

280R2F-1-GP

191R2F-GP
1

0R0402-PAD-2-GP

0R0402-PAD-2-GP
PR4231

2
1
PC4211 10R2F-L-GP

2
PR4260 SC1U10V2KX-1GP

PWR_VCORE_VR_ENABLE
866KR2F-GP 78.10523.5FL

X02_0611
PWR_VCORE_R_OSC

PWR_VCORE_R_SEL0

PWR_VCORE_R_SEL1
2

PWR_VCORE_R_SEL6
PWR_VCORE_VR_READY2
PWR_VCORE_VR_READY1
PWR_VCORE_VR_TT#
PWR_VCORE_R_SEL4
1 2
PWR_VCORE_VIN_UVLO_R

X02_0611
PC4237 SCD1U16V2KX-3GP

1
X02_0615

1
PR4263
100KR2F-L1-GP PC4214

SCD1U16V2KX-3GP
GND_1318

2
X02_0611

2
PR4223
1 2
GND_1318
0R0402-PAD-2-GP

49

48
47
46
45
44
43
42
41
40
39
38
37
PU4201
X02_0615

R_SEL6
VR_READY2
VR_READY1
VR_TT#
R_SEL4
ALERT#
VDIO
VCLK
VR_ENABLE

R_SEL0
R_SEL1
GND

R_OSC
1D8V_S0

PWR_VCORE_VDD3 1 36 PWR_VCORE_R_SEL2
VDD3 R_SEL2 PWR_VCORE_R_SEL3
2 35
VDD R_SEL3 PWR_VCORE_R_REF
3 34
PWR_VCORE_VIN_UVLO VDD R_REF
4 33
PWR_VCORE__PWM3 VIN_UVLO IPH2_2 PWR_VCORE_R_SEL5
5 32 PWR_AXG_IPH2_1_R 44
PWR_VCORE__PWM2 PWM1_3 R_SEL5 PWR_AXG_PWM2_2
6 31
PWR_VCORE__PWM1 PWM1_2 PWM2_2 PWR_AXG_PWM2_1 PR4229
7 30
43 PWR_VCORE__PWM1 PWR_VCORE__TP_FAULT#1 PWM1_1 PWM2_1 PWR_AXG_TS_FAULT#2 PWR_AXG_PWM2_1 44 1K96R2F-1-GP
8 29
43 PWR_VCORE__TP_FAULT#1 TS_FAULT#1 TS_FAULT#2 PWR_AXG_IPH2_1 PWR_AXG_TS_FAULT#2 44
9 28 1 2 1 2
IPH1_3 IPH2_1 PWR_AXG_MRAMP2 PR4246
10 27
PWR_VCORE_IPH1_1 IPH1_2 MRAMP2
1 2 1 2 11 26 X02_0611

1
IPH1_1 SENSE2+ 1KR2F-3-GP

PR4257

PC4201
PC4229 PWR_VCORE_MRAMP1

SENSE1+
12 25

A2_OUT1

A3_OUT1
A3_OUT2

A2_OUT2
SENSE1-
MRAMP1 SENSE2-

A_ERR1

A_ERR2
PR4261

PR4219
PR4256 PR4216 PR4218 PR4212

A2_IN1

A3_IN1

A3_IN2

A2_IN2
DY

1
750R2F-GP 1K96R2F-1-GP PR4215 0R2J-2-GP 0R0402-PAD-2-GP
DY

2
1

1
SC10P50V2JN-4GP

C PR4258 C

13KR2F-GP

15K4R2F-GP

SC10P50V2JN-4GP
0R2J-2-GP
DY DY

2
43 PWR_VCORE_IPH1_1_L

0R0402-PAD-2-GP

0R0402-PAD-2-GP
VT1318MFQX-2-GP
2

13
14
15
16
17
18
19
20
21
22
23
24
74.01318.B73

PWR_VCORE_A_ERR1
PWR_VCORE_A2_IN1
PWR_VCORE_A2_OUT1
PWR_VCORE_A3_IN1
PWR_VCORE_A3_OUT1
PWR_AXG_A3_OUT2
PWR_AXG_A3_IN2
PWR_AXG_A2_OUT2
PWR_AXG_A2_IN2
PWR_AXG_A_ERR2
PC4231
SC22P50V2JN-4GP PC4236 GND_1318
SC47P50V2JN-3GP X02_0611
2 1 1 2
X02_0611 PR4252
X02_0626 GND_1318 0R0402-PAD-2-GP
PC4232 PR4234 PWR_AXG_SENSE2_P 2 1 VCC_AXG_SENSE 9
2 1 VCORE_IN1_R0 2 1 1 2 VCORE_IN1_L0 1 2
DY DY PR4235 PWR_AXG_SENSE2_N 2 1 VSS_AXG_SENSE 9
SC22P50V2JN-4GP 6K81R2F-1-GP PC4238 15KR2F-GP X02_0611 PR4254
SC680P50V3JN-GP 0R0402-PAD-2-GP
PR4251
1 2 1 2VCORE_IN1_R1 1 2 2 1 8 VCCSENSE 1 2 PWR_VCORE_SENSE_P
PR4237 PR4264
487R2F-GP PR4236 PR4233 0R0402-PAD-2-GP PC4235 SC22P50V2JN-4GP PC4233 SC22P50V2JN-4GP
866R2F-GP 7K5R2F-1-GP 10KR2F-2-GP
X02_0626 1 2 1 2
PR4250
0R0402-PAD-2-GP X02_0626
1 2 PWR_VCORE_SENSE_N
8 VSSSENSE
PC4218 PR4244 PC4234
1 2 AXG_IN2_L1 1 2 1 2 AXG_IN2_R0 1 2 1 2
DY DY
PR4255 SC1K5P50V3JN-GP 6K81R2F-1-GP SC22P50V2JN-4GP PR4240
30K1R2F-L-GP 665R2F-2-GP

A00_0806 1 2 1 2AXG_IN2_R1 1 2 X01_0424

1 2VCORE_IPH1_R0 1 2 PR4245 10KR2F-2-GP PR4239
PG4201 PR4249 412R2F-GP
1 2 PR4238 PC4213 7K68R2F-GP
2K7R2F-GP SC3300P50V2KX-1GP
GAP-CLOSE-PWR-3-GP

GND_1318
B B

PR4243
1 2 AXG_IPH2_R0 1 2

PC4219 SCD01U50V2KX-1GP 3K24R2F-GP

X02_0611 X02_0615
3D3V_S0
VCC_CORE
PR4202 PR4253
1 2 PWR_VCORE_MRAMP1 1 2 PWR_VCORE_VR_READY1 2 1
PR4222 IMVP_PWRGD 27,36
10KR2F-2-GP 0R0402-PAD-2-GP
43KR2F-GP
PR4203
1 2 PWR_VCORE_VR_READY2

10KR2F-2-GP
VCC_GFXCORE

1 2 PWR_AXG_MRAMP2
PR4227 X00_1026
56K2R2F-2-GP

VCCP_CPU

PR4206
1 2 PWR_VCORE_VR_TT#

62R2J-GP
1

PC4202
SC47P50V2JN-3GP
2

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VT1318+1323_CPU_CORE1+1(1/3)
Size Document Number Rev
A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 42 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = CPU.Regulator A00_0806

PW R_CPU_CORE 5V_S5

EG4301
2 1

GAP-CLOSE-PW R-3-GP
Vinafix.com 2
EG4302
1

D GAP-CLOSE-PW R-3-GP D
EG4303
2 1

GAP-CLOSE-PW R-3-GP
EG4304
2 1

GAP-CLOSE-PW R-3-GP
EG4305 PW R_CPU_CORE
2 1 Small caps close to slave for placement
GAP-CLOSE-PW R-3-GP
EG4306
2 1

PC4304

PC4305

PC4306

PC4307

PC4308

PC4309
SC1U10V2KX-1GP

SC1U10V2KX-1GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
GAP-CLOSE-PW R-3-GP

1
EG4307
2 1 PC4310
SCD1U16V2KX-3GP

2
1D8V_S0 GAP-CLOSE-PW R-3-GP
X02_0615

C1

C2

C3

C4
PU4301
1

PC4302
Design Current = 25A

VDDH

VDDH

VDDH

VDDH
SC4D7U10V3KX-GP A1 B4 PW R_CORE_BT1
42 PW R_VCORE__TP_FAULT#1 TS_FAULT# BST
C
Peak Current = 33A C
2

1
A4 VCC
D1 PC4301
VX#D1 SCD22U10V3KX-2GP
D2

2
VX#D2
VX#D3 D3 PL4301
PW R_VCORE_PU4301_VDD B1 D4 VCC_CORE
VDD VX#D4
VX#F1 F1
F2 PW R_CORE_VX1 1 2
VX#F2 IND-D1UH-26-GP
VX#F3 F3
42 PW R_VCORE_IPH1_1_L B2 ISENSE VX#F4 F4 68.R1010.10T
VX#H1 H1 2nd = 68.R1010.10X

1
1D8V_S0 B3 H2 PR4303
42 PW R_VCORE__PW M1 PWM VX#H2
VX#H3 H3

100R5F-2-GP
H4
VX#H4
K1 DY
VX#K1
PR4301 K2

2
PC4303 VX#K2
VX#K3 K3
1 2 1 2 A2 GND VX#K4 K4

SCD1U25V2KX-GP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
10R2F-L-GP

VT1326SFCX-1-GP
E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
L1
L2
L3
L4
74.01326.A7Z

B B

A00_0806

PG4301
1 2

GAP-CLOSE-PW R-3-GP

GND_1323S_1

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VT1318+1326_CPU_CORE2+1(2/3)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 43 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = CPU.Regulator
A00_0806
PW R_CPU_GFX 5V_S5

EG4401
Vinafix.com 2 1

GAP-CLOSE-PW R-3-GP
D EG4402 D
2 1

GAP-CLOSE-PW R-3-GP
EG4403
2 1

GAP-CLOSE-PW R-3-GP
EG4404
2 1

GAP-CLOSE-PW R-3-GP
EG4405 PW R_CPU_GFX
2 1

GAP-CLOSE-PW R-3-GP
Small caps close to slave for placement
EG4406
2 1

PC4403

PC4404

PC4405

PC4406

PC4407
SC1U10V2KX-1GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
GAP-CLOSE-PW R-3-GP

1
EG4407
2 1 PC4408
SCD1U16V2KX-3GP

2
1D8V_S0 GAP-CLOSE-PW R-3-GP
X02_0615

C1

C2

C3

C4
C PU4401 C
1

PC4401
Design Current = 22A

VDDH

VDDH

VDDH

VDDH
SC4D7U10V3KX-GP A1 B4 PW R_AXG_BT3
42 PW R_AXG_TS_FAULT#2 TS_FAULT# BST
Peak Current = 33A
2

1
A4 VCC
H4 PC4409
VX#H4 SCD22U10V3KX-2GP
H3

2
VX#H3 VCC_GFXCORE
VX#H2 H2 PL4401
PW R_AXG_PU4401_VDD B1 H1
VDD VX#H1
VX#F4 F4
F3 PW R_AVG_VX1 1 2
VX#F3 IND-D1UH-26-GP
VX#F2 F2
42 PW R_AXG_IPH2_1_R B2 ISENSE VX#F1 F1 68.R1010.10T
VX#D4 D4 2nd = 68.R1010.10X

1
1D8V_S0 B3 D3 PR4402
42 PW R_AXG_PW M2_1 PWM VX#D3
VX#D2 D2

100R5F-2-GP
D1
PR4401
VX#D1 DY
PC4402

2
1 2 1 2 A2 GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCD1U25V2KX-GP
10R2F-L-GP
VT1323SFCX-1-GP

E1
E2
E3
E4
G1
G2
G3
G4
J1
J2
J3
J4
74.01323.A7Z

PG4401
B B

1 2

GAP-CLOSE-PW R-3-GP

GND_1323S_3 A00_0806

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VT1318+1323_CPU_CORE1+1(3/3)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 44 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p05v
140mils or Copper Shape
3D3V_S0
A00_0806

5V_S5 +PW R_SRC_1D05V

A00_0806

2
1D05VTT_PW R VCCP_CPU 1D05VTT_PW R VCCP_CPU
EG4527
1 2
Vinafix.com PR4518
10KR2J-3-GP X02_0611 PG4506 PG4513
1 2 1 2
D GAP-CLOSE-PW R-3-GP A00_0806 D
PR4523

1
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PW R_1D05V_STAT 2 1 1D05V_VTT_PW RGD 37,48 PG4507 PG4508
1 2 1 2
0R0402-PAD-2-GP

2
EG4528 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
1 2 DY PC4531 PG4510 PG4509
SC2200P50V2KX-2GP 1 2 1 2

1
GAP-CLOSE-PW R-3-GP
EG4525 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
1 2 +PW R_SRC_1D05V PG4512 PG4514
1 2 1 2
GAP-CLOSE-PW R-3-GP
EG4522 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
1 2 PG4516 PG4515

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
PC4508

PC4507

PC4514
1 2 1 2

SC4D7U10V3KX-GP

SCD1U16V2KX-3GP
GAP-CLOSE-PW R-3-GP

1
GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP

PC4515
PG4519 PG4511
DY 1 2 1 2

2
X01_0418 GAP-CLOSE-PW R-3-GP GAP-CLOSE-PW R-3-GP
PG4517
1 2

X02_0615 Design Current = 10.67A GAP-CLOSE-PW R-3-GP

PU4501 PG4518
16.77A<OCP< 19.82A 1 2
B5 VDD VX#B2 B2
C C5 B3 GAP-CLOSE-PW R-3-GP C
Diff pair VDD VX#B3
B4 1D05VTT_PW R PG4520
VX#B4 PL4501 400mils or Copper Shape 1 2
PW R_1D05V_VSENSE+ A2 C2
PW R_1D05V_VSENSE- SENSE+ VX#C2 PW R_1D05V_VX GAP-CLOSE-PW R-3-GP
1 2 2 1 A3 SENSE- VX#C3 C3 1 2
PR4506 C4 COIL-D2UH-2-GP
2K74R2F-GP PR4507 VX#C4
68.R2010.20B

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
6K81R2F-1-GP PW R_1D05V_STAT

PC4519

PC4528
A4 2nd = 68.R2010.10Q

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
STAT

PC4518

PC4521

PC4530

PC4529
X02_0611 A1

SCD1U16V2KX-3GP
AGND

1
2 1 PU4501_OE A5
19,46,47,93 RUNPW ROK OE

2
PR4522

PC4522
B1
GND DY

EC4501
SCD1U10V2KX-5GP

EC4502
SCD1U10V2KX-5GP

EC4503
SCD1U10V2KX-5GP
0R0402-PAD-2-GP C1 AGND_1D05V_385
DY DY DY

2
GND
DY

1
VT386FCX-ADJ-GP
1
PC4539

74.00386.03Z
SCD1U10V2KX-4GP

DY

1
PR4515
2

150R2F-1-GP PR4501 X02_0615

1 2
DY 1 2 25K5R2F-GP RF
VCCIO_SENSE_1

PC4502

2
SC3300P50V2KX-1GP

1 2
A00_0806 VCCP_CPU
PC4501
SC4700P50V2KX-1GP
PG4505

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
B B

PC4525

PC4520

PC4526

PC4527
1 2

SC22U6D3V5MX-2GP
PC4523

PC4509

PC4510

PC4512

PC4513

PC4516

PC4517
PC4511
X02_0615

SCD1U16V2KX-3GP

1
GAP-CLOSE-PW R-3-GP

1
1

1
DY

PC4506
AGND_1D05V_385 DY DY DY

2
2

2
2

2
22u Cap x 18
0.1 u Cap x 2
close output MLCC
VCCIO_SENSE_C PR4510 2 1 0R0402-PAD-2-GP VCCIO_SENSE 8

PR4511 2 1 0R0402-PAD-2-GP VSSIO_SENSE 8

X02_0611
close output MLCC

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

1D05V_PCH & VCCP_CPU

Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 45 of 106
5 4 3 2 1
 5 4 3 2 1
PU4602
Main source FDMS3604 (84.00033.037)
SSID = PWR.Plane.Regulator_1p5v0p75v +PW R_SRC_1D5V

PC4614
SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SCD1U50V3KX-GP

SC4D7U25V5KX-GP
PC4613
DCBATOUT +PW R_SRC_1D5V 1D5V_PW R 1D5V_S3

1
PC4609

PC4611

PC4612
Vinafix.com PG4603
1 2
PG4608

2
GAP-CLOSE-PW R-3-GP 1 2
D PG4604 D
1 2 GAP-CLOSE-PW R-3-GP
PG4609
GAP-CLOSE-PW R-3-GP 1 2
PG4605
1 2 GAP-CLOSE-PW R-3-GP
PG4610
GAP-CLOSE-PW R-3-GP 1 2
PG4606
5V_S5 1 2 GAP-CLOSE-PW R-3-GP
PG4611
GAP-CLOSE-PW R-3-GP 1 2
PG4625
1 2 GAP-CLOSE-PW R-3-GP
3D3V_S0 PG4612

1
PC4601 GAP-CLOSE-PW R-3-GP 1 2

5
6
7
8
SC1U16V3KX-5GP

D
D
D
D
PU4602
GAP-CLOSE-PW R-3-GP

2
FDMS7698-GP
1

PG4613
PR4604 X02_0615 84.07698.037 1 2
20KR2J-L2-GP 2ND = 84.00172.037

G
4 GAP-CLOSE-PW R-3-GP

S
S
S
PU4601 PG4614

PR4605_2
2

X02_0626 Design Current = 16.04A

3
2
1
19,45,47,93 RUNPW ROK 20 PGOOD V5IN 12 1 2

17 PR4605 PC4619 25.2A<OCP< 29.8A GAP-CLOSE-PW R-3-GP

37 0D75V_EN VTTEN PW R_1D5V_VBST1 1 2
15 2 PG4615
PW R_1D5V_EN VBST 2D2R3J-2-GP
16 EN/PSV SCD1U25V3KX-GP 1D5V_PW R 1 2
C
PW R_1D5V_VREF 6 PW R_1D5V_DRVH PL4601 C
VREF DRVH 14 RF GAP-CLOSE-PW R-3-GP
1

PG4616
PR4603 PW R_1D5V_SW 1 2 1 2
10KR2F-2-GP 13
SW COIL-1UH-51-GP-U
GAP-CLOSE-PW R-3-GP
PW R_1D5V_DRVL
68.1R01C.10Q

SC4D7U25V5KX-GP

SCD1U16V2KX-3GP
PG4617

2
EC4602
SCD1U16V2KX-3GP

EC4603
SCD1U16V2KX-3GP
2

PT4603

PC4620

PC4621
PW R_1D5V_REFIN 8 11 2ND = 68.2R25B.10M 1 2

5
6
7
8

1
2ND = 77.24771.13L
79.47719.2BL
SE470UF2VDM-GP

EC4604
SCD1U10V2KX-5GP
REFIN DRVL

SCD1U50V3KX-GP
DY

D
D
D
D
PU4603

PG4607
PR4612 GAP-CLOSE-PW R-3-GP

1
10
47KR2F-GP

DY
SCD1U16V2KX-3GP

SCD01U50V2KX-1GP

PGND FDMS0309AS-GP
1 PR4601 2

EC4601
PW R_1D5V_MODE 19 2D2R5F-2-GP PG4618

2
GAP-CLOSE-PWR-3-GP
MODE
1

84.00309.037
PC4603

1 2
200KR2F-L-GP

1
1

2ND = 84.00166.037
PC4602

G
1 PR4608 2

PW R_1D5V_TRIP 18 9 PW R_1D5V_VDDQS 4 GAP-CLOSE-PW R-3-GP

2

S
S
S
TRIP VDDQS TPS51216_PHS_SET PG4619
80K6R2F-GP

PWR_1D5V_VDDQS
2

PR4602
PR4601_1

3
2
1
VTTIN 2 1 2

1
+0D75V_DDR_P X02_0615
5K1R2F-2-GP

PW R_1D5V_VTTREF5
VTTREF
1

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
3 PC4622 GAP-CLOSE-PW R-3-GP
DY
SCD1U16V2KX-3GP

VTT
1

PC4610 SC330P50V2KX-3GP
PR4606

PG4620

2
PC4616

PC4617
1

X02_0615 SCD22U6D3V2KX-1GP 1
PC4615

1 1 2
2

VTTS X01_0417
21 GND DY
2

4 GAP-CLOSE-PW R-3-GP
2

VTTGND
7 PG4621
GND
1 2
X02 1223 X01 1110 TPS51216RUKR-GP
GAP-CLOSE-PW R-3-GP
74.51216.073 1D5V_PW R
PG4622
X02_0615 1 2

1
B PC4604 GAP-CLOSE-PW R-3-GP B
SC1U16V3KX-5GP PG4623
1 2

2
X02_0615 GAP-CLOSE-PW R-3-GP
A00_0806 PG4624
1 2
+0D75V_DDR_P 0D75V_S0 GAP-CLOSE-PW R-3-GP
PG4601
2 1

GAP-CLOSE-PW R-3-GP
PG4602
2 1

GAP-CLOSE-PW R-3-GP
State S3 S5 VDDR VTTREF VTT PR4607
1 2 PW R_1D5V_EN
S0 Hi Hi On On On DDR_VREF_S3
19,27 PM_SLP_S4#
PR4611 0R0402-PAD-2-GP
S3 Lo Hi On On Off(Hi-Z)

1
PW R_1D5V_VTTREF 1 PC4606
2 SCD1U10V2KX-5GP
S4/S5 Lo Lo Off Off Off X02_0611 DY
0R0603-PAD

2
MODE X02 1229
PR4608 Frequency Discharge Mode <Variant Name>
A A
200k ohm 400kHz
Tracking Discharge Wistron Corporation
100k ohm 300kHz
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
68k ohm 300kHz I/P cap:10U 25V K0805 X5R/ 78.10622.51L Taipei Hsien 221, Taiwan, R.O.C.
Non-tracking Discharge Inductor: CHIP CHOKE 1.0UH PCMB104T-1R0M Cyntec 3mohm/3.3mohm Isat =28Arms68.1R01C.10Q
47k ohm 400kHz Title
O/P cap: CHIP CAP 470UF 2V EEFSX0D471X 6mOhm 3.5Arm/Panasonic/79.47719.2BL
H/S,L/S: FDMS3604S / 7.5mohm/9.8mOhm@4.5Vgs, 2.6mohm/3.2mOhm@4.5Vgs/ 84.03604.037
TPS51216_+1.5V_SUS
Size Document Number Rev
A3
Enrico Caruso 14 MLK DIS A00
Date: Tuesday, August 14, 2012 Sheet 46 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p8v

Vinafix.com
D D

RT8068A for 1D8V_S0

Design Current = 0.87A
X01_0424 X01_0502 1.29A<OCP< 1.52A
X01_0424
X01_0424 3D3V_S5 PU4701 1D8V_S0
PL4701
RF
9 GND LX#1 1
8 2 PW R_1D8V_PHASE 1 2
PR4701 PVIN#8 LX#2
7 PVIN#7 PGOOD 3
1 2 PW R_1D8V_SVIN 6 4 IND-1D5UH-116-GP PR4703
SVIN EN

1
2D2R2F-GP 5 68.1R550.20F 102KR2F-GP

SC22P50V2JN-4GP
1 FB

PC4705
PC4703
R1

2
EC4701
SCD1U16V2KX-3GP

EC4702
SCD1U16V2KX-3GP
SC1U6D3V2KX-GP RT8068AZSP-GP PC4706 PC4707
2

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

EC4703
SCD1U10V2KX-5GP
74.08068.041 DY

2
1

C PC4701 PC4702 C

1
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

DY PW R_1D8V_FB
2

1
X02_0611 PR4704
51KR2F-L-GP
R2
1 2 PW R_1D8V_EN

2
19,27,36,37 PM_SLP_S3# PR4702
0R0402-PAD-2-GP
1

PC4704
DY SC22P50V2GN-GP
2

19,45,46,93 RUNPW ROK

Vo=0.6*(1+(R1/R2))

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8068A_1D8V_S0
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 47 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_vccsa

VCCP_CPU
A00_0806 Vinafix.com
PG4812
D 2 1 PW R_VCCSA_VIN D

GAP-CLOSE-PW R-3-GP
PG4811
2 1

GAP-CLOSE-PW R-3-GP
PG4810
2 1

GAP-CLOSE-PW R-3-GP
PG4801
2 1

GAP-CLOSE-PW R-3-GP
PG4802
2 1

GAP-CLOSE-PW R-3-GP 5V_S5

PG4809
2 1

1
GAP-CLOSE-PW R-3-GP X02_0611
3D3V_S0 PR4801
0R0402-PAD-2-GP
Iomax=4A
PC4803 PC4802 OCP>9A

2
1

VCCSA=0.9V
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1 PW R_VCCSA_VCNTL A00_0724

1
C PR4802 PC4801 C
2

10KR2J-3-GP SC1U6D3V2KX-GP
2
PU4801 VCCSA_PW R A00_0806 0D85V_S0
2

PW R_VCCSA_VIN 5 PG4803
VIN#5
6 VCNTL VOUT#4 4 1 2
7 POK VOUT#3 3 R1

1
42 D85V_PW RGD 1 2 PW R_VCCSA_EN 8 2 GAP-CLOSE-PW R-3-GP
37,45 1D05V_VTT_PW RGD EN FB

1
PR4803 PW R_VCCSA_VIN 9 1 PR4804 PC4804 PG4804
0R0402-PAD-2-GP VIN#9 GND 10KR2F-2-GP 1 2
1

SC100P50V2JN-3GP
X02_0611 PC4805 PC4806

2
1

PR4808 APL5916KAI-TRG-GP GAP-CLOSE-PW R-3-GP

1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
47KR2F-GP
DY DY PC4809 74.05916.A31 PW R_VCCSA_FB
1
PG4805
2
2

SC1U6D3V2KX-GP
R2
2

2
1
GAP-CLOSE-PW R-3-GP

1
PR4806 PG4806
PR4805 160KR2F-GP DY 1 2
80K6R2F-GP
GAP-CLOSE-PW R-3-GP

2
PG4807

2
1 2

PWR_VCCSA_SEL1
GAP-CLOSE-PW R-3-GP
Vout=0.8*(1+R1/R2) PG4808
1 2

GAP-CLOSE-PW R-3-GP
B B
PQ4801
2N7002BK-GP

S
DY D

84.07002.I31
2nd = 84.2N702.W31

G
3rd = 84.2N702.J31

PR4807
PW R_VCCSA_SEL0 1 2
DY VCCSA_SEL1 9

10KR2J-3-GP

1
DY PC4807
SCD1U10V2KX-4GP

2
A TPAD14-OP-GP TP4801 1 DMB50 A
VCCSA_SEL0 9

Wistron Corporation
TPAD14-OP-GP TP4802 1 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VCCSA_SENSE 9 Taipei Hsien 221, Taiwan, R.O.C.

Title

APL5916_VCCSA
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 48 of 106
5 4 3 2 1
SSID = VIDEO LCD_TST_C 2
RN4901
3 LCD_TST 27
SSID = VIDEO
BLON_OUT_C 1 4 BLON_OUT 27

2
SRN100J-3-GP
LVDS CONN
R4908
X01_0417 100KR2J-1-GP LCD Power for ROSA
X01_0424 SWAP Signals

1
Main Source=20.F2101.030
DCBATOUT_LCD
Vinafix.com A00_0803
R4905 X02_0619
2 1
LCD1
34 0R0402-PAD-2-GP
32 D4901
30 R4902 D4902 1
17 LVDS_VDD_EN
29 33R2J-2-GP 1 L_BKLT_CTRL 17
28 BLON_OUT_C 3 LCDVDD_EN
27 LCD_BRIGHTNESS 2 1 BKLT_CTRL 3
26 DBC_EN_C DY 27 LCD_TST_EN 2

2
25 3D3V_CAMERA_S0 2 KBC_BKLT 27 3D3V_S0
24 USB_CAMERA# BAT54CPT-GP R4909
23 USB_CAMERA BAT54CPT-GP 83.R2003.E81 100KR2J-1-GP
22 COLOR_ENGINE_R 83.R2003.E81 2ND = 83.00054.Q81 U4901
21 AUD_DMIC_CLK_L 1 R4914 2 0R0402-PAD-2-GP 3D3V_S0 2ND = 83.00054.Q81 LCDVDD

1
AUD_DMIC_IN0_L AUD_DMIC_CLK 29
20 1 R4915 2 0R0402-PAD-2-GP AUD_DMIC_IN0 29 1 EN IN 5
19 X02_0611 2 GND
18 LVDSA_CLK 17 3 OUT NC#4 4

1
2
17 LVDSA_CLK# 17

1
16 C4907
15 LVDSA_DATA2 17 SY6288C6AAC-GP SC4D7U6D3V3KX-GP

1
14 LVDSA_DATA2# 17 RN4903 C4908 EC4907 74.06288.B7F

2
13 SRN2K2J-1-GP SC4D7U6D3V3KX-GP SCD1U50V3KX-GP 2nd = 74.09724.09F
12 LVDSA_DATA1 17
Layout Note: 3rd = 74.03514.07F

4
3

2
11 LVDSA_DATA1# 17 Trace width = 80mil
10
9 LVDSA_DATA0 17
8 LVDSA_DATA0# 17 RN4902
7 LVDS_DDC_DATA_R_1 1 4 LVDS_DDC_DATA_R 17
6 LVDS_DDC_CLK_R_1 2 3 LVDS_DDC_CLK_R 17
5 LCD_TST_C
4 3D3V_LCD_ROM SRN0J-6-GP
3
2

1 LCDVDD
31 3D3V_S0 3D3V_LCD_ROM
2

2
EC4912

EC4911

33 EC4915 C4902
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U16V2KX-3GP SC1U6D3V2KX-GP
STAR-CON30-1-GP-U DY DY R4901 1 2 0R3J-0-U-GP
1

20.F2101.030
2nd = 20.F2056.030 F4902 1 2 FUSE-2A32V-16-GP
DY

RF
X02_0621
Pin 25 no wire to LCD RF

LVDSA_CLK EC4901 1
LVDSA_CLK# EC4902 1 DY22SCD1U10V2KX-5GP
X02_0611 DY SCD1U10V2KX-5GP
LVDSA_DATA2 EC4904 1
LVDSA_DATA2# EC4905 1 DY22SCD1U10V2KX-5GP
Camera Power R4912 DY SCD1U10V2KX-5GP
DBC_EN_C LVDSA_DATA1 EC4906 1
1 2 DBC_EN 22
LVDSA_DATA1# EC4908 1 DY22SCD1U10V2KX-5GP
0R0603-PAD-2-GP DY SCD1U10V2KX-5GP
3D3V_S0 3D3V_CAMERA_S0 LVDSA_DATA0 EC4909 1
R4904 LVDSA_DATA0# EC4910 1 DY22SCD1U10V2KX-5GP
1 2 COLOR_ENGINE_R 1 2
DY SCD1U10V2KX-5GP
DY COLOR_ENGINE 22
0R3J-0-U-GP R4913
1

0R3J-0-U-GP
EC4903 C4903
SCD1U10V2KX-5GP DY SC10U6D3V5KX-1GP
2

X02_0625
USB_CAMERA#
USB_PN12 18

DCBATOUT_LCD DCBATOUT
TR4902
RF F4901 1 2
2 1 X03_0724
4 3
2

POLYSW -1D1A24V-GP-U
C4904

C4905

FILTER-4P-6-GP
EC4913

EC4914

69.50007.A31
SC1KP50V2KX-1GP
SCD1U50V3KX-GP

SCD1U50V3KX-GP

SCD1U50V3KX-GP

DY DY 2nd = 69.50007.A41 69.10103.041 DMB50

1

2nd = 68.00201.141
USB_CAMERA
USB_PP12 18
Wistron Corporation
X02_0625 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD Connector
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 49 of 106
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CRT Connector
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 50 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
5V_HDMI_S0

HDMI CONN
HDMI Level Shifter

3
D5102
BAW 56-2-GP HDMI1
C5103 1 2 SCD1U16V2KX-3GP HDMI_CLK_R_C# 83.00056.G11 22
17 HDMI_CLK_R#
17 HDMI_CLK_R
C5104 1 2 SCD1U16V2KX-3GP Vinafix.com HDMI_CLK_R_C 2nd = 83.00056.E11
HDMI_DATA2_R_C_CON
20
1

1
C5105 1 2 SCD1U16V2KX-3GP HDMI_DATA0_R_C#
17 HDMI_DATA0_R# C5106 1 2 SCD1U16V2KX-3GP HDMI_DATA0_R_C 2

D5102_2

D5102_1
D D
17 HDMI_DATA0_R HDMI_DATA2_R_C#_CON 3
HDMI_DATA1_R_C_CON 4
5
HDMI_DATA1_R_C#_CON 6
C5110 1 2 SCD1U16V2KX-3GP HDMI_DATA1_R_C# HDMI_DATA0_R_C_CON 7
17 HDMI_DATA1_R#

4
3
C5107 1 2 SCD1U16V2KX-3GP HDMI_DATA1_R_C 8
17 HDMI_DATA1_R 3D3V_S0 HDMI_DATA0_R_C#_CON 9
C5108 1 2 SCD1U16V2KX-3GP HDMI_DATA2_R_C# RN5101 HDMI_CLK_R_C_CON 10
17 HDMI_DATA2_R# C5109
17 HDMI_DATA2_R 1 2 SCD1U16V2KX-3GP HDMI_DATA2_R_C SRN2K2J-1-GP 11
HDMI_CLK_R_C#_CON 12
13

1
2
X02_0615 Q5104 14
4 3 DDC_CLK_HDMI DDC_CLK_HDMI 15
17 PCH_HDMI_CLK

8
7
6
5

8
7
6
5
S D
5V_HDMI_S0 DDC_DATA_HDMI 16
RN5106 RN5107 5 G G 2 17
SRN680J-GP SRN680J-GP 18
6 D S 1 19
21

1
2N7002BKS-GP-U X02_0615 23

1
2
3
4

1
2
3
4
HDMI_PLL_GND 17 PCH_HDMI_DATA 84.2N702.E3F C5102
SCD1U16V2KX-3GP SKT-HDMI19P-69-GP

2
DDC_DATA_HDMI 22.10296.211
2nd = 22.10296.431

HPD_HDMI_CON
X02_0615
D

3D3V_S0
5V_S0 Q5103
C 2N7002BK-GP C
G
84.07002.I31

3
Q5102 1 HDMI_HPD_B 2 1
PMBS3904-1-GP 150KR2J-L1-GP R5111
X02_0611

2
S

1
X02_0615
17 HDMI_PCH_DET 2 1 HDMI_HPD_E 84.03904.L06 R5110
R5125 2nd = 84.03904.P11 200KR2J-L1-GP
DY

1
0R0402-PAD-2-GP 3rd = 84.03904.T11
R5112

2
10KR2J-3-GP

2
R5101
HDMI_CLK_R_C# 1 2 HDMI_CLK_R_C#_CON

0R0603-PAD-2-GP

X02_0704
1

ER5101
180R2J-1-GP X02_0622
2

B R5102 B
HDMI_CLK_R_C 1 2 HDMI_CLK_R_C_CON

0R0603-PAD-2-GP

R5104 500mA
HDMI_DATA0_R_C# 1 2 HDMI_DATA0_R_C#_CON 5V_S0 5V_HDMI_S0
F5101
0R0603-PAD-2-GP
1 2
X02_0704
1

FUSE-1D1A6V-4GP-U
ER5102 69.50007.691
180R2J-1-GP X02_0622 2nd = 69.50007.771
R5106
2

HDMI_DATA1_R_C# 1 2 HDMI_DATA1_R_C#_CON

R5103 0R0603-PAD-2-GP
HDMI_DATA0_R_C 1 2 HDMI_DATA0_R_C_CON
X02_0704
1

0R0603-PAD-2-GP
ER5104
R5108 180R2J-1-GP X02_0622
HDMI_DATA2_R_C# 1 2 HDMI_DATA2_R_C#_CON
2

0R0603-PAD-2-GP
DMB50
A X02_0704 A
1

R5105
ER5103 X02_0622 HDMI_DATA1_R_C 1 2 HDMI_DATA1_R_C_CON
180R2J-1-GP Wistron Corporation
0R0603-PAD-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2

Title
R5107
HDMI_DATA2_R_C 1 2 HDMI_DATA2_R_C_CON HDMI Level Shifter/Connector
Size Document Number Rev
0R0603-PAD-2-GP A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 51 of 106

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 52 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 53 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 54 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
ITP/Fan Connector
Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 55 of 106
5 4 3 2 1
SSID = SATA
3D3V_S0 5V_S0 HDD CONN

1
C5604 C5601 C5605 C5606
SC10U6D3V5KX-1GP
DY DY SCD1U10V2KX-5GP SC10U10V5ZY-1GP SCD1U10V2KX-5GP HDD1
Vinafix.com
DY

2
3D3V_S0 P1 V33 23 23
P2 V33 24 24
P3 V33

5V_S0 P7 V5
P8 V5
P9 V5
P13 V12 GND S1
P14 V12 GND S4
P15 V12 GND S7
GND P4
GND P5
SATA_TXP0_C S2 P6
SATA_TXN0_C A+ GND
S3 P10
Layout Note: A- GND
P12
SATA_RXP0_C GND
AC coupling Cap; S6 B+
place near CONN(<100mils) SATA_RXN0_C S5 P11
B- DAS/DSS

SKT-SATA7P-15P-85-GP
21 SATA_TXP0 C5614 2 1 SCD01U50V2KX-1GP SATA_TXP0_C 20.81599.022
21 SATA_TXN0 C5613 2 1 SCD01U50V2KX-1GP SATA_TXN0_C 2nd = 22.10300.C51

21 SATA_RXP0 C5615 1 2 SCD01U50V2KX-1GP SATA_RXP0_C

21 SATA_RXN0 C5616 1 2 SCD01U50V2KX-1GP SATA_RXN0_C

X02_0615

ODD CONN
5V_S0

Layout Note:

2
ODD1 SATA_RX- and SATA_RX+ Trace
15 AC coupling Cap; R5605
Length match within 20 mil
NP2 place near CONN(<100mils) DY 100KR2J-1-GP
X02_0615
S1

1
S2 SATA_TXP4_C C5612 1 2SCD01U50V2KX-1GP SATA_TXP4 21
SATA_TXN4_C C5611 1 2SCD01U50V2KX-1GP SATA_ODD_DA#_C

ODD_PWRGT#
S3 SATA_TXN4 21
S4
S5 SATA_RX4-_C C5607 1 2SCD01U50V2KX-1GP SATA_RXN4 21
S6 SATA_RX4+_C C5608 1 2SCD01U50V2KX-1GP SATA_RXP4 21
S7
3D3V_S0

D 6

G 5

S 4
1 SATA_ODD_PRSNT# 22 X02_0615
Q5601
2 R5604 1 210KR2J-3-GP DY 2N7002BKS-GP-U
ODD_PW R_5V DY

1
3

1 S

2 G

3 D
4 SATA_ODD_DA#_C 2 1 R5607 84.2N702.E3F
SATA_ODD_DA# 18
5 10KR2J-3-GP
6 R5602
0R2J-2-GP

2
NP1
14
SATA_ODD_PW RGT SATA_ODD_DA#

SKT-SATA7P+6P-77-GP-U
22.10300.581
2nd = 20.81152.013

22 SATA_ODD_PW RGT

Zero Power ODD Power Sequence

U5602 ODD_PW R_5V
5V_S0
4 EN OC# 5
3 6 ODD_PW R_5V 100 mil
VIN VOUT#6
2 VIN VOUT#7 7
1 GND VOUT#8 8
1

1
C5617 C5618
SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
UP7534PRA8-15-GP
2

2
74.07534.D79
2nd = 74.00547.G79
DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1
R5606
DY 0R5J-6-GP
2
Taipei Hsien 221, Taiwan, R.O.C.

Title
1
R5603
DY 0R5J-6-GP
2
HDD/ODD
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 56 of 106
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 57 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO

Speaker
X01_0417 X02_0622
SPK1
5
AUD_SPK_L-_C

Vinafix.com
1 R5801 1 2 0R0603-PAD-2-GP
AUD_SPK_L- 29
2 AUD_SPK_L+_C R5802 1 2 0R0603-PAD-2-GP
AUD_SPK_R-_C R5803 AUD_SPK_L+ 29
3 1 2 0R0603-PAD-2-GP
AUD_SPK_R+_C R5804 AUD_SPK_R- 29
4 1 2 0R0603-PAD-2-GP
AUD_SPK_R+ 29
D 6 D

ACES-CON4-29-GP
Layout Note:

2
20.F1639.004 trace width=30mil

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2ND = 20.F1804.004 DY DY DY DY

EC5809

EC5808

EC5807

EC5810
1

1
AFTP5801 1 AUD_SPK_L-_C
AFTP5802 1 AUD_SPK_L+_C
AFTP5803 1 AUD_SPK_R-_C
AFTP5804 1 AUD_SPK_R+_C

Combo Jack

C C

HPMIC1
3 RING2
1 AUD_HP1_JACK_L1 BLM18BD601SN1D-GP 2 1 L5801 AUD_HP1_JACK_L
AUD_HP1_JACK_L 29
5 AUD_HP1_JD# 29
6
2 AUD_HP1_JACK_R1 BLM18BD601SN1D-GP 2 1 L5802 AUD_HP1_JACK_R
AUD_HP1_JACK_R 29
4 SLEEVE
1

1
7 EC5802 EC5804 X02_0615

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP
EC5801
DY EC5803 DY EC5805

SC1KP25V2KX-GP
PHONE-JK509-GP-U1 83.00402.0A0

2
TVL-0402-01-AB1-GP

SC1KP25V2KX-GP
22.10270.L71 2ND = 83.05125.0A0
2ND = 22.10270.P11 X01_0417
2

1 AFTP5810

AFTP5805 1 SLEEVE
AFTP5806 1 RING2
AFTP5807 1 AUD_HP1_JACK_L1
AFTP5808 1 AUD_HP1_JACK_R1
AFTP5809 1 AUD_HP1_JD#

B 3D3V_S0 RTC_AUX_S5 B

SLEEVE

1
R5810 X02_0615

D
100KR2J-1-GP

1
Q5803

2
R5809
R5807 10KR2J-3-GP G

AUD_VREFOUT_A 1 2
29 AUD_VREFOUT_A

2
2N7002BK-GP

D
X02_0615 84.07002.I31

S
1

2K2R2J-2-GP Q5802
C5806
SC1U10V2KX-1GP Layout Note: G
2

L5803 close to Jack

R5808

S
29 MIC_IN_R MIC_IN_R 1 2 MIC_IN_R_C 1 2 MICP 2N7002BK-GP
L5803 BLM18BD601SN1D-GP 84.07002.I31
0R0402-PAD-2-GP
1

A00_0803
C5809 C5811 X02_0615
DY SC100P50V2JN-3GP SC220P50V2KX-3GP 3D3V_S0
2

C5801 C5802 C5803 C5804

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

SCD01U50V2KX-1GP
2

U5801

3D3V_S0 3D3V_S0 13 8
VDD MIC_PRESENT EXT_MIC_JD# 29
16 5 AUD_HP1_JD
RN5801 VDD DET_TRIGGER
4
A MIC_SCL MIC_SCL ADDR_SEL A
1 4 1
1

AUD_HP1_JD# MIC_SDA MIC_SDA SCL MICP

29 AUD_HP1_JD# 2 3 2 11
R5806 SDA MICP
12

1
SLEEVE MICN C5805 EC5806
100KR2J-1-GP 15
G

SRN2K2J-1-GP SLEEVE_SENSE

SC330P50V2KX-3GP

SCD01U16V2KX-3GP
Q5801 6
AUD_HP1_JACK_L1 9
SLEEVE
3
DY
2

2
RING2 TIP_SENSE GND DMB50
14 10
1

AUD_HP1_JD RING2_SENSE GND

S D 7 17
R5805 RING2 GND

DY 10KR2J-3-GP Wistron Corporation

1

2N7002BK-GP
84.07002.I31 DY C5807
SCD1U10V2KX-4GP
TS3A225ERTER-GP
73.03225.003
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
2

X02_0615 Title
Speaker/HPMIC CONN
Size Document Number Rev
A2
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 58 of 106
5 4 3 2 1
 5 4 3 2 1

X01_0413
SSID = LOM XF5901

24 1 MDO3-
31 LAN_MDI3N

Vinafix.com
D 23 2 MDO3+ D
31 LAN_MDI3P
AVDD_CEN 22 1:1 3 XFR_CMT3

AVDD_CEN 21 4 XFR_CMT2
1:1
20 5 MDO2-
31 LAN_MDI2N

XFR_CMT1
19 6 MDO2+ XFR_CMT0
31 LAN_MDI2P
XFR_CMT3
XFR_CMT2
18 7 MDO1-
31 LAN_MDI1N

8
7
6
5
RN5901
SRN75J-1-GP

C 17 8 MDO1+ X01_0426 C
31 LAN_MDI1P
AVDD_CEN 16 1:1 9 XFR_CMT1

1
2
3
4
AVDD_CEN 15 10 XFR_CMT0 LAN_TERMINAL 1 2
1:1
14 11 MDO0-
31 LAN_MDI0N
C5902
SC100P3KV8JN-GP

13 12 MDO0+
31 LAN_MDI0P

XFORM-24P-38-GP
68.IH115.30A
2ND = 68.69241.30C
CHECK CONN
B B
RJ45 Connector
1

C5905 C5904 C5903 C5901

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

DY DY
2

RJ45
10
AFTP5913 1 MDO3- 8
AFTP5912 1 MDO3+ 7
AFTP5903 1 MDO1- 6
AFTP5911 1 MDO2- 5
X02_0615 AFTP5910 1 MDO2+ 4 X01_0412
AFTP5906 1 MDO1+ 3
AFTP5907 1 MDO0- 2

AFTP5908 1 MDO0+ 1 DMB50

9

A
RJ45-8P-118-GP-U
22.10019.141
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AFTP5909 Taipei Hsien 221, Taiwan, R.O.C.
1
Title

RJ45+Transfermer
Size Document Number Rev
0412 Connector List shows 22.10019.141 A4
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 59 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = Flash.ROM
SPI Flash ROM(8M) for PCH
3D3V_S5
Vinafix.com
3D3V_S5

D D

1
X02_0615
C6001 C6002
SC10U6D3V5KX-1GP DY SCD1U16V2KX-3GP

2
2

4
3
R6003 RN6001
4K7R2J-2-GP SRN4K7J-8-GP
PCH

1
2
SPI_HOLD_0#

3D3V_S5
U6001 SPI
21,27 SPI_CS0#_R 1 CS# VCC 8
21,27 SPI_SO_R 2 SO/SIO1 HOLD# 7
SPI_W P# 3 6 SPI_CLK_R 21,27
WP# SCLK
4 5 SPI_SI_R 21,27
1
GND SI/SIO0 KBC

1
MX25L6406EM2I-12G-GP
EC6002 DY 72.25640.D01 EC6001
SC4D7P50V2CN-1GP 2nd = 72.25Q64.B01 DY DY SC10P50V2JN-4GP
2

2
3rd = 72.25Q64.F01 Layout Note:
4th = 72.25Q64.D01 EC6003
X00_1026 SC4D7P50V2CN-1GP KBC----10"----PCH
C
KBC----1.5"~6.5"----SPI C
PCH----0.5"~6.5"----SPI

SSID = RBATT

B B

3D3V_AUX_S5

R6006 RTC_AUX_S5 Q6001 RTC_PW R +RTC_VCC

100R2J-2-GP 2

1 2 3 R6002 RTC1
DY 1KR2J-1-GP
1 1 2 1 PWR
2

2 GND
C6003 CH715FPT-GP NP1
RTC_PW R SC1U6D3V2KX-GP NP1
NP2
1

NP2
83.R0304.B81
2nd = 83.00040.E81 AFTP6001 1
G
1

Q6002 BAT-AAA-BAT-054-P04-GP-U1
R6007 62.70001.061
10MR2J-L-GP 2nd = 62.70015.001
S D RTC_DET# 22
2

2N7002BK-GP
A 84.07002.I31 DMB50 A

AFTP6002 1 +RTC_VCC
X02_0615
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Flash/RTC
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 60 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 61 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = USB
USB3.0 Port1 with power share
USB_PN0_RR X02_0625 USB20_DN0_C
USB30_VCCA
USB1
Vinafix.com 1 VBUS SSRX- 5 USB30_RXDN1_C
TR6204 6 USB30_RXDP1_C USB30_TXDP1_C 1 AFTP6201
SSRX+ USB30_VCCA AFTP6202
D 4 3 1 D
A00_0724 USB20_DN0_C 2 8 USB30_TXDN1_C USB30_TXDN1_C 1 AFTP6203
USB20_DP0_C D- SSTX- USB30_TXDP1_C USB20_DN0_C AFTP6204
1 2 3 D+ SSTX+ 9 1
USB30_RXDP1_C 1 AFTP6205
FILTER-4P-62-GP 10 USBDET# 1 AFTP6206
10 USBDET# USB30_RXDN1_C AFTP6207
11 11 PGND 4 1
12 USB20_DP0_C 1 AFTP6209
12 AFTP6208
13 13 GND 7 1

USB_PP0_RR USB20_DP0_C
X02_0625 SKT-USB13-70-GP-U
22.10341.691

X02_0611
X02_0611
R6208
R6281
USBDET# 1 2 USBDET_CON# 27
1 2 USB30_TXDN1_R 1 2 USB30_TXDN1_C 18 USB3_RX1_N 1 R6283 2 USB30_RXDN1_C
18 USB3_TX1_N 0R0402-PAD-2-GP 0R0402-PAD-2-GP
C6223 0R0402-PAD-2-GP X02_0622
SCD1U16V2KX-3GP

C C
X02_0625 X02_0625
X02_0615
U6204 USB30_VCCA

USB20_DN0_C 1 8

USB20_DP0_C 2 7
1 2 USB30_TXDP1_R 1 R6282 2 USB30_TXDP1_C 18 USB3_RX1_P 1 R6284 2 USB30_RXDP1_C
18 USB3_TX1_P
C6222 0R0402-PAD-2-GP 0R0402-PAD-2-GP
SCD1U16V2KX-3GP USB30_RXDP1_C 3 6 USB30_TXDP1_C
X02_0611 X02_0611
DY
USB30_RXDN1_C 4 5 USB30_TXDN1_C

AZ1065-06Q-GP

B B

5V_S5

USB Charger
1

C6201
SC1U10V3ZY-6GP U6201
USB30_VCCA
2

1 IN DM_OUT 2 USB_PN0 18 TPS2541 charging type setting

DP_OUT 3 USB_PP0 18
12 OUT
11 USB_PN0_RR CTL1 CTL2 CTL3
TC6201 DM_IN USB_PP0_RR
X02_0611 DP_IN 10
1

C6203 C6202 27 USBCHG_EN 5 DSC

SC100U6D3V6MX-GP

SCD1U16V2KX-3GP

R6203 2 1 0R0402-PAD-2-GP CTL1 6 CDP 1 1 1

SC10U10V5ZY-1GP

R6204 CTL1
78.10710.52L 2 1 0R0402-PAD-2-GP CTL2 7 9
2

R6205 CTL2 NC#9

27 USBCHARGER_CB0 2 1 0R0402-PAD-2-GP CTL3 8 CTL3
FAULT# 13 USB_OC#0_1 18,63 DCP 0 0 X
20KR2J-L2-GP 2 1 R6210 ILIM0 16
20KR2J-L2-GP 2 ILIM0
1 R6211 ILIM1 15 14
2 DY
1 R6202 ILIM_SEL 4
ILIM1 GND
17
0R0402-PAD-2-GP ILIM_SEL GND
A X01_0417 X02_0615 DMB50 A
X02_0611 TPS2541ARTER-GP
74.02541.A73
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB 3.0
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 62 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = USB

Vinafix.com 5V_S5 U6301

USB30_VCCB

D 1 GND VOUT#8 8 D
2 VIN VOUT#7 7
3 6 TC6303
VIN VOUT#6

1
C6307
SC1U16V3KX-5GP
4 5 USB_OC#0_1 18,62 C6306
EN# OC#

SCD1U16V2KX-3GP

SC100U6D3V6MX-GP
18 USB_PN1 USB_PN1 X02_0625 USB20_DN1_C C6301 78.10710.52L
SC1U10V3ZY-6GP

2
UP7534QRA8-15-GP

2
74.07534.C79
2nd = 74.06288.A79
TR6301 3rd = 74.02000.B71
4 3 A00_0724 27,82 USB_PW R_EN#
X01_0417
1 2 X02_0615
FILTER-4P-62-GP

18 USB_PP1 USB_PP1 USB20_DP1_C USB3.0 Port2

X02_0625

0411 Connector List shows 22.10341.A81

USB30_VCCB

USB2 USB30_VCCB 1 AFTP6301

10 CHASSIS CHASSIS
13 USB20_DN1_C 1 AFTP6302
USB30_TXDP2_C 9 USB20_DP1_C 1 AFTP6303
C 1 USB30_RXDN2_C 1 AFTP6304 C
X02_0611 USB30_RXDP2_C 1 AFTP6305
USB30_TXDN2_C 8 USB30_TXDN2_C 1 AFTP6306
USB20_DN1_C 2 USB30_TXDP2_C 1 AFTP6307
R6305
7
1 2 USB30_TXDN2_R 1 2 USB30_TXDN2_C USB20_DP1_C 3
18 USB3_TX2_N USB30_RXDP2_C 6
C6314 0R0402-PAD-2-GP 4
SCD1U16V2KX-3GP USB30_RXDN2_C 5
11 12 1 AFTP6308
CHASSIS CHASSIS

SKT-USB13-90-GP
22.10341.A81
X02_0625
X01_0412
X02_0615

1 2 USB30_TXDP2_R 1 R6306 2 USB30_TXDP2_C

18 USB3_TX2_P
C6315 0R0402-PAD-2-GP
SCD1U16V2KX-3GP

B B

X02_0611
R6307

18 USB3_RX2_N 1 2 USB30_RXDN2_C

0R0402-PAD-2-GP

U6302 USB30_VCCB

USB20_DN1_C 1 8
X02_0625
USB20_DP1_C 2 7

USB30_RXDP2_C 3 6 USB30_TXDP2_C

18 USB3_RX2_P 1 R6308 2 USB30_RXDP2_C DY

USB30_RXDN2_C 4 5 USB30_TXDN2_C
0R0402-PAD-2-GP

AZ1065-06Q-GP
A X02_0611 DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB3.0 PORT
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 63 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Finger Printer
Document Number Rev
A3 BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 64 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = Wireless
Mini Card Connector(802.11a/b/g/n)
Vinafix.com
WLAN CONN
D D

X02_0611 1D5V_S0 3D3V_W LAN_AOAC 1D5V_S0

W LAN1
53
R6502
NP1 X02_0615 X01_0420 X02_0615 RF X02_0615
27,66 AOAC_PCIE_W AKE# 1 2 W LAN_W AKE# 1 2

C6505
0R0402-PAD-2-GP

SCD1U16V2KX-3GP
1

1
TPAD14-OP-GP TP6502 1 W LAN_ACT 3 4

SC10U6D3V5KX-1GP
C6502

C6501

C6503
TPAD14-OP-GP TP6503 1 BT_ACT 5 6 C6504
DY

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
1

2
CLK_PCIE_W LAN_REQ#_C 7 8 SC10U6D3V5MX-3GP

2
EC6501
SCD1U10V2KX-5GP

EC6502
SCD1U10V2KX-5GP
9 10
20 CLK_PCIE_W LAN# 11 12
DY DY

1
20 CLK_PCIE_W LAN 13 14
15 16

TPAD14-OP-GP TP6501 1 E51_RxD_R 17 18 X02_0611

1 2 E51_TxD_R 19 20
27 E51_TxD
R6504 DY 0R2J-2-GP 21 22 W LAN_22 1 R6505 2
W IFI_RF_EN 27
R6503
PLT_RST# 5,18,27,31,66,71,83 USB_PP11_R
20 PCIE_RXN4 23 24 18 USB_PP11 1 2
20 PCIE_RXP4 25 26 0R0402-PAD-2-GP
27 28 0R0603-PAD-2-GP
29 30 PCH_SMBCLK
PCH_SMBCLK 14,15,20,66,69
20 PCIE_TXN4 31 32 PCH_SMBDATA
PCH_SMBDATA 14,15,20,66,69
20 PCIE_TXP4 33 34
35 36 USB_PN11_R
37 38 USB_PP11_R
C 39 40 X02_0622 C
3D3V_W LAN_AOAC
41 42
43 44 W LAN_LED# W LAN_LED# 68
45 46 W PAN_LED# W PAN_LED# 68
R6508 47 48
10KR2J-3-GP 49 50
1 2 51 52 R6506
5V_S5 DY NP2 18 USB_PN11 1 2 USB_PN11_R
54
RF 0R0603-PAD-2-GP

2
18 BLUETOOTH_EN SKT-MINI52P-54-GP-U

EC6503
SCD1U10V2KX-5GP

EC6504
SCD1U10V2KX-5GP

EC6505
SCD1U10V2KX-5GP
62.10043.981 DY DY DY
2nd = 20.F1764.052

1
3rd = 62.10043.F11

3D3V_S5 3D3V_W LAN_AOAC 3D3V_W LAN_AOAC

U6502
AO3400A-GP

1
D S
R6507
100R2J-2-GP
3D3V_W LAN_AOAC 84.03400.B37 DY

G
B B
2nd = 84.03404.B31

2
AO3404A MAX 4.9A
Rds(on) =33 ~ 40mOhm

U6501_D
1

R6513
10KR2J-3-GP 15V_S5 1 2 VAUX_G_SW
1

R6512

D
2

1
R6509
CLK_WLAN_REQ#_EN

10KR2J-3-GP
100KR2J-1-GP C6506

SCD01U50V2KX-1GP
2

2
X02_0615 DY
3D3V_S5

D
U6503
84.03904.L06
2ND = 84.03904.P11

S
2
G
1

Q6502 R6510 AOAC_W LAN_EN#

PMBS3904-1-GP 100KR2J-1-GP
20 CLK_PCIE_W LAN_REQ# 3 2 CLK_PCIE_W LAN_REQ#_C U6501
2N7002BK-GP 2N7002K-2-GP

S
R6511 84.07002.I31 84.2N702.J31
2
DY 1 2ND = 84.2N702.031
0R2J-2-GP 27,68 AOAC_W LAN_EN# AOAC_W LAN_EN#

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

WLAN/BT
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 65 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = Wireless

WWAN CONN

WWAN1
53 R6615

Vinafix.com
NP1 0R2J-2-GP
R6602 2 1 WWAN_WAKE# 2 1
1 2 USB_PP8_R 1D5V_S0 DY AOAC_PCIE_WAKE# 27,65
18 USB_PP8 WWAN 4 3
0R0603-PAD-2-GP 6 5
D UIM_PWR 8 7 D

1
C6602 C6603 UIM_DATA 10 9

2
SC33P50V2JN-3GP SCD047U10V2KX-2GP UIM_CLK_L R6604 1 2 33R2J-2-GP UIM_CLK 12 11

EC6615
SCD1U10V2KX-5GP

EC6614
SCD1U10V2KX-5GP
UIM_RESET 14 13
DY DY WWAN WWAN WWAN

2
UIM_VPP 16 15

1
X02_0622
3D3V_WWAN_AOAC
X02_0611 18 17
3G_EN 20 19
27 3G_EN
1 R6616 2 WWAN_22 22 21
RF 5,18,27,31,65,71,83 PLT_RST# 0R0402-PAD-2-GP 24 23
26 25

2
R6601 C6604 28 27

EC6613
SCD1U10V2KX-5GP

EC6612
SCD1U10V2KX-5GP
1 USB_PN8_R SCD1U16V2KX-3GP
18 USB_PN8 WWAN2 DY DY 14,15,20,65,69 PCH_SMBCLK 30
32
29
31
WWAN 14,15,20,65,69 PCH_SMBDATA

1
0R0603-PAD-2-GP 34 33
USB_PN8_R 36 35
USB_PP8_R 38 37
40 39
RF 68 WWAN_LED#
WWAN_LED# 42 41
3D3V_WWAN_AOAC
44 43
46 45
EC6602 3D3V_WWAN_AOAC 48 47
SC1U6D3V2KX-GP 50 49 DAS 1 TP6602 TPAD14-OP-GP
SIM1 52 51

SC33P50V2JN-3GP
C6605

SC33P50V2JN-3GP
C6606

SCD047U10V2KX-2GP
C6607

SCD047U10V2KX-2GP
C6608
10 1 2 NP2
8 WWAN 54
C1 UIM_PWR TC6601

1
SKT-MINI52P-54-GP-U

ST220U6D3VDM-20GP
C5
C2 UIM_RESET WWAN

2
C6 UIM_VPP 62.10043.981
WWAN C3 UIM_CLK_L WWAN WWAN 2nd = 20.F1764.052
C7 UIM_DATA WWAN WWAN WWAN 3rd = 62.10043.F11
9
11

SDCARD-10P-1-GP
62.10051.971

C C

Layout Note:
DATA & CLK keep about 20mil
3D3V_S5 3D3V_WWAN_AOAC 3D3V_WWAN_AOAC
U6607
AO3400A-GP

1
D S
R6611
6 UIM_VPP DY 100R2J-2-GP
UIM_RESET 1 84.03400.B37 DY

G
2nd = 84.03404.B31

2
2 5 UIM_PWR AO3404A MAX 4.9A
DY RF 3D3V_S0 3D3V_WWAN_AOAC RF Rds(on) =33 ~ 40mOhm

U6605_D
R6603
1 2
0R0603-PAD-2-GP
2

2
UIM_CLK_L 3 4 UIM_DATA 1 2 WWAN_G_SW
15V_S5
EC6608
SCD1U10V2KX-5GP

EC6609
SCD1U10V2KX-5GP

EC6610
SCD1U10V2KX-5GP

EC6611
SCD1U10V2KX-5GP
DY DY DY DY
SC10P50V2JN-4GP

SC33P50V2JN-3GP

EC6605 EC6601 U6601 1 2

DY DY

D
1

1
1

1
SC33P50V2JN-3GP

SC33P50V2JN-3GP

EC6606

EC6607

SRV05-4-2-GP R6605 R6612

1

0R0603-PAD-2-GP X01_0418 100KR2J-1-GP C6609

WWAN WWAN
WWAN WWAN

SCD01U50V2KX-1GP
2

2
Close to SIM1 DY
2

X02_0622 3D3V_AUX_KBC

D
U6608

S
2
G
R6613 AOAC_WWAN_EN#
DY
Layout Note: 100KR2J-1-GP
DY U6605
2N7002BK-GP 2N7002K-2-GP

S
84.07002.I31 84.2N702.J31
2ND = 84.2N702.031
X02_0615
AOAC_WWAN_EN#
27,68 AOAC_WWAN_EN#
B B

SSID = MSATA mSATA CONN

MSATA1
53
NP1
2 1

3D3V_S0
X02_0611 3D3V_MSATA
4 3
6 5
R6606 8 7
10 9
1 2 12 11
0R0603-PAD-2-GP 14 13
16 15
R6607
18 17 X02_0615
1 2 3D3V_MSATA 20 19
0R0603-PAD-2-GP 22 21
24 23 SATA_RXP1_C C6614 1 2 SCD01U50V2KX-1GP SATA_RXP1 21
26 25 SATA_RXN1_C C6611 1 2 SCD01U50V2KX-1GP SATA_RXN1 21
28 27
1

14,15,20,65,69 PCH_SMBCLK 30 29
C6622 14,15,20,65,69 PCH_SMBDATA 32 31 SATA_TXN1_C C6619 1 2 SCD01U50V2KX-1GP SATA_TXN1 21
SCD1U16V2KX-3GP 34 33 SATA_TXP1_C C6618 1 2 SCD01U50V2KX-1GP SATA_TXP1 21
2

36 35
X02_0615 38 37
40 39 3D3V_MSATA
42 41
A A
44 43
3D3V_MSATA 46 45
48 47
50 49 DAS 1 TP6601 TPAD14-OP-GP
52 51 MSATA_DET#
MSATA_DET# 22 DMB50
SC33P50V2JN-3GP
C6625

SC33P50V2JN-3GP
C6626

SCD047U10V2KX-2GP
C6627

SCD047U10V2KX-2GP
C6623

NP2
54

Wistron Corporation
1

SKT-MINI52P-54-GP-U
62.10043.981 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2nd = 20.F1764.052 Taipei Hsien 221, Taiwan, R.O.C.
2

3rd = 62.10043.F11
Title

WWAN/MSATA
Size Document Number Rev
A2
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 66 of 106

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 67 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface
PWRBTN
Front Power LED
PW SW 1
LOW actived from KBC GPIO
5V_S5
Q6801
Vinafix.com

1
R2
E R6806
27 PW RLED# B R1
C LED_PW R 1 2 FPOW ER_LED_A FPOW ER_LED_A 82 27 KBC_PW RBTN# 1 2 KBC_PW RBTN#_C 6 5
D R6802 D

1
PDTA144VT-GP 680R2J-3-GP PW LED1 100R2J-2-GP

SC220P50V2KX-3GP
2 POW ER_SW _LED_B

EC6801
84.00144.P11 DY 1 A K

2
2nd = 84.DT144.A11 R6808 300R2J-4-GP

2
83.19213.H70 LED-W -45-GP
A00_0808 2nd = 83.00191.F70
PW LED2
1 2 POW ER_SW _LED_C A K SW -TACT-130-GP-U
R6811 300R2J-4-GP 62.40009.731
5V_S0 83.19213.H70 LED-W -45-GP 2nd = 62.40089.441
2nd = 83.00191.F70 3rd = 62.40009.D71
Q6805
R2
E R6812
21 SATA_LED# B R1
C SATA_LED_R 1 2 HDD_LED_A HDD_LED_A 82
SATA HDD LED

1
PDTA144VT-GP 680R2J-3-GP

EC6810
SC220P50V2KX-3GP
LOW actived from PCH GPIO 84.00144.P11 DY
2nd = 84.DT144.A11

2
C Battery LED2(White_LED) C
5V_S5
LOW actived from KBC GPIO Q6809
R2
E R6804
27 BATT_W HITE_LED# B R1
C LED_BATCHG 1 2 BAT_W HITE_LED_A BAT_W HITE_LED_A 82
PDTA144VT-GP 5V_S5 5V_W LAN_LED

SC220P50V2KX-3GP
680R2J-3-GP

1
EC6804
84.00144.P11
2nd = 84.DT144.A11 DY Q6802

2
S

D
5V_S5
Battery LED1(Amber_LED) Q6808
R2
DY G
E
LOW actived from KBC GPIO B
R6805
2N7002K-2-GP
27 CHG_AMBER_LED# R1
LED_BAT BAT_AMBER_LED_A
C 1 2 BAT_AMBER_LED_A 82
84.2N702.J31
SC220P50V2KX-3GP

PDTA144VT-GP
EC6802

680R2J-3-GP 2ND = 84.2N702.031

1

84.00144.P11
2nd = 84.DT144.A11 DY
2

1 2 AOAC_LED_SW
TPLOCK LED 15V_S5 DY
LOW actived from KBC GPIO

1
R6807
100KR2J-1-GP
B DY C6802 B

SCD01U50V2KX-1GP
2
3D3V_S5

D
5V_S0
Q6807
R2
E

2
B
27 TP_LOCK_LED# R1
C TP_LOCK_LED_R 1 2 TP_LOCK_LED_A DY
TP_LOCK_LED_A 82 DY R6803
1

PDTA144VT-GP R6818 100KR2J-1-GP

SC220P50V2KX-3GP

680R2J-3-GP Q6803
EC6812

84.00144.P11 DY

S
2nd = 84.DT144.A11 D6802 2N7002K-2-GP
2

27,66 AOAC_W W AN_EN# 1 84.2N702.J31

3 AOAC_LED_EN# 2ND = 84.2N702.031
DY
27,65 AOAC_W LAN_EN# 2
WLAN LED X02_0611 BAT54A-7-F-1-GP
LOW actived from KBC GPIO 5V_S0 5V_W LAN_LED
1 2
R6810
R6809 DY 0R2J-2-GP
1 2

0R0402-PAD-2-GP

D6801 5V_W LAN_LED

A 1 Q6806 A
66 W W AN_LED# R2 DMB50
E R6815
3 AOAC_LED# B R1
83.R2003.P81 C W LAN_LED_R 1 2 W LAN_LED_A
65 W PAN_LED# 2 2nd = 83.00056.G11
W LAN_LED_A 82
Wistron Corporation
1

PDTA144VT-GP 680R2J-3-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

SC220P50V2KX-3GP

BAT54A-7-F-1-GP Taipei Hsien 221, Taiwan, R.O.C.

EC6811

84.00144.P11 DY
D6803 2nd = 84.DT144.A11
2

B0530W S-7-F-GP Title

65 W LAN_LED# K A LED Bard/Power Button

Size Document Number Rev
83.R5003.G8H A3
2nd = 83.R5003.H8H BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 68 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = KBC SSID = Touch.Pad

Internal Keyboard Connector

KB1 1 AFTP6901
Vinafix.com
31
D 1 D
KB_DET# 21 Touch Pad Connector X02_0622
2 KROW 7 1 AFTP6909
3 KROW 6 1 AFTP6910
4 KROW 4 1 AFTP6911
5 KROW 2 1 AFTP6913 TP_VDD 3D3V_S0
6 KROW 5 1 AFTP6912 TP_VDD TP_VDD R6909
7 KROW 1 1 AFTP6914 1 2
8 KROW 3 1 AFTP6916
9 KROW 0 1 AFTP6915 0R0603-PAD-2-GP
10 KCOL5 1 AFTP6917 X02_0615

1
2

1
11 KCOL4 1 AFTP6919
12 KCOL7 1 AFTP6918 KROW [0..7] 27 RN6901 C6901
13 KCOL6 1 AFTP6920 SRN10KJ-5-GP SCD1U16V2KX-3GP X02_0621

2
14 KCOL8 1 AFTP6922
15 KCOL3 1 AFTP6921 KCOL[0..16] 27 TPAD1
16 KCOL1 1 AFTP6923 7

4
3
17 KCOL2 1 AFTP6925 1
18 KCOL0 1 AFTP6924
19 KCOL12 1 AFTP6926 27 TPCLK R6911 1 2 0R2J-2-GP TPCLK_C 2
20 KCOL16 1 AFTP6928 27 TPDATA R6910 1 2 0R2J-2-GP TPDATA_C 3
21 KCOL15 1 AFTP6927 4
22 KCOL13 1 AFTP6929 14,15,20,65,66 PCH_SMBCLK 5

1
23 KCOL14 1 AFTP6931 14,15,20,65,66 PCH_SMBDATA 6
24 KCOL9 1 AFTP6930 EC6917 EC6918 8
25 KCOL11 1 AFTP6932 SC33P50V2JN-3GP DY SC33P50V2JN-3GP
DY

2
26 KCOL10 1 AFTP6934 PTW O-CON6-12-GP
27 CAP_LED CAP_LED 20.K0382.006
28 2nd = 20.K0320.006
C 29 1 C
30 1 AFTP6902 AFTP6935
32

JAE-CON30-7-GP
20.K0565.030
2nd = 20.K0592.030 TP_VDD 1 AFTP6906
TPCLK_C 1 AFTP6907
TPDATA_C 1 AFTP6908
PCH_SMBCLK 1 AFTP6933
PCH_SMBDATA 1 AFTP6937

CAP LED Control 5V_S0 CAP_LED

Q6902
LOW actived from KBC GPIO R2
E
B R6906
27 CAP_LED# R1
CAP_LED_Q CAP_LED
C 1 2

PDTA144VT-GP 1KR2J-1-GP
84.00144.P11
2nd = 84.DT144.A11

KB Backlight Connector
5V_S0 +5V_KB_BL
B B
R6902
1 2
0R2J-2-GP
1

1 2 C6905
R6907 DY 0R5-2A SCD1U16V2KX-3GP
2

KBLIT1
5
X02_0615 1

1 2 KB_LED_DET_C1 2
R6905 51KR2J-1-GP 3
2 KB_LED_DET_C
KB_BL_CTRL#

1 4
18 KB_LED_BL_DET R6904 DY 51KR2J-1-GP 6
A00_0803
1

ACES-CON4-34-GP
R6903 20.K0589.004 +5V_KB_BL 1
KB_LED_BL_DET AFTP76
100KR2J-1-GP

2nd = 20.K0613.004 1
KB_BL_CTRL#_R 1 AFTP77
2

2 0R2J-2-GP
R6912

AFTP78
2

0R0402-PAD-2-GP
R6908

DY
1

1 KB_BL_CTRL#_R

A DMB50 A
A00_0803
D

Q6901
P8503BMG-GP Wistron Corporation
G 84.P8503.031 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
27 KB_BL_CTRL Taipei Hsien 221, Taiwan, R.O.C.
2nd = 84.03404.C31
1

R6901 Title
100KR2J-1-GP
Key Board/Touch Pad
Size Document Number Rev
2

A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 69 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface
Vinafix.com
D D

27 LID_CLOSE# LID_CLOSE#

1
C7002
SCD047U16V2KX-1-GP DY

2
3D3V_S5 LIDSW1
C C
3 OUT
2 VDD
1 VSS

1
X02_0615
C7001 S-5712ACDL1-M3T1U-GP
SCD1U16V2KX-3GP 74.05712.0BB

2
2nd = 74.09132.C7B
3rd = 74.01803.07B

B B

DMB50

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Hall Sensor
Size Document Number Rev
A4 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 70 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = DEBUG PORT

Layout Note: Debug Connector
A00_0806
Place near trace separated point 3D3V_S0
DB1
11
LPC_AD[3..0] RN7101 1
21,27 LPC_AD[3..0]
SRN0J-7-GP
Vinafix.com
LPC_AD0
LPC_AD1
DY
1
2
8
7
LPC_LAD0_R
LPC_LAD1_R
2
3
LPC_AD2 3 6 LPC_LAD2_R 4
D LPC_AD3 4 5 LPC_LAD3_R 5 D
LPC_FRAME#_DEBUG 6
1 2 PLT_RST#_DEBUG 7
21,27 LPC_FRAME#
R7101 1
DY 2 0R2J-2-GP R7103 8
5,18,27,31,65,66,83 PLT_RST#
R7102 DY 0R2J-2-GP 1 2 CLK_PCI_LPC_R 9
18 CLK_PCI_LPC DY 10

1
22R2J-2-GP 12

EC7101
SC33P50V2JN-3GP
PAD-10P-177042-GP
DY

2
ZZ.00PAD.Y41

Layout Note:
Keep R7103,EC7101 close to PCH

SSID = CPU

C C

CPU XDP

XDP_PREQ# 1 TP7101 TPAD14-OP-GP

5 XDP_PREQ# XDP_PRDY# TP7102 TPAD14-OP-GP
5 XDP_PRDY# 1

5 XDP_BPM0 XDP_BPM0 1 TP7103 TPAD14-OP-GP

5 XDP_BPM1 XDP_BPM1 1 TP7104 TPAD14-OP-GP

5 XDP_BPM2 XDP_BPM2 1 TP7105 TPAD14-OP-GP

5 XDP_BPM3 XDP_BPM3 1 TP7106 TPAD14-OP-GP

5 XDP_BPM4 XDP_BPM4 1 TP7107 TPAD14-OP-GP

5 XDP_BPM5 XDP_BPM5 1 TP7108 TPAD14-OP-GP

5 XDP_BPM6 XDP_BPM6 1 TP7109 TPAD14-OP-GP

5 XDP_BPM7 XDP_BPM7 1 TP7110 TPAD14-OP-GP
B CFG0 TP7111 TPAD14-OP-GP B
7 CFG0 1

DMB50
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Dubug connector
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 71 of 106

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 72 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 73 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 74 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

DMB50
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 75 of 106

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 76 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 77 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 78 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 79 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 80 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 81 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface X02_0621

5V_S5
MEDIA1
9 LEDBD1 TPLED1
1 7 5
1 FPOW ER_LED_A
2
3
INSTANT_LAUNCH#_LED_1 R8201 1
AUDIO_PRESENT#_LED_1 R8202 1
Vinafix.com
21KR2J-1-GP
21KR2J-1-GP
INSTANT_LAUNCH#_LED# 27
AUDIO_PRESENT#_LED# 27 2 HDD_LED_A
FPOW ER_LED_A 68

HDD_LED_A 68
1 TP_LOCK_LED_A 68

4 MOBILITY_CENTER#_LED_1 R8203 1 21KR2J-1-GP MOBILITY_CENTER#_LED# 27 3 BAT_W HITE_LED_A BAT_W HITE_LED_A 68 2

D 5 INSTANT_LAUNCH#_1 1 8 INSTANT_LAUNCH# 27 4 BAT_AMBER_LED_A BAT_AMBER_LED_A 68 3 D
6 AUDIO_PRESENT#_1 2 7 AUDIO_PRESENT# 27 5 W LAN_LED_A W LAN_LED_A 68 4
7 MOBILITY_CENTER#_1 3 6 MOBILITY_CENTER# 27 6
8 4 5 8 6
10
RN8201 PTW O-CON6-12-GP ACES-CON4-10-GP-U
ACES-CON8-40-GP SRN33J-7-GP 20.K0382.006 20.K0320.004
20.K0667.008 2nd = 20.K0320.006 2nd = 20.K0382.004
2nd = 20.K0665.008 INSTANT_LAUNCH#_LED# 1 2
AUDIO_PRESENT#_LED# EC8203 1 2 SC470P50V-2-GP
MOBILITY_CENTER#_LED# EC8204 1 2 SC470P50V-2-GP
EC8205 SC470P50V-2-GP AFTP8209 1 FPOW ER_LED_A AFTP8215 1 TP_LOCK_LED_A
AFTP8210 1 HDD_LED_A AFTP8214 1 GND
AFTP8211 1 BAT_W HITE_LED_A
AFTP8212 1 BAT_AMBER_LED_A
AFTP8201 1 INSTANT_LAUNCH#_LED_1 AFTP8213 1 W LAN_LED_A
AFTP8202 1 AUDIO_PRESENT#_LED_1 AFTP8216 1 GND
AFTP8203 1 MOBILITY_CENTER#_LED_1

AFTP8205 1 INSTANT_LAUNCH#
AFTP8206 1 AUDIO_PRESENT#
AFTP8207 1 MOBILITY_CENTER#
AFTP8208 1 GND 3D3V_S0 5V_S0

X02_0611

1
R8205 R8204
C
X01_0417 Change Conn 0R3J-0-U-GP
DY 0R0603-PAD-2-GP C

X01_0424 Swap signal TPAN1

2
7
X01_0430 Change to 20.F2089.040 USB_PP2_C USB_PP2 18
X02_0625 1 TPAN_VDD

IOBD1 2
49 TR8201 3 USB_PN4_TPAN
1 2 4 USB_PP4_TPAN
47 51 X03_0724 5
40 5V_S5 6
39 4 3
38 W CM2012F2S-GP-U2 8
37 69.10084.081
36 ETY-CON6-21-GP
35 USB_PN2_C USB_PN2 18 20.F1876.006
46 34 X02_0625
33 X01_0423
32
31
30
29 3D3V_S0
28
45 27 USB_PW R_EN# 27,63 USB_PP3_C X02_0625 USB_PP3 18
26 A00_0806
25 USB_OC#2_3 18
24
23 USB_PP2_C TR8202 18 USB_PN4 ER8207 1 2 USB_PN4_TPAN
B USB_PN2_C 0R0603-PAD-2-GP B
22 1 2
21 X03_0724 18 USB_PP4 ER8208 1 2 USB_PP4_TPAN
44 20 USB_PP3_C 0R0603-PAD-2-GP
19 USB_PN3_C 4 3
18 W CM2012F2S-GP-U2
17 USB_PP10_C 69.10084.081
16 USB_PN10_C
15 USB_PN3_C USB_PN3 18
14 X02_0625
43 13
12 USB3_TX3_P 18
11 USB3_TX3_N 18
10
9 5V_S5 3D3V_S0
USB3_RX3_N 18
8 USB3_RX3_P 18
7 USB_PP10_C ER8205 1 2 0R0603-PAD-2-GP USB_PP10 18
42 6 USB3_TX4_P 18

SC10U6D3V3MX-GP
5 USB3_TX4_N 18 X02_0605

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
EC8201

EC8202
4

SCD1U16V3KX-3GP
2

C8205
3 USB3_RX4_N 18

C8206
2 USB3_RX4_P 18
X02_0622 DY DY

2
1
41 50

48

IPEX-CONN40-2R-1-GP USB_PN10_C 1 2 USB_PN10 18 X01_0417 C8201=EC8201 , C8202=EC8202

A 20.F2089.040 ER8206 0R0603-PAD-2-GP DMB50 A
2nd = 20.F2091.040

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

IO Board Connector Rev
A3 BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 82 of 106
5 4 3 2 1
 5 4 3 2 1

4 PEG_TXP[7..0] 1D05V_VGA_S0
3D3V_VGA_S0 4 PEG_TXN[7..0]

X02_0615 3D3V_VGA_S0 Vinafix.com 4 PEG_RXP[7..0]

4 PEG_RXN[7..0]
C8334 C8340 C8337 C8348 C8338 C8339 C8353 C8346

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
SCD1U16V2KX-3GP
G

SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
D D

1
Q8301

1
10KR2J-3-GP

10KR2J-3-GP
R8303 VGA1A 1 OF 14 SG SG SG SG SG SG SG SG
D S
SG DY

2
SG R8302
1/14 PCI_EXPRESS
2N7002BK-GP

2
84.07002.I31 AB6
PEX_WAKE#

PEX_IOVDD
AA22
3300 mA
VGA_RST# AC7 AB23
PEX_RST# PEX_IOVDD
PEX_IOVDD
AC24 X02_0615
R8308 1 20R2J-2-GP VGA_PEG_CLKREQ# AC6 AD25
20 PEG_CLKREQ# DY PEX_CLKREQ# PEX_IOVDD
AE8
PEX_IOVDD
AE26
AE27
X7R, Under GPU. X7R, Near GPU and power soruce.
20 CLK_PCIE_VGA PEX_REFCLK PEX_IOVDD
20 CLK_PCIE_VGA# AD8
PEX_REFCLK#
PEG_RXP0 SCD22U10V2KX-1GP 2 C8318 PEG_C_RXP0 AC9
PEG_RXN0 SCD22U10V2KX-1GP 2 SG11 C8317 PEG_C_RXN0 AB9 PEX_TX0 1D05V_VGA_S0
SG PEX_TX0#
PEG_TXP0 AG6
PEG_TXN0 PEX_RX0
AG7 AA10
PEX_RX0# PEX_IOVDDQ
AA12
PEG_RXP1 SCD22U10V2KX-1GP 2 C8320 PEG_C_RXP1 AB10 PEX_IOVDDQ C8345 C8343
C8342
PEG_RXN1 SCD22U10V2KX-1GP 2 SG11 C8319 PEG_C_RXN1 AC10 PEX_TX1 PEX_IOVDDQ
AA13
AA16
SG PEX_TX1# PEX_IOVDDQ
AA18

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
PEG_TXP1 PEX_IOVDDQ C8344 C8341 C8347 C8354
AF7 AA19

1
PEG_TXN1 PEX_RX1 PEX_IOVDDQ
AE7 AA20

1
PEX_RX1# PEX_IOVDDQ

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
PEG_RXP2 PEG_C_RXP2 AD11 PEX_IOVDDQ
AA21
SG SG SG
SCD22U10V2KX-1GP 2 C8321 SG SG SG SG
SG11 AB22

2
PEG_RXN2 SCD22U10V2KX-1GP 2 C8322 PEG_C_RXN2 AC11 PEX_TX2 PEX_IOVDDQ
AC23
SG

2
PEX_TX2# PEX_IOVDDQ
AD24
PEG_TXP2 PEX_IOVDDQ
AE9 AE25
PEG_TXN2 PEX_RX2 PEX_IOVDDQ
AF9 AF26
PEX_RX2# PEX_IOVDDQ
AF27
PEG_RXP3 SCD22U10V2KX-1GP 2 C8323 PEG_C_RXP3 AC12 PEX_IOVDDQ
SG11 PEX_TX3
X02_0615
PEG_RXN3 SCD22U10V2KX-1GP 2 C8328 PEG_C_RXN3 AB12
SG PEX_TX3#
PEG_TXP3
PEG_TXN3
AG9
AG10
PEX_RX3 X7R, Under GPU.
PEX_RX3# X7R, Near GPU and power soruce.
PEG_RXP4 SCD22U10V2KX-1GP 2 C8327 PEG_C_RXP4 AB13
C
PEG_RXN4 SCD22U10V2KX-1GP 2 SG1 C8326 PEG_C_RXN4 AC13 PEX_TX4
C

SG1 PEX_TX4#
PEG_TXP4 AF10
PEG_TXN4 PEX_RX4
AE10
PEX_RX4#
PEG_RXP5 SCD22U10V2KX-1GP 2 C8335 PEG_C_RXP5 AD14
PEG_RXN5 SCD22U10V2KX-1GP 2 SG11 C8336 PEG_C_RXN5 AC14 PEX_TX5
AA8 X02_0615 210 mA
SG PEX_TX5# PEX_PLL_HVDD
AA9 3D3V_VGA_S0
PEG_TXP5 PEX_PLL_HVDD
AE12
PEG_TXN5 PEX_RX5 C8367 C8371
AF12
PEX_RX5#
AB8

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
1

1
PEG_RXP6 SCD22U10V2KX-1GP 2 C8330 PEG_C_RXP6 AC15 PEX_SVDD_3V3
PEG_RXN6 SCD22U10V2KX-1GP 2 SG11 C8329 PEG_C_RXN6 AB15 PEX_TX6
SG PEX_TX6# SG
SG

2
PEG_TXP6 AG12
PEG_TXN6 PEX_RX6
AG13
PEX_RX6#
PEG_RXP7 SCD22U10V2KX-1GP 2 C8332 PEG_C_RXP7 AB16
PEG_RXN7 SCD22U10V2KX-1GP 2 SG11 C8331 PEG_C_RXN7 AC16 PEX_TX7
SG PEX_TX7#
PEG_TXP7 AF13
PEG_TXN7 PEX_RX7
AE13
PEX_RX7# SG
AD17 NC
Near GPU and power soruce.
PEX_TX8
AC17 NC
PEX_TX8#
AE15 NC
PEX_RX8
AF15 NC
PEX_RX8#
AC18 NC F2
PEX_TX9 VDD_SENSE NVVDD_SENSE 92
AB18 NC
PEX_TX9#
AG15 NC F1
PEX_RX9 GND_SENSE NVGND_SENSE 92
AG16 NC
PEX_RX9#
AB19 NC
PEX_TX10
AC19 NC
PEX_TX10#
AF16 NC
PEX_RX10
AE16 NC
B PEX_RX10# B
AD20 NC
PEX_TX11
AC20 NC
PEX_TX11#
AE18 NC
PEX_RX11
AF18 NC
PEX_RX11#
AC21
AB21
PEX_TX12 NC
R8305
dGPU reset
PEX_TX12# NC
200R2F-L-GP
PEX_TSTCLK_OUT
AG18
PEX_RX12 NC PEX_TSTCLK_OUT
AF22
PEX_TSTCLK_OUT#
1 DY 2 R8307
AG19
PEX_RX12# NC PEX_TSTCLK_OUT#
AE22 22 DGPU_HOLD_RST# 1 DY 2
0R2J-2-GP VGA_RST# 86
AD23
PEX_TX13 NC
150mA 1D05V_VGA_S0
AE23 NC
PEX_TX13#
AF19 NC AA14 X02_0615 R8309
PEX_RX13 PEX_PLLVDD VCC1R05VIDEO_PEX_PLLVDD 3D3V_VGA_S0
AE19 AA15 2 1
PEX_RX13# NC PEX_PLLVDD SG U8301
AF24 NC C8369 C8368 C8370 0R0603-PAD-2-GP 1 5
PEX_TX14 22 DGPU_HOLD_RST# A VCC
AE24

SCD1U16V2KX-3GP
NC

1
PEX_TX14#
X02_0622 2 SG

SC1U16V3KX-5GP

SC4D7U25V5KX-GP
5,18,27,31,65,66,71 PLT_RST# B
AE21
PEX_RX14 NC
R8304 SG SG SG VGA_RST#
AF21 NC 3 4 X01 1110

2
PEX_RX14# TESTMODE GND Y
AD9 1 2
AG24 NC
TESTMODE 10KR2J-3-GP SG U74LVC1G08G-AL5-R-GP-U R8319
PEX_TX15
AG25
PEX_TX15# NC DY 10KR2J-3-GP

AG21 NC 73.01G08.EHG

1
PEX_RX15
AG22
PEX_RX15# NC 2nd = 73.7SZ08.EAH
R8306 C8369, Under GPU.
GF119 GF117
AF25 PEX_TERMP 2 1 20100621 NV suggestion 3rd = 73.7SZ08.DAH
PEX_TERMP SG
2K49R2F-GP Near GPU and power soruce. 4th = 73.01G08.L04
N13M-NS-S-A1-GP

A A

DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_PEG/STRAPPING(1/5)
Size Document Number Rev
A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 83 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
88,89 FBA_D[63..0] VGA1B 2 OF 14
D 1D5V_VGA_S0 D
2/14 FBA
FBA_D0 E18 F3 FB_CLAMP 4 OF 14 VGA1D
FBA_D0 GF119 NC FB_CLAMP
FBA_D1 F18 12/14 FBVDDQ
FBA_D2 FBA_D1
E16 GF117

1
FBA_D3 FBA_D2
F17 B26
FBA_D4 FBA_D3 FBVDDQ C8409 C8408 C8411 C8410 C8412 C8433
D20 C25
FBA_D5 FBA_D4 FBVDDQ
D21 SG R8411 E23

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
FBA_D6 FBA_D5 FBVDDQ

C8434

C8432
F20 10KR2J-3-GP E26

1
FBA_D7 FBA_D6 FBVDDQ
E21 F14

2
FBA_D8 FBA_D7 FBVDDQ
E15
FBA_D8 FBVDDQ
F21
SG SG SG SG SG SG SG SG X01_0420
FBA_D9 D15 G13

2
FBA_D10 FBA_D9 FBVDDQ
F15 G14
FBA_D11 FBA_D10 FBVDDQ
F13 G15
FBA_D12 FBA_D11 FBVDDQ
C13 G16
FBA_D13 FBA_D12 FBVDDQ
B13 G18
FBA_D14 FBA_D13 FBVDDQ
E13 G19
FBA_D15 FBA_D14 FBVDDQ
D13
FBA_D15 FBVDDQ
G20 X02_0615
FBA_D16 B15 G21
FBA_D17 FBA_D16 FBVDDQ
C16 H24
FBA_D18 FBA_D17 FBVDDQ
A13 H26
FBA_D19 FBA_D18 FBVDDQ
FBA_D20
A15
B18
FBA_D19 FBVDDQ
J21
K21
Under GPU Near GPU
FBA_D21 FBA_D20 FBVDDQ
A18 L22
FBA_D22 FBA_D21 FBVDDQ
A19 L24
FBA_D23 FBA_D22 FBVDDQ
C19 L26
FBA_D24 FBA_D23 FBVDDQ
B24 M21
FBA_D25 FBA_D24 FBVDDQ
C23 N21
FBA_D26 FBA_D25 FBVDDQ
A25 R21
FBA_D27 FBA_D26 FBVDDQ
A24 T21
FBA_D28 FBA_D27 FBVDDQ
A21 V21
FBA_D29 FBA_D28 FBVDDQ
B21 W21
FBA_D30 FBA_D29 FBVDDQ
C20
FBA_D31 FBA_D30
C21
FBA_D32 FBA_D31
R22
FBA_D33 FBA_D32
R24 C27
FBA_D34 T22
FBA_D33 FBA_CMD0
C26 FBA_CMD1
FBA_CMD0
1
88 TP8414 TPAD14-OP-GP SG
FBA_D35 FBA_D34 FBA_CMD1
R23 E24
FBA_D36 FBA_D35 FBA_CMD2 FBA_CMD2 88
N25 F24
FBA_D37 FBA_D36 FBA_CMD3 FBA_CMD3 88
N26 D27
FBA_D38 N23
FBA_D37 SG FBA_CMD4
D26
FBA_CMD4 88,89
FBA_D39 FBA_D38 FBA_CMD5 FBA_CMD5 88,89
C N24 F25 C
FBA_D40 FBA_D39 FBA_CMD6 FBA_CMD6 88,89
V23 F26
FBA_D41 FBA_D40 FBA_CMD7 FBA_CMD7 88,89
V22 F23
FBA_D42 FBA_D41 FBA_CMD8 FBA_CMD8 88,89
T23 G22
FBA_D43 FBA_D42 FBA_CMD9 FBA_CMD9 88,89
U22 G23
FBA_D44 FBA_D43 FBA_CMD10 FBA_CMD10 88,89
Y24 G24
FBA_D45 FBA_D44 FBA_CMD11 FBA_CMD11 88,89
AA24 F27
FBA_D46 FBA_D45 FBA_CMD12 FBA_CMD12 88,89
Y22 G25
FBA_D47 FBA_D46 FBA_CMD13 FBA_CMD13 88,89
AA23 G27
FBA_D48 FBA_D47 FBA_CMD14 FBA_CMD14 88,89
AD27 G26
FBA_D49 FBA_D48 FBA_CMD15 FBA_CMD15 88,89
AB25 M24
FBA_D50 FBA_D49 FBA_CMD16 FBA_CMD16 89 TP8415
AD26 M23 FBA_CMD17 1 TPAD14-OP-GP
FBA_D51 FBA_D50 FBA_CMD17
AC25 K24 1D5V_VGA_S0
FBA_D52 FBA_D51 FBA_CMD18 FBA_CMD18 89
AA27 K23
FBA_D53 FBA_D52 FBA_CMD19 FBA_CMD19 89
AA26 M27
FBA_D54 FBA_D53 FBA_CMD20 FBA_CMD20 88,89 R8401
W26 M26
FBA_D55 FBA_D54 FBA_CMD21 FBA_CMD21 88,89 FB_CAL_PD_VDDQ
Y25 M25 1 SG 2 D22
FBA_D56 FBA_D55 FBA_CMD22 FBA_CMD22 88,89 FB_CAL_PD_VDDQ
R26 K26 40D2R2F-GP
FBA_D57 FBA_D56 FBA_CMD23 FBA_CMD23 88,89
T25 K22
FBA_D58 FBA_D57 FBA_CMD24 FBA_CMD24 88,89 FB_CAL_PU_GND
N27 J23 C24
FBA_D59 FBA_D58 FBA_CMD25 FBA_CMD25 88,89 FB_CAL_PU_GND
R27 J25
FBA_D60 FBA_D59 FBA_CMD26 FBA_CMD26 88,89
V26 J24
FBA_D61 FBA_D60 FBA_CMD27 FBA_CMD27 88,89 FB_CAL_TERM_GNDB25
V27 K27
FBA_D62 FBA_D61 FBA_CMD28 FBA_CMD28 88,89 FB_CAL_TERM_GND
W27 K25
FBA_D63 FBA_D62 FBA_CMD29 FBA_CMD29 88,89
W25 J27
FBA_D63 FBA_CMD30 FBA_CMD30 88,89TP8401
J26 FBA_CMD31 1 TPAD14-OP-GP N13M-NS-S-A1-GP
FBA_CMD31
D19
88 FBA_DQM0 FBA_DQM0

2
D14
88 FBA_DQM1 FBA_DQM1
C17 1D5V_VGA_S0 R8405 R8404
88 FBA_DQM2 FBA_DQM2
C22 42D2R2F-GP 51D1R2F-GP
88 FBA_DQM3 FBA_DQM3
89 FBA_DQM4
P24
FBA_DQM4 SG SG
W24
89 FBA_DQM5 FBA_DQM5

1
AA25
89 FBA_DQM6 FBA_DQM6 FBA_DEBUG0 R8424 1
U25 F22 DY 2 60D4R2F-GP
89 FBA_DQM7 FBA_DQM7 FBA_DEBUG0 FBA_DEBUG1
J22 1 DY 2 60D4R2F-GP
FBA_DEBUG1 R8428
E19
88 FBA_DQS_WP0 FBA_DQS_WP0
C15
88 FBA_DQS_WP1 FBA_DQS_WP1
B16 D24
88 FBA_DQS_WP2 FBA_DQS_WP2 FBA_CLK0 FBA_CLK0 88
B22 D25
B 88 FBA_DQS_WP3 FBA_DQS_WP3 FBA_CLK0# FBA_CLK0# 88 B
R25 N22
89 FBA_DQS_WP4 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1 89
W23 M22
89 FBA_DQS_WP5 FBA_DQS_WP5 FBA_CLK1# FBA_CLK1# 89
AB26
89 FBA_DQS_WP6 FBA_DQS_WP6
T26
89 FBA_DQS_WP7 FBA_DQS_WP7

F19 D18
88 FBA_DQS_RN0 FBA_DQS_RN0 FBA_WCK1
C14 C18
88 FBA_DQS_RN1 FBA_DQS_RN1 FBA_WCK1#
A16 D17
88 FBA_DQS_RN2 FBA_DQS_RN2 FBA_WCK23
A22 D16
88 FBA_DQS_RN3 FBA_DQS_RN3 FBA_WCK23#
P25 T24
89 FBA_DQS_RN4 FBA_DQS_RN4 FBA_WCK45
W22 U24
89 FBA_DQS_RN5 FBA_DQS_RN5 FBA_WCK45#
AB27 V24
89 FBA_DQS_RN6 FBA_DQS_RN6 FBA_WCK67
T27 V25
89 FBA_DQS_RN7 FBA_DQS_RN7 FBA_WCK67#

30ohm@100MHZ(ESR=0.01ohm)
F16 1D05V_VGA_S0
FB_PLLAVDD
P22 L8401
FB_PLLAVDD
GF119 FB_DLLAVDD
H22 FB_PLLVDD_16mil 1 (
SG ( 2

BLM18KG300TN1D-GP
GF117 FB_PLLAVDD
SC22U6D3V5MX-2GP

CHIP BEAD BLM18KG300TN1D MURATA

1

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C8414 C8413 C8435 C8431

SG SG SG SG
2

TPAD14-OP-GP TP8416 1 FB_VREF_PROBE D23

FB_VREF_PROBE
Near GPU.
N13M-NS-S-A1-GP X02_0615

Under GPU
One per Ball
A A

DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU Memory(2/5)
Size Document Number Rev
A2 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 84 of 106
5 4 3 2 1
 5 4 3 2 1

VGA1G
7 OF 14
4/14 IFPAB
10 OF 14

Vinafix.com
VGA1J
GF117 GF119
7/14 IFPEF
NC AC4
IFPA_TXC#
NC AC3 GF119
GF119 GF117 IFPA_TXC GF117
DVI-DL DVI-SL/HDMI DP
D AA6 NC D
IFPAB_RSET
NC Y3 NC I2CY_SDA I2CY_SDA J3
IFPA_TXD0# GF119 GF117 IFPE_AUX_I2CY_SDA#
NC Y4 NC I2CY_SCL I2CY_SCL J2
IFPA_TXD0 TP8506 IFPEF_PLVDD_J7 IFPE_AUX_I2CY_SCL
1 J7 NC
TPAD14-OP-GP TP8501 IFPAB_PLLVDD_V7 TPAD14-OP-GP IFPEF_PLLVDD
1 V7 NC
IFPAB_PLLVDD
NC AA2 NC TXC TXC J1
TPAD14-OP-GP TP8503 IFPAB_PLLVDD_W7 IFPA_TXD1# IFPE_L3#
1 W7 NC NC AA3 NC TXC TXC K1
IFPAB_PLLVDD IFPA_TXD1 TP8507 IFPEF_PLVDD_K7 IFPE_L3
1 K7 NC
TPAD14-OP-GP IFPEF_PLLVDD
K3
NC TXD0 TXD0 IFPE_L2#
NC AA1 NC K2
IFPA_TXD2# TXD0 TXD0 IFPE_L2
NC AB1
IFPA_TXD2
K6 NC NC TXD1 TXD1 M3
IFPEF_RSET IFPE_L1#
NC TXD1 TXD1 M2
IFPE_L1
NC AA5
IFPA_TXD3#
NC AA4 M1
IFPA_TXD3 NC TXD2 TXD2 IFPE_L0#
NC N1
TXD2 TXD2 IFPE_L0
SG
NC AB4
IFPB_TXC# IFPE
NC AB5
IFPB_TXC
GF119 GF117
TPAD14-OP-GP TP8504 1 IFPA_IOVDD_W6 W6 NC NC AB2 NC HPD_E HPD_E C2
IFPA_IOVDD IFPB_TXD4# GPIO18
NC AB3
TPAD14-OP-GP TP8505 IFPB_IOVDD_Y6 IFPB_TXD4
1 Y6
IFPB_IOVDD NC SG
GF119 GF117
NC AD2
IFPB_TXD5# TPAD14-OP-GP TP8508 IFPE_IOVDD_H6
NC AD3 1 H6 NC
IFPB_TXD5 IFPE_IOVDD
GF119
TPAD14-OP-GP TP8509 1 IFPE_IOVDD_J6 J6 NC GF117
IFPF_IOVDD DVI-DL DVI-SL/HDMI DP
NC AD1
IFPB_TXD6#
NC AE1 NC I2CZ_SDA H4
IFPB_TXD6 IFPF_AUX_I2CZ_SDA#
NC I2CZ_SCL H3
IFPF_AUX_I2CZ_SCL
NC AD5
IFPB_TXD7#
NC AD4 NC TXC J5
IFPB_TXD7 IFPF_L3#
NC TXC J4
IFPF_L3

NC TXD3 TXD0 K5
IFPF_L2#
NC TXD3 TXD0 K4
IFPF_L2
NC B3 NC TXD4 TXD1 L4
GPIO14 IFPF_L1#
C
IFPAB IFPF NC TXD4 TXD1
IFPF_L1
L3 C

N13M-NS-S-A1-GP NC TXD5 TXD2 M5

IFPF_L0#
NC TXD5 TXD2 M4
IFPF_L0

NC HPD_F F7
GPIO19

VGA1K 11 OF 14
3/14 DACA N13M-NS-S-A1-GP
X02_0622
GF119 GF117
GF117 GF119
DACA_VDD W5 NC NC B7
1

DACA_VDD I2CA_SCL
NC A7
R8503 TP8502 DACA_VREF I2CA_SDA
1 AE2 TSEN_VREF
TPAD14-OP-GP DACA_VREF
0R0402-PAD-2-GP
SG AF2 AE3
DACA_RSET NC NC DACA_HSYNC
NC AE4
2

DACA_VSYNC

SG
NC AG3
DACA_RED

NC AF4
DACA_GREEN

NC AF3
DACA_BLUE

N13M-NS-S-A1-GP VGA1H 8 OF 14
5/14 IFPC
IFPC
GF119 GF117
T6 NC GF117 GF119
IFPC_RSET
DVI/HDMI DP
B B
TPAD14-OP-GP TP8513 1 IFPC_PLLVDD_M7 M7 NC NC I2CW_SDA IFPC_AUX_I2CW_SDA# N5
TPAD14-OP-GP TP8514 IFPC_PLLVDD_N7 IFPC_PLLVDD
1 N7 NC NC I2CW_SCL N4
IFPC_PLLVDD IFPC_AUX_I2CW_SCL

NC TXC N3
IFPC_L3#
NC TXC N2
IFPC_L3
VGA1I 9 OF 14
SG NC TXD0 IFPC_L2#
R3
6/14 IFPD
NC TXD0 R2
IFPC_L2
GF119 GF117
NC TXD1 R1
GF117 GF119 IFPC_L1#
U6 NC NC TXD1 T1
IFPD_RSET IFPC_L1
DVI/HDMI DP
NC TXD2 T3
IFPC_L0#
NC TXD2 T2
TPAD14-OP-GP TP8510 IFPD_PLLVDD_T7 IFPC_L0
1 T7 NC NC I2CX_SDA IFPD_AUX_I2CX_SDA# P4
IFPD_PLLVDD
NC I2CX_SCL P3
TPAD14-OP-GP TP8511 IFPD_PLLVDD_R7 IFPD_AUX_I2CX_SCL
1 R7 NC
IFPD_PLLVDD TPAD14-OP-GP TP8515 IFPC_IOVDD_P6
1 P6 NC NC C3
IFPC_IOVDD GPIO15
NC TXC R5
IFPD_L3#
NC TXC R4
IFPD_L3 N13M-NS-S-A1-GP
NC TXD0 T5
IFPD_L2#
NC TXD0 T4
IFPD_L2

SG NC TXD1 IFPD_L1#
U4
IFPD NC TXD1 IFPD_L1
U3

NC TXD2 V4
IFPD_L0#
NC TXD2 V3
IFPD_L0

TPAD14-OP-GP TP8512 1 IFPD_IOVDD_R6 R6 GF119 NC D4

IFPD_IOVDD GPIO17

NC GF117

A N13M-NS-S-A1-GP A

DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
GPU_DP/LVDS/CRT/GPIO(3/5)
Size Document Number Rev
A2
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 85 of 106
5 4 3 2 1
 5 4 3 2 1

1.05V +/- 3%
150mA 3D3V_VGA_S0

(180 ohm ESR=0.2)

1D05V_VGA_S0 PLLVDD_PWR

3
4
L8601 RN8606
1 SG 2 SG SRN2K2J-1-GP
0R0603-PAD-2-GP
X02_0615 VGA1N 14 OF 14

2
1
Vinafix.com
8/14 MISC1
X02_0622 D9 SMBC_Therm_NV

SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP
1

1
C8608 C8609 C8604 C8605 I2CS_SCL SMBD_Therm_NV
D8
I2CS_SDA
SG SG SG SG

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
A9 GPU_LVDS_CLK1

2
VGA1M 13 OF 14 I2CC_SCL GPU_LVDS_DATA1
D B9 D
I2CC_SDA
9/14 XTAL_PLL

L6 TPAD14-OP-GP TP8607 1 THERMDN E12 GF117 GF119

CORE_PLLVDD THERMDN
M6 NC C9
SP_PLLVDD TPAD14-OP-GP TP8608 THERMDP I2CB_SCL
1 F12 NC C8
TP8606 VID_PLLVDD_N6 THERMDP I2CB_SDA
1 N6 GF119
TPAD14-OP-GP VID_PLLVDD
TPAD14-OP-GP TP8609 JTAG_TCK_VGA
NEAR GPU X7R, Under GPU. NC GF117
TPAD14-OP-GP TP8603
1
NV_TMS
AE5
JTAG_TCK
SG TPAD14-OP-GP TP8604
1
NV_TDI
AD6
JTAG_TMS
1 AE6
TPAD14-OP-GP TP8605 NV_TDO JTAG_TDI
1 AF6
VIDEO_CLK_XTAL_SS JTAG_TDO
A10 C10 N12P_XTAL_OUTBUFF JTAG_TRST# AG4 C6 NV_VID4
NV_VID4 92
XTAL_SSIN XTAL_OUTBUFF JTAG_TRST# GPIO0 NV_VID3
B2 NV_VID3 92

2
1
GPIO1
C11 B10 RN8602
SG GPIO2
D6
C7
XTAL_IN XTAL_OUT GPIO3
SG SRN10KJ-5-GP GPIO4
F9
N13M-NS-S-A1-GP A3 NV_VID1
NV_VID1 92

1
GPIO5 NV_VID2
A4 NV_VID2 92

1
R8605 GPIO6
SG B6

3
4
GPIO7 NV_THERM_OVERT
10KR2J-3-GP A6
GPIO8 NV_THERM_ALERT
SG R8604 GPIO9
F8
10KR2J-3-GP C5

2
27MHZ_OUT GPIO10 NV_VID0
E7 NV_VID0 92

2
27MHZ_IN GPIO11 PWR_LEVEL
D7
GPIO12 NV_VID5
B4 NV_VID5 92
GPIO13
C8611
GF117 GF119
2SG 1
NC D5
SC12P50V2JN-3GP GPIO16
NC E6
GPIO20
NC C4

2
GPIO21

SG R8607

1
0R0402-PAD-2-GP
82.30034.641 X8601
1MR2F-GP N13M-NS-S-A1-GP
2nd = 82.30034.651 XTAL-27MHZ-85-GP SG

1
R8606
SG
3rd = 82.30034.681 X02_0622

2
1

2
C GPIO12 C
C8610
2SG 1 27MHZ_OUT_R 1 - > normal mode
3D3V_VGA_S0
SC12P50V2JN-3GP 0 -> P8 mode 3D3V_VGA_S0

1 R8608 2 AC_PRESENT_R
100KR2J-1-GP 1 R8610 H_PROCHOT#_LL
SG 2
100KR2J-1-GP
D G S DY
D G S
X02_0615

D 6

G 5

S 4
Q8603

4
2N7002BKS-GP-U

D2

G1

S1
SG Q8604
84.2N702.E3F 3D3V_VGA_S0 ME2N7002DKW-G-GP DY

1 S

2 G

3 D

D1
S2

G2
84.2N702.F3F

3
1
S G D R8609 2nd = 84.2N702.A3F
10KR2J-3-GP S G D
SG 3rd = 84.DMN66.03F
PWR_LEVEL

2
27 OVER_CURRENT_P8#
PWR_LEVEL
5 H_PROCHOT#_L

3D3V_VGA_S0 PURE_HW_SHUTDOWN# 27,28,36

D
Q8602
2N7002BK-GP
R8641
RN8603
83 VGA_RST# 2 DY 1VGA_RST#_R G DY 84.07002.I31
NV_THERM_OVERT 1 4 0R2J-2-GP
Samsung (72.41646.00U) NV_THERM_ALERT 2 SG 3 2nd = 84.2N702.W31
Micron (72.41K26.00U)
3rd = 84.2N702.J31

S
SRN10KJ-5-GP
NV_THERM_OVERT
B B
3D3V_VGA_S0

3
4
RN8605
SRN4K7J-8-GP SG
X02_0615
Q8601
3D3V_VGA_S0

2
1
SMBC_Therm_NV 1 S D 6
SML1_CLK 20,27,28
3D3V_VGA_S0
SG G 5
2 G
SML1_DATA 20,27,28
1

3 D S 4
R8636
VGA1L 12 OF 14
DY 10KR2J-3-GP 2N7002BKS-GP-U
10/14 MISC2
84.2N702.E3F
2

SMBD_Therm_NV
2KR2F-3-GP

15KR2F-GP
10KR2F-2-GP

DY R8624 DY R8625 DY R8626

E10
VMON_IN0
F10 D12 ROM_CS# 3D3V_VGA_S0
VMON_IN1 ROM_CS#
2

B12 SUB_VENDOR
ROM_SI
A12 VGA_DEVICE
RAM_CFG[0] ROM_SO
D1 C12 SMB_ALT_ADDR
RAM_CFG[1] STRAP0 ROM_SCLK
D2 SG
1

RAM_CFG[2] STRAP1
E4 3D3V_VGA_S0
RAM_CFG[3] STRAP2
E3
PCIE_MAX_SPEED STRAP3 R8627
D3
STRAP4 SG SG R8617
10KR2F-2-GP
SG R8618
10KR2F-2-GP 10KR2F-2-GP
GF119
2

GF117

1
R8638
C1 NC DY
1

1
STRAP5
BUFRST#
D11 Micron DY R8640
10KR2F-2-GP
4K99R2F-L-GP

F6 D10 VGA_PGOOD R8631

SG DYR8633 R8635

2
A MULTI_STRAP_REF0_GND PGOOD 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP A
RAM_CFG[3]
Follow PUN-05935-001_V03 GF119
2

2
GF117
1

RAM_CFG[0]
F4 NC
RAM_CFG[1] PCIE_MAX_SPEED
MULTI_STRAP_REF1_GND R8639 RAM_CFG[2]
F5
CEC
E9 SG 10KR2F-2-GP
NC
1

1
MULTI_STRAP_REF2_GND DMB50
SAMSUNG
2

2
R8630
DY SGR8632 R8634
N13M-NS-S-A1-GP 10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP Wistron Corporation
SG R8637 SGR8623 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2

10KR2F-2-GP 10KR2F-2-GP
N13x GPUs do not support CEC.Leave the CEC pin as NC Taipei Hsien 221, Taiwan, R.O.C.

1
Title
GPU_POWER(4/5)
Size Document Number Rev
A2
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 86 of 106
5 4 3 2 1
 5 4 3 2 1

VGA_CORE

Under GPU
VGA1F 6 OF 14
13/14 GND VGA1E 5 OF 14
A2 M13
Vinafix.com
11/14 NVVDD
GND GND
AB17 GND GND M15 K10 VDD
AB20 GND GND M17 K12 VDD
AB24 N10 C8715 C8714 C8713 C8711 C8710 C8709 C8701 C8702 C8703 C8704 C8705 C8706 C8707 C8708 K14
GND GND VDD
D AC2 GND GND N12 K16 VDD D

1
AC22 N14 K18

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
GND GND VDD
AC26
AC5
GND GND N16
N18
SG SG SG SG SG SG SG SG SG SG SG SG SG SG L11
L13
VDD

2
GND GND VDD
AC8 GND GND P11 L15 VDD
AD12 GND GND P13 L17 VDD
AD13 GND GND P15 M10 VDD
A26 GND GND P17 M12 VDD
AD15 GND GND P2 M14 VDD
AD16
AD18
GND GND P23
P26 X02_0615
M16
M18
VDD SG
GND GND VDD
AD19 GND GND P5 N11 VDD
AD21 GND GND R10 N13 VDD
AD22 GND GND R12 N15 VDD
AE11 GND GND R14 N17 VDD
AE14 GND GND R16 P10 VDD
AE17 GND GND R18 P12 VDD
C8731 C8730
AE20
AB11
GND SG GND T11
T13
P14
P16
VDD

SC22U6D3V5MX-2GP
GND GND C8712 C8719 C8718 C8717 C8716 VDD

1
AF1 T15 P18

SC47U6D3V5MX-1-GP
GND GND VDD

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP
AF11
AF14
GND GND T17
U10
SG SG SG SG SG SG SG R11
R13
VDD

2
GND GND VDD
AF17 GND GND U12 R15 VDD
AF20 GND GND U14 R17 VDD
AF23 GND GND U16 T10 VDD
AF5 GND GND U18 T12 VDD
AF8 GND GND U2 T14 VDD
AG2 GND GND U23 T16 VDD
AG26 GND GND U26 T18 VDD
C AB14 U5 U11 C
GND GND VDD
B1 V11 U13
B11
GND GND
V13
NEAR GPU U15
VDD
GND GND VDD
B14 GND GND V15 U17 VDD
B17 GND GND V17 V10 VDD
B20 GND GND Y2 V12 VDD
B23 GND GND Y23 V14 VDD
B27 GND GND Y26 V16 VDD
B5 GND GND Y5 V18 VDD
B8 GND
E11 GND
E14 N13M-NS-S-A1-GP
GND
E17 GND
E2 GND
E20 GND
E22 GND
E25 GND
E5 GND
E8 GND
H2 GND
H23 GND
H25 GND
H5 GND
K11 GND
K13 GND
K15 GND 3D3V_VGA_S0
K17 GND
L10 VGA1C 3 OF 14
GND
B
L12 GND 14/14 XVDD/VDD33 X02_0615 B
L14 GND
L16 GND AD10 NC#AD10 VDD33 G10
L18 GND AD7 NC#AD7 VDD33 G12
L2 B19 G8 C8732 C8733
GND NC#B19 VDD33
L23 G9

SC4D7U6D3V3KX-GP
GND TP8701 VDD33

1
L25 C8734 C8735 C8739 C8736

SC1U16V3KX-5GP
GND

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
3V3AUX_F11
L5
M11
GND GND AA7
AB7
1 F11 3V3AUX SG SG SG SG SG SG

2
GND GND
TPAD14-OP-GP

N13M-NS-S-A1-GP

CONFIGURABLE
SG
POWER CHANNELS
* nc on substrate

G1
Under GPU NEAR GPU
NC#G1
G2 NC#G2 One per pin
G3 NC#G3
G4 NC#G4
G5 NC#G5
G6 NC#G6
G7 NC#G7

V1 NC#V1 DMB50
A V2 NC#V2 A
V5 NC#V5
V6 NC#V6 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
W1 Taipei Hsien 221, Taiwan, R.O.C.
NC#W1
W2 NC#W2
W3 Title
NC#W3
W4 NC#W4 GPU_DPPWR/GND(5/5)
Size Document Number Rev
N13M-NS-S-A1-GP A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 87 of 106

5 4 3 2 1
 5 4 3 2 1

MODE D

1D5V_VGA_S0 1D5V_VGA_S0
VRAM1 VRAM2
FBA_D[63..0] 84,89 FBA_D[63..0] 84,89
K8 E3 FBA_D0 K8 E3 FBA_D23
Vinafix.com K2
N1
VDD
VDD
VDD
DQL0
DQL1
DQL2
F7
F2
FBA_D4
FBA_D3
K2
N1
VDD
VDD
VDD
DQL0
DQL1
DQL2
F7
F2
FBA_D16
FBA_D20
R9 F8 FBA_D5 R9 F8 FBA_D18
VDD DQL3 FBA_D1 VDD DQL3 FBA_D22
D B2 VDD DQL4 H3 B2 VDD DQL4 H3 D
D9 H8 FBA_D6 D9 H8 FBA_D19
VDD DQL5 FBA_D2 VDD DQL5 FBA_D21
G7 VDD DQL6 G2 G7 VDD DQL6 G2
R1 H7 FBA_D7 R1 H7 FBA_D17
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D7 FBA_D11 D7 FBA_D31
DQU0 FBA_D12 DQU0 FBA_D25
A8 VDDQ DQU1 C3 A8 VDDQ DQU1 C3
A1 C8 FBA_D10 A1 C8 FBA_D30
VDDQ DQU2 FBA_D13 VDDQ DQU2 FBA_D24
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
C9 A7 FBA_D9 C9 A7 FBA_D28
VDDQ DQU4 FBA_D15 VDDQ DQU4 FBA_D26
D2 VDDQ DQU5 A2 D2 VDDQ DQU5 A2
E9 B8 FBA_D8 E9 B8 FBA_D29
VDDQ DQU6 FBA_D14 VDDQ DQU6 FBA_D27
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 FBA_DQS_W P1 84 H2 VDDQ DQSU C7 FBA_DQS_W P3 84
DQSU# B7 FBA_DQS_RN1 84 DQSU# B7 FBA_DQS_RN3 84
FBA_VREF_0 H1 FBA_VREF_0 H1
VREFDQ VREFDQ
M8 VREFCA DQSL F3 FBA_DQS_W P0 84 M8 VREFCA DQSL F3 FBA_DQS_W P2 84
VRAM_CH_A_ZQ_1 L8 G3 VRAM_CH_A_ZQ_2 L8 G3
1 ZQ DQSL# FBA_DQS_RN0 84 ZQ DQSL# FBA_DQS_RN2 84

1
ODT K1 FBA_CMD2 84 ODT K1 FBA_CMD2 84
R8801 84,89 FBA_CMD9 N3 A0 84,89 FBA_CMD9 N3 A0
SG 84,89 FBA_CMD11 P7 R8802 SG 84,89 FBA_CMD11 P7
243R2F-2-GP A1 243R2F-2-GP A1
84,89 FBA_CMD8 P3 A2 CS# L2 FBA_CMD0 84 84,89 FBA_CMD8 P3 A2 CS# L2 FBA_CMD0 84
84,89 FBA_CMD25 N2 T2 FBA_CMD5 84,89 84,89 FBA_CMD25 N2 T2 FBA_CMD5 84,89
2

2
A3 RESET# A3 RESET#
84,89 FBA_CMD10 P8 A4 84,89 FBA_CMD10 P8 A4
84,89 FBA_CMD24 P2 A5 84,89 FBA_CMD24 P2 A5
84,89 FBA_CMD22 R8 A6 NC#T7 T7 FBA_CMD4 84,89 84,89 FBA_CMD22 R8 A6 NC#T7 T7 FBA_CMD4 84,89
84,89 FBA_CMD7 R2 A7 NC#L9 L9 84,89 FBA_CMD7 R2 A7 NC#L9 L9
C T8 L1 T8 L1 C
84,89 FBA_CMD21 A8 NC#L1 84,89 FBA_CMD21 A8 NC#L1
84,89 FBA_CMD6 R3 A9 NC#J9 J9 84,89 FBA_CMD6 R3 A9 NC#J9 J9
84,89 FBA_CMD29 L7 A10/AP NC#J1 J1 84,89 FBA_CMD29 L7 A10/AP NC#J1 J1
84,89 FBA_CMD23 R7 A11 84,89 FBA_CMD23 R7 A11
84,89 FBA_CMD28 N7 A12/BC# 84,89 FBA_CMD28 N7 A12/BC#
84,89 FBA_CMD20 T3 A13 VSS J8 84,89 FBA_CMD20 T3 A13 VSS J8
84,89 FBA_CMD14 M7 NC#M7 VSS M1 84,89 FBA_CMD14 M7 NC#M7 VSS M1
SG VSS M9 SG VSS M9
VSS J2 VSS J2
84,89 FBA_CMD12 M2 BA0 VSS P9 84,89 FBA_CMD12 M2 BA0 VSS P9
84,89 FBA_CMD27 N8 BA1 VSS G8 84,89 FBA_CMD27 N8 BA1 VSS G8
84,89 FBA_CMD26 M3 BA2 VSS B3 84,89 FBA_CMD26 M3 BA2 VSS B3
VSS T1 VSS T1
R8807 1 SG 2 162R2F-GP A9 A9
VSS VSS
84 FBA_CLK0 J7 CK VSS T9 84 FBA_CLK0 J7 CK VSS T9
84 FBA_CLK0# K7 CK# VSS E1 84 FBA_CLK0# K7 CK# VSS E1
VSS P1 VSS P1
84 FBA_CMD3 K9 CKE 84 FBA_CMD3 K9 CKE
VSSQ G1 VSSQ G1
VSSQ F9 VSSQ F9
84 FBA_DQM1 D3 DMU VSSQ E8 84 FBA_DQM3 D3 DMU VSSQ E8
84 FBA_DQM0 E7 DML VSSQ E2 84 FBA_DQM2 E7 DML VSSQ E2
VSSQ D8 VSSQ D8
VSSQ D1 VSSQ D1
84,89 FBA_CMD13 L3 WE# VSSQ B9 84,89 FBA_CMD13 L3 WE# VSSQ B9
84,89 FBA_CMD15 K3 CAS# VSSQ B1 84,89 FBA_CMD15 K3 CAS# VSSQ B1
84,89 FBA_CMD30 J3 RAS# VSSQ G9 84,89 FBA_CMD30 J3 RAS# VSSQ G9
1D5V_VGA_S0
B H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP B

1
72.52G63.A0U 72.52G63.A0U
R8803
1K33R2F-GP SG
1D5V_VGA_S0

2
FBA_VREF_0
follow NV FAE suggest

1
C8805 C8806 C8807
FOR VRAM1

1
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C8808 C8802 R8804

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SCD01U50V2KX-1GP 1K33R2F-GP FBA_CMD2 R8805 2 10KR2J-3-GP

SCD1U10V2KX-5GP

SG
1

ODT 1
SC4D7U6D3V3KX-GP

SG SG
1

1
1

SG C8801 SG C8803

2
FBA_CMD3 R8806 2 10KR2J-3-GP
2

SG DY SG SG CKE 1 SG
2

2
2

FBA_CMD5 R8808 1 SG 2 10KR2J-3-GP

RST
1D5V_VGA_S0
CLOSE TO THE MEMORY
1D5V_VGA_S0
C8813 C8814 C8815 C8816
FOR VRAM2 DG requires 4x0.1uF and 8x1.0uF per
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
SC1U6D3V3KX-2GP

DMB50
1

C8810
A VRAM chip A
SCD1U16V2KX-3GP

SG SG C8811 SG DY
SCD1U16V2KX-3GP
SG SG Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

DY C8809 Taipei Hsien 221, Taiwan, R.O.C.
SC10U6D3V3MX-GP
2

Title

CLOSE TO THE MEMORY GPU-VRAM1,2 (1/4)

Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 88 of 106

5 4 3 2 1
 5 4 3 2 1

1D5V_VGA_S0 1D5V_VGA_S0
VRAM3 VRAM4
FBA_D[63..0] 84,88 FBA_D[63..0] 84,88
K8 E3 FBA_D33 K8 E3 FBA_D43
VDD DQL0 FBA_D39 VDD DQL0 FBA_D44
K2 VDD DQL1 F7 K2 VDD DQL1 F7
N1 F2 FBA_D35 N1 F2 FBA_D40
VDD DQL2 FBA_D36 VDD DQL2 FBA_D45
R9 F8 R9 F8
B2
D9
Vinafix.com
VDD
VDD
VDD
DQL3
DQL4
DQL5
H3
H8
FBA_D34
FBA_D38
B2
D9
VDD
VDD
VDD
DQL3
DQL4
DQL5
H3
H8
FBA_D41
FBA_D46
G7 G2 FBA_D32 G7 G2 FBA_D42
VDD DQL6 FBA_D37 VDD DQL6 FBA_D47
D R1 VDD DQL7 H7 R1 VDD DQL7 H7 D
N9 VDD N9 VDD
D7 FBA_D59 D7 FBA_D51
DQU0 FBA_D60 DQU0 FBA_D52
A8 VDDQ DQU1 C3 A8 VDDQ DQU1 C3
A1 C8 FBA_D58 A1 C8 FBA_D50
VDDQ DQU2 FBA_D61 VDDQ DQU2 FBA_D53
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
C9 A7 FBA_D57 C9 A7 FBA_D49
VDDQ DQU4 FBA_D63 VDDQ DQU4 FBA_D55
D2 VDDQ DQU5 A2 D2 VDDQ DQU5 A2
E9 B8 FBA_D56 E9 B8 FBA_D48
VDDQ DQU6 FBA_D62 VDDQ DQU6 FBA_D54
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 FBA_DQS_W P7 84 H2 VDDQ DQSU C7 FBA_DQS_W P6 84
DQSU# B7 FBA_DQS_RN7 84 DQSU# B7 FBA_DQS_RN6 84
FBA_VREF_1 H1 FBA_VREF_1 H1
VREFDQ VREFDQ
M8 VREFCA DQSL F3 FBA_DQS_W P4 84 M8 VREFCA DQSL F3 FBA_DQS_W P5 84
VRAM_CH_A_ZQ_3 L8 G3 VRAM_CH_A_ZQ_4 L8 G3
ZQ DQSL# FBA_DQS_RN4 84 ZQ DQSL# FBA_DQS_RN5 84

ODT K1 FBA_CMD18 84 ODT K1 FBA_CMD18 84

1

1
84,88 FBA_CMD9 N3 A0 84,88 FBA_CMD9 N3 A0
84,88 FBA_CMD11 P7 A1 84,88 FBA_CMD11 P7 A1
SG R8901 84,88 FBA_CMD8 P3 L2 FBA_CMD16 84 R8904 SG 84,88 FBA_CMD8 P3 L2 FBA_CMD16 84
243R2F-2-GP84,88 FBA_CMD25 A2 CS# 243R2F-2-GP A2 CS#
N2 A3 RESET# T2 FBA_CMD5 84,88 84,88 FBA_CMD25 N2 A3 RESET# T2 FBA_CMD5 84,88
84,88 FBA_CMD10 P8 84,88 FBA_CMD10 P8
2

2
A4 A4
84,88 FBA_CMD24 P2 A5 84,88 FBA_CMD24 P2 A5
84,88 FBA_CMD22 R8 A6 NC#T7 T7 FBA_CMD4 84,88 84,88 FBA_CMD22 R8 A6 NC#T7 T7 FBA_CMD4 84,88
84,88 FBA_CMD7 R2 A7 NC#L9 L9 84,88 FBA_CMD7 R2 A7 NC#L9 L9
84,88 FBA_CMD21 T8 A8 NC#L1 L1 84,88 FBA_CMD21 T8 A8 NC#L1 L1
84,88 FBA_CMD6 R3 A9 NC#J9 J9 84,88 FBA_CMD6 R3 A9 NC#J9 J9
84,88 FBA_CMD29 L7 A10/AP NC#J1 J1 84,88 FBA_CMD29 L7 A10/AP NC#J1 J1
C R7 R7 C
84,88 FBA_CMD23 A11 84,88 FBA_CMD23 A11
84,88 FBA_CMD28 N7 A12/BC# 84,88 FBA_CMD28 N7 A12/BC#
84,88 FBA_CMD20 T3 A13 VSS J8 84,88 FBA_CMD20 T3 A13 VSS J8
84,88 FBA_CMD14 M7 NC#M7 VSS M1 84,88 FBA_CMD14 M7 NC#M7 VSS M1
SG VSS M9 SG VSS M9
VSS J2 VSS J2
84,88 FBA_CMD12 M2 BA0 VSS P9 84,88 FBA_CMD12 M2 BA0 VSS P9
84,88 FBA_CMD27 N8 BA1 VSS G8 84,88 FBA_CMD27 N8 BA1 VSS G8
84,88 FBA_CMD26 M3 BA2 VSS B3 84,88 FBA_CMD26 M3 BA2 VSS B3
VSS T1 VSS T1
R8908 1 SG 2 162R2F-GP A9 A9
VSS 1D5V_VGA_S0 VSS
84 FBA_CLK1 J7 CK VSS T9 84 FBA_CLK1 J7 CK VSS T9
84 FBA_CLK1# K7 CK# VSS E1 84 FBA_CLK1# K7 CK# VSS E1
VSS P1 VSS P1

1
84 FBA_CMD19 K9 CKE 84 FBA_CMD19 K9 CKE
G1 R8902 G1
VSSQ 1K33R2F-GP VSSQ
VSSQ F9 SG VSSQ F9
84 FBA_DQM7 D3 DMU VSSQ E8 84 FBA_DQM6 D3 DMU VSSQ E8
84 FBA_DQM4 E7 E2 84 FBA_DQM5 E7 E2

2
DML VSSQ DML VSSQ
VSSQ D8 VSSQ D8
D1 FBA_VREF_1 D1
VSSQ VSSQ
84,88 FBA_CMD13 L3 WE# VSSQ B9 84,88 FBA_CMD13 L3 WE# VSSQ B9

1
84,88 FBA_CMD15 K3 CAS# VSSQ B1 84,88 FBA_CMD15 K3 CAS# VSSQ B1

1
84,88 FBA_CMD30 J3 G9 C8902 R8903 84,88 FBA_CMD30 J3 G9
RAS# VSSQ SCD01U50V2KX-1GP 1K33R2F-GPSG RAS# VSSQ
SG

2
H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP

2
72.52G63.A0U 72.52G63.A0U
B B

follow NV FAE suggest

1D5V_VGA_S0

FBA_CMD18 R8909 1 SG 2 10KR2J-3-GP

X02_0615 C8905 C8906 C8907 C8908
ODT
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

FBA_CMD19 R8910 1 SG 2 10KR2J-3-GP

CKE
FOR VRAM3
1

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C8901 C8903
SG SG SG SG SG SG
2

1D5V_VGA_S0

C8909
SC4D7U6D3V3KX-GP

1D5V_VGA_S0
CLOSE TO THE MEMORY
1

SG
DMB50
2

A C8913 C8915 C8916 A

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

Wistron Corporation
1

1
SCD1U16V2KX-3GP

C8910
SG SG C8911 SG DY C8914 SG SG CLOSE TO THE MEMORY 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
FOR VRAM4 Taipei Hsien 221, Taiwan, R.O.C.
2

Title

GPU-VRAM3,4 (2/4)
Size Document Number Rev
A3 A00
X02_0615 BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 89 of 106

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 90 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM7,8 (3/4)
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 91 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_vga_core

Vinafix.com
D D

V-BOOT VID0 VID1 VID2 VID3 VID4 VID5 VID6

0.9000V 0 0 0 0 1 1 0

3D3V_S5

1
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP
DY SG SG DY DY DY DY
PR9201
PR9202 PR9203 PR9204 PR9205 PR9206 PR9207

2
PWR_VGA_CORE_VID6
NV_VID5 PR9215 1 SG 2 0R2J-2-GP PWR_VGA_CORE_VID5
86 NV_VID5
NV_VID4 PR9216 1 SG 2 0R2J-2-GP PWR_VGA_CORE_VID4
86 NV_VID4
NV_VID3 PR9217 1 SG 2 0R2J-2-GP PWR_VGA_CORE_VID3
86 NV_VID3
NV_VID2 PR9218 1 SG 2 0R2J-2-GP PWR_VGA_CORE_VID2 X02_0626
86 NV_VID2
NV_VID1 PR9241 1 SG 2 0R2J-2-GP PWR_VGA_CORE_VID1
86 NV_VID1
NV_VID0 PR9242 1 SG 2 0R2J-2-GP PWR_VGA_CORE_VID0
86 NV_VID0
1

1
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP
SG DY DY SG SG SG SG
PR9208 PR9209 PR9210 PR9211 PR9212 PR9213 PR9214
2

2
0322_X01

5V_S5

83.R5003.C8F
Please confirm with H/W for resistor pull high and pull GND 2nd = 83.R5003.G8H
3rd = 83.R5003.H8H

1
4th = 83.5R003.08F X02_0626
PD9201 PR9220
SG 10R2J-2-GP
93 DGPU_PWR_EN 2 DY1

2
CH551H-30PT-GP DCBATOUT

PR9219
3D3V_VGA_S0 1 SG 2 PWR_VGA_CORE_VR_ON
C C

1
10KR2J-3-GP
PC9201 SG PC9220 PC9218 PC9222 PC9217 PC9221
SCD1U25V3KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
2

SCD1U50V3KX-GP
PC9202

PWR_VGA_CORE_VCC
SC1U10V2KX-1GP SG SG
SG
DY SG SG
Design Current = 25A

1
OCP>31A

5
6
7
8

5
6
7
8
3D3V_S0

D
D
D
D

D
D
D
D
PU9202 PU9203
GND_3211 FDMS7682-GP FDMS7682-GP

1
VGA_CORE
SG 84.07682.A37 SG 84.07682.A37
2ND = 84.00462.037 2ND = 84.00462.037

32
31
30
29
28
27
26
25
PR9221 PU9201

G
DY 4 4

S
S
S

S
S
S
SG 10KR2J-3-GP

EN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GND_3211 2 1 PC9203

3
2
1

3
2
1
SC1KP50V2KX-1GP PR9240
0R2J-2-GP PC9211 X02_0621
PR9222 1 SG 24 SG SCD22U25V3KX-GP
22,27,93 DGPU_PWROK PWRGD VCC PWR_VGA_CORE_BOOT PWR_VGA_CORE_BOOT_R PWR_VGA_CORE_UG
1 DY 2 2 23 1 SG 2 1 2
3
IMON
CLKEN#
BST
DRVH
22 PWR_VGA_CORE_UG
PL9201 RF
66K5R2F-GP PWR_VGA_CORE_FBRTN 4 21 PWR_VGA_CORE_SW PWR_VGA_CORE_SW 1 2
PWR_VGA_CORE_FB 5
FBRTN SW
20 5V_S0
SG
FB PVCC

PC9219
SCD1U25V3KX-GP
PWR_VGA_CORE_COMP PWR_VGA_CORE_LG IND-D22UH-28-GP
6 19 A00_0727
SC100P50V2JN-3GP

COMP DRVL

PT9204

PT9205

PT9203
7 18 68.R2210.10N
SC22P50V2JN-4GP

5V_S0 GPU PGND

SE330U2VDM-L-GP

SE330U2VDM-L-GP

SE330U2VDM-L-GP
SG 1 SG 2 PWR_VGA_CORE_ILIM 8 17
ILIM GND
1

5
6
7
8

5
6
7
8

2
PR9225 2K49R2F-GP 33 SG PU9204 PU9205

CSCOMP
GND
1

D
D
D
D

D
D
D
D

EC9201
SCD1U10V2KX-5GP

EC9202
SCD1U16V2KX-3GP

EC9203
SCD1U16V2KX-3GP

EC9204
SCD1U10V2KX-5GP
PC9204 SG X01_0426 PC9212 FDMS0309AS-GP FDMS0309AS-GP
DY SG SG SG DY SG SG DY

CSREF
RAMP
LLINE

CSFB
PC9206 SC2D2U10V3KX-1GP 84.00309.037 84.00309.037 PG9206 PG9207

IREF
RPM
2

1
2ND = 84.00166.037 2ND = 84.00166.037

RT
SG SG
2

PC9205 PWR_VGA_CORE_CSCOMP

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
1

1
SC470P50V2KX-3GP

G
SG SG 4 4

9
10
11
12
13
14
15
16

S
S
S

S
S
S
1 2 1 2 1 2 ADP3211MNR2G-GP
PWR_VGA_CORE_FB_L

SG 74.03211.033

3
2
1

3
2
1
PR9223 PR9224 GND_3211

2
1KR2F-3-GP 20KR2F-L-GP PWR_VGA_CORE_IREF

PWR_VGA_CORE_LG

PWR_VGA_CORE_LG
PWR_VGA_CORE_RPM
PWR_VGA_CORE_RT

PWR_VGA_CORE_CSCOMP
PWR_VGA_CORE_CSREF
PWR_VGA_CORE_FB_R

PWR_VGA_CORE_LLINE

PWR_VGA_CORE_CSFB
PWR_VGA_CORE_RAMP

PR9228
1 SG 2 PWR_VGA_CORE_CSCOMP_R
1

PR9229 PR9230
80K6R2F-GP
2

PR9235 69.60029.001 X02_0626

PR9226 PR9227 SG SG SG SG PR9231 NTC-220K-2-GP 2nd = 69.60028.001
191KR2F-1-GP

300KR2F-L-GP

0R0402-PAD-2-GP 0R0402-PAD-2-GP 422KR2F-1-GP

2

PR9237 PR9238
1

1 SG 2 1 SG 2 1 2 PWR_VGA_CORE_L_L
SG
PWR_VGA_CORE_RAMP_1

A00_0803 PR9236
76K8R2D-GP 174KR2F-GP 174KR3F-GP
1

1
SC330P50V2KX-3GP
PR9233 SG SG PC9209 SG
GND_3211 20KR2F-L-GP PC9210
X02_0626 SC680P50V2KX-2GP
2

2
B B
2

DCBATOUT
X02_0626
1

1 SG 2
PR9234 SG
PR9232 20KR2F-L-GP
1KR2F-3-GP
2
1

SG
PC9207
NVGND_SENSE

PWR_VGA_CORE_CSCOMP
NVVDD_SENSE

SC1KP50V2KX-1GP
2

SG
1

GND_3211 PC9208
SC1KP50V2KX-1GP
2

83 NVGND_SENSE NVVDD_SENSE 83 A00_0803

GND_3211
PR9239
1 2
Please confirm on H/W side whether have resistor pull high and pull GND by 100 ohm
0R0402-PAD-2-GP
GND_3211

A A

DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ADP3211+VGA_CORE
Size Document Number Rev
A1 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 92 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_3p3v_vga, 1p8v_vga, 1p5v_vga, 1v_vga

3D3V_S0 to 3D3V_VGA_S0 Transfer
3D3V_VGA_S0

3D3V_S0 PR93011 DY 20R2J-2-GP

S
DMP2130L-7-GP
Vinafix.com
84.02130.031
2nd = 84.00102.031

1
PR9316 PQ9302 D 3rd = 84.03413.A31

D
D SG 10KR2F-2-GP SG PC9324 D

G
SCD1U16V2KX-3GP SG 3D3V_VGA discharge
4th = 84.02301.G31

2
1

G
PR9319
1 SG 2 PQ9302_G
10KR2F-2-GP

PR9319_1

2
X02_0615

D 6

G 5

S 4
PR9314
PQ9303 SG 470R2J-2-GP
2N7002BKS-GP-U SG

1 S

2 G

3 D
84.2N702.E3F

1
PR9337
1 SG 2 3.3V_RUN_VGA_1
19,45,46,47 RUNPWROK 100KR2J-1-GP

PR9321
3D3V_S0 1 DY 2

10KR2J-3-GP
DGPU_PWR_EN

22 DGPU_PWR_EN#

NV do not need 1.8V

G

PQ9304

S D DGPU_PWR_EN 92

SG
2N7002BK-GP
C 84.07002.I31 C
X02_0615

DGPU_PWR_EN#
dGPU mode L
IGPU H

IGPU with BACO L

change low Rds(on) MOSFET

1D5V_VGA_S0 1D5V_S3 1D5V_VGA_S0 1D05V_VGA_S0
PU9305
SI4178DY-T1-GE3-GP RF
AO4468, SO-8 8 D S 1
7 D S 2 3D3V_VGA_S0 should ramp-up before VGA_Core
Id=?A, Qg=9~12nC
2

6 D S 3 2
1

EC9304
SCD1U16V2KX-3GP

EC9305
SCD1U16V2KX-3GP

EC9306
SCD1U10V2KX-5GP
Rdson=17.4~22m ohm D PC9332 SG SG VCCP_CPU 1D05V_VGA_S0
5
SG DY VGA_Core should ramp-up before 1D5V_VGA_S0
1

PC9327 84.04178.037 SG PU9306

RF
1

SG G 2nd = 84.04468.037 SC10U6D3V3MX-GP 1D5V_VGA_S0 should ramp-up before 1D05V_VGA_S0 SI4178DY-T1-GE3-GP

4

3rd = 84.02659.037 AO4468, SO-8 8 D S 1

SC10U6D3V3MX-GP
2

7 D S 2
Decap
Id=?A, Qg=9~12nC

2
6 D S 3

EC9301
SCD1U16V2KX-3GP

EC9302
SCD1U16V2KX-3GP

EC9303
SCD1U16V2KX-3GP
Rdson=17.4~22m ohm 5 D
SG DY PC9333 SG SG SG

1
PC9329 84.04178.037

1
B 1D5V_ENABLE_RC SG G 2nd = 84.04468.037 SC10U6D3V3MX-GP B

2
3rd = 84.02659.037

SC10U6D3V3MX-GP
2
PR9330
1 SG 2

0R2J-2-GP Discharge Circuit

1

1D05V_ENABLE_RC
3D3V_AUX_S5 PC9326 SG 1D5V_VGA_S0
SCD01U50V2KX-1GP PR9334
2

1 SG 2 1D5V_VGA_EN# 1 SG 2
PR9332 100KR2J-1-GP
Discharge Circuit
1

D G S 0R2J-2-GP

1
SG PR9336
83.R5003.C8F X02_0615 470R2J-2-GP 3D3V_AUX_S5 PC9328 SG 1D05V_VGA_S0
D 6

G 5

S 4

2nd = 83.R5003.G8H SCD01U50V2KX-1GP

2
PQ9305 15V_S5 SG 2 1D05V_VGA_EN#
3rd = 83.R5003.H8H 1
DIS_1D5V_VGA_S02

4th = 83.5R003.08F 2N7002BKS-GP-U SG 1D5V_VGA_EN# PR9333 100KR2J-1-GP

1
D G S
1 S

2 G

3 D

PD9301
84.2N702.E3F PR9338
2

83.R5003.C8F SG 470R2J-2-GP
G

D 6

G 5

S 4
92 DGPU_PWR_EN 2 DY1 S G D SG PR9331 PQ9307 2nd = 83.R5003.G8H X02_0615
15V_S5
100KR2J-1-GP 3rd = 83.R5003.H8H PQ9306

2
CH551H-30PT-GP 4th = 83.5R003.08F 2N7002BKS-GP-U SG
D S

DIS_1D05V_VGA_S0
1 S

2 G

3 D
84.2N702.E3F
1

1 2 1D5V_VGA_EN PD9302

2
22,27,92 DGPU_PWROK PR9326 2N7002BK-GP SG
0R0402-PAD-2-GP 1D5V_ENABLE 84.07002.I31 2 DY1 S G D PR9335
92 DGPU_PWR_EN 100KR2J-1-GP
A00_0803 X02_0615 SG
CH551H-30PT-GP

1
PR9327 1 SG 21KR2J-1-GP 1D05V_VGA_EN
22,27,92 DGPU_PWROK
1D05V_ENABLE

D
X02_0615

1
PC9330
SCD1U25V2KX-GP SG
G 1D05V_VGA_EN#

2
SG
PQ9308
A A
2N7002BK-GP

S
84.07002.I31

DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DISCRETE VGA POWER
Size Document Number Rev
A2 BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 93 of 106
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

DMB50
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 94 of 106

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

DMB50
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 95 of 106

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

(Blanking)

B B

A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 96 of 106
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface
X01_0508
DCBATOUT DCBATOUT DCBATOUT DCBATOUT
On the TOP side
Vinafix.com
5V_S5 3D3V_S5
HS1
SPR1
1

1
EC9701 EC9702 EC9704 H1 H8
EC9703 STF237R148H67-GP SPRING-13-GP-U
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
EC9706 HOLE256R115-GP HOLE197R166-1-GP
D SCD1U50V3KX-GP 1 2 D
2

1
SCD1U16V2KX-3GP
X02_0615

1
X02_0619

HS2 X01_0412
STF237R148H67-GP H2 H9
X01_0430 HOLE256R115-GP HOLE197R166-1-GP

1
+PW R_SRC_1D05V

1
1

EC9705
SCD1U25V2KX-GP
2

HS3
STF237R117H83-1-GP H3 H10
HOLE237R95-GP HOLE197R166-1-GP

1
C C

1
HS4
STF237R117H83-1-GP
H4 H11
HOLE256R115-GP HOLET335B131R115-GP

1
H5 H12
HOLE335R115-GP HOLE237R95-GP

1
B B

H6 H13
HOLE335R115-GP HOLE237R95-GP

1
H7
H14
HT85BE95R29-U-5-GP HOLE237R95-GP

1
A DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A3 A00
BMW Z5 DIS
Date: Tuesday, August 14, 2012 Sheet 97 of 106
5 4 3 2 1
 5 4 3 2 1

Chief River Platform Power Sequence

(AC mode) Red Words: Controlled by EC GPIO
(DC mode) Red Words: Controlled by EC GPIO

+RTC_VCC t01 >9ms

+RTC_VCC
t01 >9ms
RTC_RST#
RTC_RST#

Within logic high level and disable if

it is less than the logic low level.
DCBATOUT

3D3V_AUX_S5
Vinafix.com DCBATOUT

3D3V_AUX_S5
KBC GPIO34 control power on by 3V_5V_EN
D D
S5_ENABLE Sense the power button status Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
Ta 5V_S5
V5REF_Sus must be powered up before PSL_OUT#(GPIO71) keep low
VccSus3_3, or after VccSus3_3 within 3D3V_S5 Ta 3D3V_AUX_KBC
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS S5_ENABLE
KBC GPIO43 to PCH
PM_RSMRST#(EC Delay 40ms) t05 >10ms 5V_S5
PCH to KBC GPIO00 V5REF_Sus must be powered up before
5V_S5 & 3D3V_S5 need meet 0.7V difference
PCH_SUSCLK_KBC t07 >5ms VccSus3_3, or after VccSus3_3 within 3D3V_S5
0.7 V. Also, V5REF_Sus must power
KBC GPO84 to PCH down after VccSus3_3, or before
5V_S5 & 3D3V_S5 need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT 0ms<t08a<90ms +5VA_PCH_VCC5REFSUS Ta
KBC GPIO43 to PCH
PM_RSMRST#(RSMRST#_RST) t05 >10ms
In case of a non-Deep S4/S5 Platform
t07 >100ms PCH to KBC GPIO00
timing t42 should be added to t07
Press Power Button which will make it 100mS minimum.
PCH_SUSCLK_KBC
Platform to KBC PSL_IN2
Sense the power button status KBC GPIO20 to PCH
AC KBC_PWRBTN#
PM_PWRBTN#
This signal has an internal
pull-up resistor and has an KBC GPIO20 to PCH
internal 16 ms de-bounce on the
input. AC PM_PWRBTN#

DC PM_PWRBTN#
After Power Button After Power Button
PCH to KBC GPIO44 PCH to KBC GPIO44
PM_SLP_S4# PM_SLP_S4#
t10 PCH to KBC GPIO01 t10 PCH to KBC GPIO01
PM_SLP_S3# >30us PM_SLP_S3# >30us
KBC GPIO47 to LAN KBC GPIO47 to LAN
PM_LAN_ENABLE PM_LAN_ENABLE
Enable by PM_SLP_S4# Enable by PM_SLP_S4#
1D5V_S3 1D5V_S3

DDR_VREF_S3(0.75V) DDR_VREF_S3(0.75V)
C
5V_S0 & 3D3V_S0 need meet 0.7V difference 5V_S0 & 3D3V_S0 need meet 0.7V difference C

5V_S0 5V_S0
Tb
V5REF must be powered up before 3D3V_S0 V5REF must be powered up before 3D3V_S0
Vcc3_3, or after Vcc3_3 within 0.7 Vcc3_3, or after Vcc3_3 within 0.7
V. Also, V5REF must power down V. Also, V5REF must power down
after Vcc3_3, or before Vcc3_3 after Vcc3_3, or before Vcc3_3
within 0.7 V. +5VS_PCH_VCC5REF Tb within 0.7 V. +5VS_PCH_VCC5REF Tb

1D5V_S0 1D5V_S0

1D8V_S0 1D8V_S0
1D8V_S0 & 1D5V_S3 power ready 1D8V_S0 & 1D5V_S3 power ready
RUNPWROK RUNPWROK

1D05V_VTT 1D05V_VTT

1D05V_VTT_PWRGD 1D05V_VTT_PWRGD

0D75V_S0 0D75V_S0

0D85V_S0 0D85V_S0

0D85V_S0 0D85V_S0
D85V_PWRGD D85V_PWRGD

SetVID ACK SetVID ACK

CPU SVID BUS 50us< t36 <2000us CPU SVID BUS 50us< t36 <2000us

VCC_CORE VCC_CORE

VCC_GFXCORE VCC_GFXCORE
t37 t37
<5ms <5ms
IMVP_PWRGD IMVP_PWRGD

B B

PCH_CLOCK_OUT PCH_CLOCK_OUT

This signal represents the Power

ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH This signal represents the Power
ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH
Good for all the non-CORE and Good for all the non-CORE and
non-graphics power rails.
PWROK(S0_PWR_GOOD) non-graphics power rails.
PWROK(S0_PWR_GOOD)
t18 t18
D85V_PWRGD >0us PCH to CPU D85V_PWRGD >0us PCH to CPU
DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms
t19 >1ms t19 >1ms
t20 >2ms t20 >2ms
1D8V_S0 1D8V_S0
5ms<t13 <650ms PCH to CPU 5ms<t13 <650ms PCH to CPU
UNCOREPWRGOOD(H_CPUPWRGD) UNCOREPWRGOOD(H_CPUPWRGD)

SYS_PWROK t21+t22 >1ms+60us SYS_PWROK t21+t22 >1ms+60us

1ms< t25 <100ms PCH to all system 1ms< t25 <100ms PCH to all system
PLT_RST# PLT_RST#
t39 <200us t39 <200us
DMI DMI

N13M-GS Power-Up/Down Sequence

3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)

3D3V_VGA_S0(VDD33)

8209A_EN/DEM_VGA(Discrete only)
A A
VGA_CORE(NVVDD) tNVVDD >0ms
RT8208 PGOOD
DGPU_PWROK(Discrete only)

1D5V_VGA_S0(FBVDDQ) tNV-FBVDDQ >0ms

1D05V_VGA_S0(PEX_VDD) tNV-PEX_VDD >0ms

First rail to power down VGA_CORE,1D05V_VGA_S0

1D5V_VGA_S0,3D3V_VGA_S0 DMB50
Last rail to power down
tPOWER-OFF <10ms Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
For power-down, reversing the ramp-up sequence is recommended. Power Sequence
Size Document Number Rev
A1
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 98 of 106
5 4 3 2 1
 5 4 3 2 1

Wistron CHIEF RIVER POWER UP SEQUENCE DIAGRAM

-6
AC AD+
Adapter in
Page38
-3a
Vinafix.com
PWR_5V3D3V_ENC
-3a
3V_5V_EN
-3a
S5_ENABLE
D D

-3b -3c
PWR_CHG_ACOK
SWITCH ENC 5V_S5 15V_S5
Page40 LL1 PUMP
3D3V_S5
LL2
SWITCH
Page40 5V_AUX_S5
TPS51125RGER VREG5
DC/DC 3D3V_AUX_S5 -4
-5 (3V/5V) VREG3 3
DCBATOUT 3V_5V_POK PM_SLP_S4# 5V_S5 1D5V_S3
VIN PGOOD

Page41

DC 4
BT+ BQ24727 PM_SLP_S3# 5V_S0 VDDP VIN
Battery SWITCH
Charger
1D5V_S3 3a
Page39 -3 Page36 3 VTTREF
3D3V_AUX_KBC -3a PM_SLP_S4#
Page40 ACOK 3D3V_S0 EN
S5_ENABLE SWITCH
-6a Page36

AC_IN# GPIO34
1D5V_S0
TPS51216
GPIO70
SWITCH 4
Page36 0D75V_S0
VTT
C
1 SLP_S4# SLP_S3# PM_SLP_S3#
C

-1 KBC VTT_EN
KBC_PWRBTN#
GPIO6 NPCE885 -2 4a
9 AND GATE
Power Button PM_RSMRST# 0D75V_EN Page46
PM_SLP_S4# GPIO43 RSMRST# A VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD B
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD 5V_S5 3D3V_S5
Page27 Panther Point 10
GPIO77 PCH Ivy Bridge
8
15 CPU 4
VDD VIN
VOUT
1D8V_S0
S0_PWR_GOOD
Sequence: APWROK
PM_SLP_S3#
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
PWROK PLT_RST# BUF_CPU_RST# EN RT8068A
PLTRST# RSTIN# RUNPWROK
SYS_PWROK SVID PGD
SYS_PWROK Page47
5

SVID
14
11

B B

5V_S5
5V_S5 DCBATOUT

V5IN VIN 1D05_PCH/VCCP_CPU 5a

VOUT 11 VIN VCC_CORE
5 OUTPUT
SVID 12
RUNPWROK VT385 SVID VCC_GFXCORE
EN 1D05V_VTT_PWRGD OUTPUT
PGOOD
Page45 VT1318+VT1326
6 7 /VT1323
5b 14
D85V_PWRGD IMVP_VR_ON 13
VR_ON IMVP_PWRGD SYS_PWROK
Page42 & 43 & 44 PGOOD

5V_S5 DCBATOUT
-4
-7 3D3V_AUX_S5
5c RTC_AUX_S5
VDDP VIN 0D85_S0
5b VOUT -8
A APL5916 +RTC_VCC A
1D05VTT_PWRGD
EN D85V_PWRGD
Page48 PGOOD

RTC battery
6 DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Power Up Sequence: -8 ~ 15 Title

Taipei Hsien 221, Taiwan, R.O.C.

Power Sequence Diagram

Size Document Number Rev
A2
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 99 of 106
5 4 3 2 1
 5 4 3 2 1

Adapter AD+ SI7121DN DCBATOUT 3D3V_S5

TPS51225RUKR

Vinafix.com
SI7121DN
D D
Charger AO3404A AO4468 AO3404A RT8068AZQWID PA102FMG
BQ24707
Battery BT+
3D3V_S0 3D3V_WWAN_AOAC 1D8V_S0 3D3V_LAN_S5
3D3V_WLAN_AOAC

3D3V_AUX_S5 5V_PWR_2
15V_S5 (3D3V_PWR_2) ADP3211 G5285T11U RTS5179 DMP2130L AO4468 AR8161

LCDVDD 3D3V_CARD_S0 3D3V_VGA_S0 1D8V_VGA_S0 DVDDL

VGA_CORE
DMP2130L
C For Discrete For Discrete For Discrete C

3D3V_AUX_KBC

5V_S5

0D75V_S0
VT1318MFQ +
TPS2541RTER+ VT1326SFCX + AO4468 VT385FCX TPS51216
UP7534QRA8 VT1323SFCX DDR_VREF_S3

USB30_VCCx VCCP_CPU 1D5V_S3

VCC_CORE VCC_GFXCORE 5V_S0

B APL5916 AO4468 B

TPCA8062 AO4468
0D85V_S0 1V_VGA_S0

For Discrete 1D5V_S0 1D5V_VGA_S0

A Power Shape DMB50 A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Regulator LDO Switch Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Power Block Diagram
Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 100 of 106
5 4 3 2 1
 A B C D E

PCH SMBus Block Diagram 3D3V_S5 3D3V_S0 KBC SMBus Block Diagram
TP_VDD
‧ ‧
3D3V_S0 ‧
SRN2K2J-1-GP SRN2K2J-1-GP
‧

SMBCLK SMB_CLK
‧
Vinafix.com
‧ PCH_SMBCLK
DIMM 1
SCL
SRN10KJ-5-GP

1 SMBDATA SMB_DATA
‧ ‧ PCH_SMBDATA SDA
GPIO37/PSCLK1
0R2J-2-GP
TouchPad Conn. 1
TPCLK
‧ TPCLK_C TPCLK
3D3V_S5 0R2J-2-GP
SMBus Address:A0h GPIO35/PSDAT1 TPDATA
‧ TPDATA_C TPDATA
2N7002KDW
‧ 3D3V_AUX_KBC
DIMM 2
SRN2K2J-1-GP ‧PCH_SMBCLK SCL
‧
‧ PCH_SMBDATA SDA

SML0CLK SML0_CLK SRN4K7J-8-GP

SMBus Address:A4h
SML0DATA SML0_DATA

3D3V_S5 Minicard GPIO17/SCL1/N2TCK BAT_SCL

33R2J-2-GP
PBAT_SMBCLK1
Battery Conn.
‧
‧PCH_SMBCLK
WLAN
SMB_CLK
GPIO22/SDA1/N2TMS BAT_SDA
‧
33R2J-2-GP
PBAT_SMBDAT1
‧ SMBus address:16h
‧ PCH_SMBDATA SMB_DATA

SRN2K2J-1-GP
BQ24707
Minicard SCL

SML1CLK/GPIO58
‧ ‧ SML1_CLK GPIO73/SCL2
To KBC W-WAN KBC SDA

SML1DATA/GPIO75 ‧ ‧ SML1_DATA
GPIO74/SDA2 ‧PCH_SMBCLK
‧ PCH_SMBDATA
SMB_CLK

SMB_DATA
NPCE885PA0DX 3D3V_S5 3D3V_S0 SMBus address:12h
3D3V_VGA_S0 SRN2K2J-1-GP

‧
‧

‧
2
‧‧ TouchPad 2

SRN2K2J-1-GP
Conn.
SRN4K7J-8-GP

‧
PCH_SMBCLK SMB_CLK

‧
PCH_SMBDATA SMB_DATA Thermal IC
GPIO73/SCL2 SML1_CLK ‧ ‧ THM_SML1_CLK
NCT7718W
SCL
THM_SML1_DATA SDA
‧ GPIO_VGA_04_CLK GPIO_4_SMBCLK GPIO74/SDA2 SML1_DATA
‧ ‧
To GPU
‧ GPIO_VGA_03_DATA
GPIO_3_SMBDATA PCH_SMBCLK SMB_CLK

SMBus Address:41h PCH_SMBDATA SMB_DATA mSATA 2N7002KDW

SMBus address:99h/98h(R/W)
2N7002KDW

PCH 5V_HDMI_S0 ‧
SML1_CLK SML1CLK/GPIO58
PCH
3D3V_S0 ‧ SML1_DATA SML1DATA/GPIO75

‧ 3D3V_VGA_S0
‧
SRN2K2J-1-GP
3D3V_S0

‧
SRN2K2J-1-GP

‧
SRN2K2J-1-GP ‧

‧
SDVO_CTRLCLK PCH_HDMI_CLK
‧ ‧DDC_CLK_HDMI
SDVO_CTRLDATA
‧
PCH_HDMI_DATA
‧ DDC_DATA_HDMI HDMI CONN GPU
SML1_CLK ‧ I2CS_SCL
3
2N7002DW-1-GP
SML1_DATA
‧ ‧ I2CS_SDA
3

3D3V_S0

SRN2K2J-1-GP

SRN0J-6-GP
L_DDC_CLK LVDS_DDC_CLK_R
‧ LVDS_DDC_CLK_R_1

L_DDC_DATA LVDS_DDC_DATA_R
‧ LVDS_DDC_DATA_R_1 LCD CONN

4 4

DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram

Size Document Number Rev
A2 BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 101 of 106
A B C D E
 A B C D E

Thermal Block Diagram Audio Block Diagram

3D3V_S5 3D3V_S0
SRN2K2J-1-GP PAGE28

Vinafix.comCPU/SYSTEM

‧
‧

‧
SRN2K2J-1-GP
PAGE29
1 D+ NCT7718_DXP 1

Thermal

‧
PMBS3904-1-GP
SC2200P50V2KX-2GP SC470P50V3JN-2GP
NCT7718W

‧
D- NCT7718_DXN PORTA_L MIC_IN_L_R MIC_JACK_R
SML1_CLK
‧ ‧ THM_SML1_CLK SCL
3D3V_S0 PORTA_R
SML1_DATA
‧ ‧ THM_SML1_DATA SDA
VREFOUT_A AUD_VREFOUT_A
2K2R3F HP/MIC
2N7002KDW
2K2R2F-3-GP
PORTB_L AUD_HP1_JACK_L
Combo
PORTB_R AUD_HP1_JACK_R
2N7002K D PURE_HW_SHUTDOWN#
T_CRIT# THERM_SYS_SHDN#
S
3V_5V_EN
3D3V_VGA_S0 G 3D3V_S0
GPIO73/SCL2 GPIO74/SDA2

PAGE27
‧
Codec DMIC_CLK/GPIO1 AUD_DMIC_CLK_R Digital
IDT DMIC_0/GPIO2 AUD_DMIC_IN0_R
MIC
KBC PAGE86
92HD94
NPCE885P 2N7002
SMBC_Therm_NV I2CS_CLK
VGA
SMBD_Therm_NV I2CS_SDA

N13P-GV2
2 PORTD_+L AUD_SPK_L+ 2

PORTD_-L AUD_SPK_L-
GPIO94/DA0 GPIO56/TA1
FAN_TACH1

SPEAKER
FAN1_DAC

PORTD_+R AUD_SPK_R+

TACH PORTD_-R AUD_SPK_R-

FAN
5V_S0 VIN
FAN_VCC

VIN VSET VOUT

FAN CONTROL
G991P11U
PAGE28

3 3

4 4

DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Thermal/Audio Block Diagram
Document Number Rev
A2
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 102 of 106
A B C D E
 5 4 3 2 1

DATA PAGE Change Iteam Owner DATA PAGE Change Iteam

3/30 39 DY R3901, Stuff BATSW1 For PT Build EE 40 CHARGER :ADD GAP EG4010, EG4011, EG4012, EG4013 By EMC EMC

27 Change R2724 to 20KΩ For PT Build EE 41 PR4103 33KR2F-GP change to 35K7R2F-L-GP (64.35725.L0L)By Power team Power
Vinafix.com PR4102 120k change to 100KR2F-L2-GP(64.10035.L1L)
71 DY RN7101,R7101,R7102,R7103,DB1 For PT Build EE 41 By Power team Power
D D

69 Change R6909 Type to 0603 Prevent not enough power EE 92 PR9238=196k ohm , PR9225=2.26k ohm By Power team Power
PU9204, PU9205=SIR166DP-T1-GE3-GP(84.00166.037)
4/9 49 Change U4901 to 74.06288.B7F Sourcer provide EE 92 By Power team Power

4/12 49 LCD1 chanage to 20.F2101.030 By ME ME 47 Del EG4701,EG4702,EG4703,EG4704,EG4705,EG4706,EG4707 By EMC EMC

59 RJ45 change to 68.IH601.301 By ME ME 49 Swap LVDS1 signals for change LVDS1 CONN For correct Net EE

66 USB2 change to 22.10341.A81 By ME ME 4/25 59 Add XF5901 2nd source 68.69241.30C By EMC EMC

97 H3 change to ZZ.00PAD.921 By ME ME 1) change PR4236=953-->1.3kohm for VCC LL

42 2) change PR4239=300-->412ohm for VCCAXG LL Power
97 Add H12 , H13 to ZZ.00PAD.921 By ME ME By Power team
4/26 92 PR9225 change to 64.24915.6DL By Power team Power
97 Add SPR1 to 34.43E24.001 By ME ME
59 Change C5902 to 78.1013N.14L By Power team Power
8 Del C845, C849, C843, C821, C846, C848, C831 Avoid Through Gole EE
Change EG4010,EG4011,EG4012,EG4013 Location to EMC
C 4/13 27 R2713 change to 64.10025.6DL from 64.1002D.6DL For 0.1% ==> 1% ME 39.40 EG3910,EG3911,EG3912,EG3913 By EMC C

39 Add EG3914,EG3915 By EMC EMC

4/27 45 Del EG4529 By EMC EMC

4/17 31 Change Q3106 from 84.00102.031 to 84.02130.031 Merge source. EE
40 Change PC4019 to BT+_G By EMC EMC
62 Change TC6201,TC6303 to 78.10710.52L By EMC EMC
39 Change AFTP3905 to BT+_G By EMC EMC
18 Change C1801 to 78.10491.4FL Merge source EE
92 Change PR9238 to 0603 size By Power team Power
82 C8201=EC8201 , C8202=EC8202 By EMC EMC
4/30 60 RTC1 change to 62.70001.061 By ME ME
97 Add EC9701,EC9702,EC9703,EC9704 By EMC EMC
49 LCD1 change to 20.F2101.030 By ME ME
56 Add TP5601,TP5602,TP5603 By EMC EMC
70 LIDSW1 change to 74.05712.0BB By ME ME
41 Change PT4101,PT4103 to 77.52271.09L By EMC EMC
97 Add EC9705 to 78.10422.5FL By EMC EMC
41 EC4119=PC4119 By EMC EMC
B B
5/3 49 Delete EC4915 By EMC EMC
58 Change EC5801 to 83.00402.0A0 By EMC EMC
5/4 28 Change FAN1 to 20.F1295.003 By ME ME
42 Change PC4211 to 78.10523.5FL For Merge Source EE
47 Change PL4701 to 68.1R550.20F By Power team Power
46 Change PC4620 to 79.47719.2BL For Merge Source EE
56 Add TP5601,TP5602,TP5603 For Layout EE
58 Change to SPK1 to 20.F1639.004 By ME ME
Change and Stuff TR6301,TR6204,TR8201,TR8202 1st
4/18 41 Change PT4101,PT4103 to 77.22271.27L By EMC EMC 5/8 62,63,82 68.00201.241 , 2nd 69.10084.081 By EMC EMC

45 Change U4501 to 74.00386.03Z By Power team Power 82 Change EC8202 to 78.10423.2FL By EMC EMC

65 Change R6510 PH to 3D3V_S5 , Change R6613 PH to 3D3V_AUX_KBC Prevent Leackage EE 97 Stuff EC9701,EC9702,EC9703,EC9704,EC9705 By EMC EMC
EMC
4/20 51 Add ER5101,ER5102,ER5103,ER5104 By EMC 49 Change and Stuff TR4902 1st 69.10084.071 , 2rd 69.10080.021 By EMC EMC
C2937 C2938 C2939 C2950 C2951 C6501 C8432
29 C8434 Change to 78.10620.51L For Merge Source EE

A 4/23 82 Change TPAN1 to 20.F1876.006 By ME ME DMB50 A

4/24 45 1.05v :ADD GAP EG4527, EG4529, EG4528, EG4525, EG4522 By EMC EMC Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
43 CPU::ADD GAP EG4301, EG4302, EG4303,,EG4304, EG4305, EG4306, EG4307 By EMC EMC Taipei Hsien 221, Taiwan, R.O.C.

Title
44 GFX: ADD GAP EG4401, EG4402, EG4403, EG4404, EG4405, EG4406, EG4407 By EMC EMC
Change History
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 103 of 106
5 4 3 2 1
 5 4 3 2 1

DATA PAGE Change Iteam Version DATA PAGE Change Iteam

5/19 82 Change EC8202 P/N to 78.10421.2BL for correction Footprint EE 92 PL9201 change to 68.R2210.10N For 3mm H Power

6/05 27 Change R2724 P/N to 64.33025.6DL for correction PCB VERSION EE TPAD1 and LEDBD1 Change to 20.K0320.006 Follow Connector List ME
Vinafix.com
Change PR3801,R2301,R2304,R2412,R2702,R2940,R4912,R6606,R6607, 6/22 48 Change PU4801 to 74.05916.A31 for Reversion changed. Power
D 6/11 R8204 to 0603 short pad EE D

Delete TR8203,TR5101,TR5102,TR5104,TR5103,TR6501, EMC

TR6601.Follow PSE recommand.

Change PR4022,PR4116,PR4127,PR4130,PR4133,PR4207,PR4212,PR4219, EE 6/25 62,63 Delete TR6205,TR6206,TR6302,TR6303.Follow PSE recommand. EMC

PR4223,PR4228,PR4250,PR4251,PR4252,PR4253,PR4254,PR4261,PR4510,
PR4511,PR4522,PR4523,PR4607,PR4702,PR4801,PR4803,R1404,R1405, 62,63 Delete R6279,R6280,R6303,R6304,R4903,R4906,TR8204,ER8201, EMC
R1503,R1505,R1823,R1916,R1921,R1924,R1925,R1927,R1929,R2136,R2205, ER8202,ER8203,ER8204.Follow PSE recommand.
R2306,R2307,R2308,R2402,R2403,R2404,R2720,R2723,R2727,R2728,R2733,
6/11 R2764,R2765,R2767,R2768,R2778,R2792,R2794,R2807,R2813,R3113,R3614,
R3710,R4914,R4915,R504,R5125,R6202,R6203,R6204,R6205,R6281,R6282, 29 Add R2902,D2902 may replace by R2902 EE
R6283,R6284,R6305,R6306,R6307,R6308,R6502,R6505,R6616,R6810,R812,
R909 to 0402 short pad 69 Delete C6906 For new NET NAME EE

69 KB_LED_DET_C change to 20mil. EE

6/11 29 Change R2935 to 0805 short pad EE 69 AFTP78 conect to Q6901.D EE

56 Delete TP5601/5602/5603 , because no need. EE

Change RN2012 to 0402 short pad R2001,R2002. EE
C 6/11 20 Change RN2014 to 0402 short pad R2012,R2014. Change PR9238 to 174KΩ C
6/26 Change PC9210 to 680pF Power
Change RN2017 to 0402 short pad R2016,R2017.
Change PR4236 to 866Ω
Change PC4236 to 47pF
6/13 49 Change TR4902 to 69.10103.041 Change PC4218 to 1500pF
For Layout, Keep NO swap components so change orignal one EE Follow Power Team change

Change TR6204,TR6301 to 69.10080.021 6/28 28 Change U2802 from 74.00991.031 to 74.05606.A71.

62,63 For Layout, Keep NO swap components so change orignal one EE For 74.00991.031 life cycle status is obsoleted EE

20 Change R2001,R2002 to RN2012, 4P2R short pad EE 7/30 69 DY R6912 , R6908 change to short pad. DY R6904, Pop R6905. EE
21 RN2101 change to short pad 0R8P4R-PAD-1-G
20 Change R2012,R2014 to RN2014, 4P2R short pad EE 29 R2941 change to short pad
49 R4905 change to short pad
6/15 49 Change TR4902 to 1st 69.10080.021 , 2nd 69.10103.041 EE 58 R5808 change to short pad
92 PR9226, PR9227, PR9239 change to short pad
31 Add C3111 , Prevent PLT_RST#_LAN rise time fail. EE 93 PR9326 change to short pad
B B

69 Change Net Rule KB_BL_CTRL# to 20 mils EE

Common Part change 8/3 27 Change R2724 to 47kΩ for A00. EE

78.10321.2FL --> 78.10324.2FL
78.10423.2FL --> 78.10421.2FL 20 Change R2003 to short pad EE
78.10523.5BL --> 78.10521.2BL EE
84.2N702.031 --> 84.07002.I31 8/6 71 Change DB1 to ZZ.00PAD.Y41 EE
84.DM601.03F --> 84.2N702.E3F
Page40,41,42,43,44,45,46,48,39
Change Pad type, change to green cover type. EE
6/19 27 Add R2793 for new NETNAME KBC_BKLT connect to D4902.2 EE

49 Move L_BKLT_CTRL to D4902.1 EE Change ER8207,ER8208 to short pad. EE

49 Add D4902 and R4905. Add a new NETNAME EE 8/8 71 Change R6808,R6811 form 680Ω to 300Ω EE
BKLT_CTRL to replace L_BKLT_CTRL

A 97 Add EC9706 EMC DMB50 A

6/20 14,15 C1514 -->EC1514 EMC Wistron Corporation

C1424 -->EC1424 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
C1421 -->EC1421 Follow EMC request Taipei Hsien 221, Taiwan, R.O.C.

Title
6/21 49 Change U4901 to 74.05285.07F.Prevent LG Falling time Fail. EE
Change History
Size Document Number Rev
Change C4901 to EC4915. EMC A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 104 of 106
5 4 3 2 1
 5 4 3 2 1

DATA PAGE Change Iteam Version DATA PAGE Change Iteam

Vinafix.com
D D

C C

B B

A DMB50
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History
Size Document Number Rev
A3
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 105 of 106
 5 4 3 2 1
BMW Z5 DIS CLK Block Diagram
CPU PCH
Ivy Bridge Panther Point
D CK0
M_A_DIMA_CLK_DDR0

M_A_DIMA_CLK_DDR#0
Vinafix.com
SA_CK0
D
CK0# SA_CLK#0
DDR3 DIMM1
M_A_DIMA_CLK_DDR1 CLK_EXP_P
CK1 SA_CK1 BCLK CLKOUT_DMI_P
M_A_DIMA_CLK_DDR#1 CLK_EXP_N
CK1# SA_CLK#1 BCLK# CLKOUT_DMI_N

CLK_PCIE_WLAN#
CLKOUT_PCIE3N PIN 11
M_B_DIMB_CLK_DDR0
WLAN
CK0 SB_CK0 CLK_PCIE_WLAN
CLKOUT_PCIE3P PIN 13
M_B_DIMB_CLK_DDR#0
CK0# SB_CLK#0
DDR3 DIMM2
M_B_DIMB_CLK_DDR1
CK1 SB_CK1
M_B_DIMB_CLK_DDR#1
CK1# SB_CLK#1

CLK_PCIE_LAN
CLKOUT_PCIE5P PIN 19
C FBA_CLK0 CLK_PCIE_LAN#
C
CK0 CLKOUT_PCIE5N PIN 20
VRAM1 FBA_CLK0#
VGA
CK0#
N13P-GV2
LANXIN
CKXTAL1
ATHEROS
FBA_CLK0
CK0 FBA_CLK0 PEX_REFCLK#
CLK_PCIE_VGA#
CLKOUT_PEG_A_N
AR8161
FBA_CLK0#
VRAM2 CK0#
FBA_CLK0# X3101
25MHz
CLK_PCIE_VGA
PEX_REFCLK CLKOUT_PEG_A_P
LANXOUT
CKXTAL2
FBA_CLK1
CK0 27MHZ_IN
XTAL_IN
VRAM3 CK0#
FBA_CLK1#

X8601
27MHz
FBA_CLK1
CK0 FBA_CLK1
FBA_CLK1# 27MHZ_OUT
VRAM4 CK0#
FBA_CLK1# XTAL_OUT AUDIO
B HDA_BITCLK R2126 HDA_CODEC_BITCLK
IDT 92HD94 B
HDA_BCLK BITCLK
33R2J-2-GP

RTC_X1
RTCX1

X2101
KBC NUVOTON
32.768KHz
NPCE885P
RTC_X2 PCH_SUSCLK_KBC
RTCX2 SUSCLK/GPIO62 GPIO0/EXTCLK
Regulatory Model: P26F R1806 CLK_PCI_KBC
CLKOUT_PCI2 LCLK/GPIOF5
Regulatory Type: P26F001 22R2J-2-GP

XTAL25_IN
XTAL25_IN

CLK_PCI_FB_R R1805
X2001 CLKOUT_PCI1
25MHz 22R2J-2-GP

XTAL25_OUT CLK_PCI_FB
A XTAL25_OUT CLKIN_PCILOOPBACK A
DMB50

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CLK_DIAG
Size Document Number Rev
Custom
BMW Z5 DIS A00
Date: Tuesday, August 14, 2012 Sheet 106 of 106

5 4 3 2 1